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DIOT Monitoring Module
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21c51224
Commit
21c51224
authored
Dec 08, 2021
by
Christos Gentsos
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Main: revert Atmel START change in their I2C code that breaks our FW
parent
b8df1aa9
Pipeline
#2958
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in 0 seconds
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-13
hpl_sercom.c
main_fw/atmel_start_prj/hpl/sercom/hpl_sercom.c
+1
-13
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main_fw/atmel_start_prj/hpl/sercom/hpl_sercom.c
View file @
21c51224
...
...
@@ -1719,10 +1719,6 @@ int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const
NVIC_ClearPendingIRQ
((
IRQn_Type
)
_sercom_get_irq_num
(
hw
));
NVIC_EnableIRQ
((
IRQn_Type
)
_sercom_get_irq_num
(
hw
));
// Enable Address Match and PREC interrupt by default.
hri_sercomi2cs_set_INTEN_AMATCH_bit
(
hw
);
hri_sercomi2cs_set_INTEN_PREC_bit
(
hw
);
return
ERR_NONE
;
}
...
...
@@ -1925,14 +1921,7 @@ static void _sercom_i2c_s_irq_handler(struct _i2c_s_async_device *device)
if
(
flags
&
SERCOM_I2CS_INTFLAG_ERROR
)
{
ASSERT
(
device
->
cb
.
error
);
device
->
cb
.
error
(
device
);
}
if
(
flags
&
SERCOM_I2CS_INTFLAG_AMATCH
)
{
hri_sercomi2cs_clear_INTFLAG_AMATCH_bit
(
hw
);
}
if
(
flags
&
SERCOM_I2CS_INTFLAG_PREC
)
{
hri_sercomi2cs_clear_INTFLAG_PREC_bit
(
hw
);
}
if
(
flags
&
SERCOM_I2CS_INTFLAG_DRDY
)
{
}
else
if
(
flags
&
SERCOM_I2CS_INTFLAG_DRDY
)
{
if
(
!
hri_sercomi2cs_get_STATUS_DIR_bit
(
hw
))
{
ASSERT
(
device
->
cb
.
rx_done
);
device
->
cb
.
rx_done
(
device
,
hri_sercomi2cs_read_DATA_reg
(
hw
));
...
...
@@ -1940,7 +1929,6 @@ static void _sercom_i2c_s_irq_handler(struct _i2c_s_async_device *device)
ASSERT
(
device
->
cb
.
tx
);
device
->
cb
.
tx
(
device
);
}
hri_sercomi2cs_clear_INTFLAG_DRDY_bit
(
hw
);
#if (CONF_MCLK_LPDIV) != (CONF_MCLK_CPUDIV)
/* Adding grace time while waiting for SCL line to be released */
hri_sercomi2cs_clear_STATUS_reg
(
hw
,
0
);
...
...
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