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DIOT Monitoring Module
DIOT Monitoring Module
Commit 16f79f84 authored by Christos Gentsos's avatar Christos Gentsos
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PCB: add the design files for the fan tray variant

parent 17d20ae6
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    monimod-pcb/analog-fantray.sch 0 → 100644
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    monimod-pcb/connectors-fantray.sch 0 → 100644
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    monimod-pcb/connectors.sch
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    ......@@ -408,6 +408,8 @@ $Comp
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    ......
    monimod-pcb/cur_sense.sch
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    ......@@ -3,7 +3,7 @@ EELAYER 30 0
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    ......@@ -74,7 +77,10 @@ AR Path="/5D45F6B0/5E5793BC" Ref="R?" Part="1"
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    ......@@ -186,7 +195,10 @@ AR Path="/5D45F6B0/5E579418" Ref="R?" Part="1"
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    F 2 "Resistors SMD:RESC1608X55N" H 5150 3930 50 0001 L CNN
    F 3 " " H 5150 3855 50 0001 L CNN
    ......@@ -250,7 +262,10 @@ AR Path="/5D45F6B0/5E579457" Ref="#PWR?" Part="1"
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    ......@@ -265,7 +280,10 @@ AR Path="/5D45F6B0/5E57945D" Ref="#PWR?" Part="1"
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    ......@@ -282,7 +300,10 @@ AR Path="/5E539656/5E579489" Ref="C?" Part="1"
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    F 2 "Capacitors SMD:CAPC1608X87N" H 2250 3680 50 0001 L CNN
    F 3 " " H 2250 3605 50 0001 L CNN
    ......@@ -339,7 +360,10 @@ AR Path="/5E539656/5E579493" Ref="#PWR?" Part="1"
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    F 3 "" H 2250 4050 50 0001 C CNN
    ......@@ -405,7 +429,10 @@ AR Path="/5D45A59D/5E5DFFDB" Ref="TP?" Part="1"
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    F 0 "TP?" H 5500 3750 50 0000 C CNN
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    F 2 "Pads:TPS127" H 5500 3620 50 0001 L CNN
    F 3 " " H 5500 3545 50 0001 L CNN
    ......@@ -460,7 +487,10 @@ P 4100 3400
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    F 2 "ICs And Semiconductors SMD:SOT95P280X145-5N" H 4100 2580 50 0001 L CNN
    F 3 " " H 4100 2505 50 0001 L CNN
    ......
    monimod-pcb/fan_mosfets.sch
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    monimod-pcb/monimod-fantray-cache.lib 0 → 100644
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    monimod-pcb/monimod-fantray.kicad_pcb 0 → 100644
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    monimod-pcb/monimod-fantray.pro 0 → 100644
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    update=Wed Aug 18 17:47:13 2021
    version=1
    last_client=kicad
    [general]
    version=1
    RootSch=
    BoardNm=
    [cvpcb]
    version=1
    NetIExt=net
    [eeschema]
    version=1
    LibDir=
    [eeschema/libraries]
    [pcbnew]
    version=1
    PageLayoutDescrFile=
    LastNetListRead=
    CopperLayerCount=4
    BoardThickness=1.6
    AllowMicroVias=0
    AllowBlindVias=0
    RequireCourtyardDefinitions=0
    ProhibitOverlappingCourtyards=1
    MinTrackWidth=0.2
    MinViaDiameter=0.4
    MinViaDrill=0.3
    MinMicroViaDiameter=0.2
    MinMicroViaDrill=0.09999999999999999
    MinHoleToHole=0.25
    TrackWidth1=0.25
    TrackWidth2=0.25
    TrackWidth3=0.4
    TrackWidth4=0.5
    TrackWidth5=0.6
    TrackWidth6=0.8
    TrackWidth7=1.5
    ViaDiameter1=0.8
    ViaDrill1=0.4
    ViaDiameter2=0.8
    ViaDrill2=0.4
    ViaDiameter3=1.6
    ViaDrill3=0.8
    dPairWidth1=0.2
    dPairGap1=0.25
    dPairViaGap1=0.25
    SilkLineWidth=0.12
    SilkTextSizeV=1
    SilkTextSizeH=1
    SilkTextSizeThickness=0.15
    SilkTextItalic=0
    SilkTextUpright=1
    CopperLineWidth=0.2
    CopperTextSizeV=1.5
    CopperTextSizeH=1.5
    CopperTextThickness=0.3
    CopperTextItalic=0
    CopperTextUpright=1
    EdgeCutLineWidth=0.05
    CourtyardLineWidth=0.05
    OthersLineWidth=0.15
    OthersTextSizeV=1
    OthersTextSizeH=1
    OthersTextSizeThickness=0.15
    OthersTextItalic=0
    OthersTextUpright=1
    SolderMaskClearance=0
    SolderMaskMinWidth=0
    SolderPasteClearance=0
    SolderPasteRatio=-0
    [pcbnew/Layer.F.Cu]
    Name=F.Cu
    Type=0
    Enabled=1
    [pcbnew/Layer.In1.Cu]
    Name=In1.Cu
    Type=1
    Enabled=1
    [pcbnew/Layer.In2.Cu]
    Name=In2.Cu
    Type=1
    Enabled=1
    [pcbnew/Layer.In3.Cu]
    Name=In3.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In4.Cu]
    Name=In4.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In5.Cu]
    Name=In5.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In6.Cu]
    Name=In6.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In7.Cu]
    Name=In7.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In8.Cu]
    Name=In8.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In9.Cu]
    Name=In9.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In10.Cu]
    Name=In10.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In11.Cu]
    Name=In11.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In12.Cu]
    Name=In12.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In13.Cu]
    Name=In13.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In14.Cu]
    Name=In14.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In15.Cu]
    Name=In15.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In16.Cu]
    Name=In16.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In17.Cu]
    Name=In17.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In18.Cu]
    Name=In18.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In19.Cu]
    Name=In19.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In20.Cu]
    Name=In20.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In21.Cu]
    Name=In21.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In22.Cu]
    Name=In22.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In23.Cu]
    Name=In23.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In24.Cu]
    Name=In24.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In25.Cu]
    Name=In25.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In26.Cu]
    Name=In26.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In27.Cu]
    Name=In27.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In28.Cu]
    Name=In28.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In29.Cu]
    Name=In29.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.In30.Cu]
    Name=In30.Cu
    Type=0
    Enabled=0
    [pcbnew/Layer.B.Cu]
    Name=B.Cu
    Type=0
    Enabled=1
    [pcbnew/Layer.B.Adhes]
    Enabled=1
    [pcbnew/Layer.F.Adhes]
    Enabled=1
    [pcbnew/Layer.B.Paste]
    Enabled=1
    [pcbnew/Layer.F.Paste]
    Enabled=1
    [pcbnew/Layer.B.SilkS]
    Enabled=1
    [pcbnew/Layer.F.SilkS]
    Enabled=1
    [pcbnew/Layer.B.Mask]
    Enabled=1
    [pcbnew/Layer.F.Mask]
    Enabled=1
    [pcbnew/Layer.Dwgs.User]
    Enabled=1
    [pcbnew/Layer.Cmts.User]
    Enabled=1
    [pcbnew/Layer.Eco1.User]
    Enabled=1
    [pcbnew/Layer.Eco2.User]
    Enabled=1
    [pcbnew/Layer.Edge.Cuts]
    Enabled=1
    [pcbnew/Layer.Margin]
    Enabled=1
    [pcbnew/Layer.B.CrtYd]
    Enabled=1
    [pcbnew/Layer.F.CrtYd]
    Enabled=1
    [pcbnew/Layer.B.Fab]
    Enabled=1
    [pcbnew/Layer.F.Fab]
    Enabled=1
    [pcbnew/Layer.Rescue]
    Enabled=0
    [pcbnew/Netclasses]
    [pcbnew/Netclasses/Default]
    Name=Default
    Clearance=0.2
    TrackWidth=0.25
    ViaDiameter=0.8
    ViaDrill=0.4
    uViaDiameter=0.3
    uViaDrill=0.1
    dPairWidth=0.2
    dPairGap=0.25
    dPairViaGap=0.25
    monimod-pcb/monimod-fantray.sch 0 → 100644
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    monimod-pcb/monimod.kicad_pcb
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    monimod-pcb/temp_sense.sch
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    ......@@ -3,7 +3,7 @@ EELAYER 30 0
    EELAYER END
    $Descr A4 11693 8268
    encoding utf-8
    Sheet 14 14
    Sheet 12 14
    Title ""
    Date ""
    Rev "0.2p"
    ......
    monimod-pcb/uC-fantray.sch 0 → 100644
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    monimod-pcb/uC.sch
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    monimod-pcb/vin_div.sch
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    ......@@ -3,7 +3,7 @@ EELAYER 30 0
    EELAYER END
    $Descr A4 11693 8268
    encoding utf-8
    Sheet 7 14
    Sheet 8 14
    Title ""
    Date ""
    Rev "0.2p"
    ......
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