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DIOT Monitoring Module
DIOT Monitoring Module
Commit 0a190869 authored by Christos Gentsos's avatar Christos Gentsos
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RadTest: add the radiation test helper designs to the main repo

parent e0029814
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radiation_tests/PSI_June_2020/helper_designs/breakout_board/breakout_board.pro 0 → 100644
View file @ 0a190869
update=Mon Jun 8 16:49:33 2020
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
TrackWidth2=0.508
TrackWidth3=1.27
ViaDiameter1=1.4
ViaDrill1=0.7
ViaDiameter2=1.5
ViaDrill2=0.7
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.05
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.25
TrackWidth=0.25
ViaDiameter=1.4
ViaDrill=0.7
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
radiation_tests/PSI_June_2020/helper_designs/breakout_board/breakout_board.sch 0 → 100644
View file @ 0a190869
This source diff could not be displayed because it is too large. You can view the blob instead.
radiation_tests/PSI_June_2020/helper_designs/breakout_board/breakout_board.sch-bak 0 → 100644
View file @ 0a190869
This source diff could not be displayed because it is too large. You can view the blob instead.
radiation_tests/PSI_June_2020/helper_designs/breakout_board/fab/breakout_board-Edge_Cuts.gbr 0 → 100644
View file @ 0a190869
%TF.GenerationSoftware,KiCad,Pcbnew,5.1.6*%
%TF.CreationDate,2020-06-11T15:53:18+02:00*%
%TF.ProjectId,breakout_board,62726561-6b6f-4757-945f-626f6172642e,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Profile,NP*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
G04 Created by KiCad (PCBNEW 5.1.6) date 2020-06-11 15:53:18*
%MOMM*%
%LPD*%
G01*
G04 APERTURE LIST*
%TA.AperFunction,Profile*%
%ADD10C,0.100000*%
%TD*%
G04 APERTURE END LIST*
D10*
X181610000Y-43180000D02*
X181610000Y-137160000D01*
X107950000Y-43180000D02*
X181610000Y-43180000D01*
X107950000Y-137160000D02*
X107950000Y-43180000D01*
X181610000Y-137160000D02*
X107950000Y-137160000D01*
M02*
radiation_tests/PSI_June_2020/helper_designs/breakout_board/fab/breakout_board-job.gbrjob 0 → 100644
View file @ 0a190869
{
"Header":
{
"GenerationSoftware":
{
"Vendor": "KiCad",
"Application": "Pcbnew",
"Version": "5.1.6"
},
"CreationDate": "2020-06-11T15:53:18+02:00"
},
"GeneralSpecs":
{
"ProjectId":
{
"Name": "breakout_board",
"GUID": "62726561-6b6f-4757-945f-626f6172642e",
"Revision": "rev?"
},
"Size":
{
"X": 73.760,
"Y": 94.080
},
"LayerNumber": 2,
"BoardThickness": 1.600
},
"DesignRules":
[
{
"Layers": "Outer",
"PadToPad": 0.250,
"PadToTrack": 0.250,
"TrackToTrack": 0.250,
"MinLineWidth": 0.250,
"TrackToRegion": 0.508,
"RegionToRegion": 0.508
}
],
"FilesAttributes":
[
{
"Path": "breakout_board-F_Cu.gbr",
"FileFunction": "Copper,L1,Top",
"FilePolarity": "Positive"
},
{
"Path": "breakout_board-B_Cu.gbr",
"FileFunction": "Copper,L2,Bot",
"FilePolarity": "Positive"
},
{
"Path": "breakout_board-Edge_Cuts.gbr",
"FileFunction": "Profile",
"FilePolarity": "Positive"
}
],
"MaterialStackup":
[
{
"Type": "Copper",
"Notes": "Layer F.Cu"
},
{
"Type": "Dielectric",
"Material": "FR4",
"Notes": "Layers L1/L2"
},
{
"Type": "Copper",
"Notes": "Layer B.Cu"
}
]
}
radiation_tests/PSI_June_2020/helper_designs/breakout_board/fab/breakout_board.drl 0 → 100644
View file @ 0a190869
M48
; DRILL file {KiCad 5.1.6} date Thu Jun 11 15:53:34 2020
; FORMAT={-:-/ absolute / metric / decimal}
; #@! TF.CreationDate,2020-06-11T15:53:34+02:00
; #@! TF.GenerationSoftware,Kicad,Pcbnew,5.1.6
FMAT,2
METRIC
T1C0.700
T2C0.900
T3C1.000
T4C1.200
T5C2.200
%
G90
G05
T1
X110.744Y-121.285
X116.459Y-104.14
X119.38Y-83.82
X119.634Y-110.236
X120.142Y-118.364
X120.878Y-86.334
X121.412Y-116.84
X121.793Y-96.393
X121.92Y-83.82
X122.555Y-85.664
X122.682Y-108.966
X123.825Y-123.952
X124.587Y-75.057
X125.222Y-105.156
X125.73Y-89.535
X126.365Y-111.125
X127.889Y-112.903
X128.778Y-101.6
X130.175Y-92.075
X131.064Y-115.189
X131.191Y-112.395
X131.306Y-94.996
X132.804Y-110.655
X132.969Y-54.737
X132.969Y-59.563
X135.636Y-102.997
X139.7Y-79.502
X146.939Y-89.789
X150.114Y-125.857
X152.654Y-103.251
X152.654Y-112.268
X154.94Y-81.858
X155.078Y-126.466
X157.607Y-78.232
X158.75Y-52.832
X158.877Y-49.53
X161.739Y-102.3
X162.626Y-119.38
X162.626Y-121.158
X163.388Y-102.235
X164.059Y-113.765
X164.084Y-87.376
X164.465Y-74.041
X164.592Y-107.823
X165.42Y-75.753
X165.608Y-111.76
X165.862Y-105.791
X166.059Y-124.718
X166.116Y-87.122
X166.497Y-64.897
X166.792Y-122.286
X167.622Y-109.982
X168.021Y-89.789
X168.021Y-94.996
X168.021Y-97.282
X168.021Y-116.205
X168.148Y-108.204
X168.27Y-105.897
X168.275Y-79.248
X168.529Y-101.092
X168.656Y-129.54
X171.45Y-127.762
X172.212Y-130.302
X173.99Y-80.01
X176.53Y-76.2
X176.911Y-67.564
T2
X145.796Y-116.967
X149.606Y-116.967
X145.796Y-96.647
X149.606Y-96.647
X145.796Y-106.807
X149.606Y-106.807
X168.656Y-132.588
X171.196Y-132.588
X173.736Y-132.588
X176.276Y-132.588
T3
X113.919Y-121.793
X113.919Y-124.333
X113.919Y-126.873
X116.459Y-121.793
X116.459Y-124.333
X116.459Y-126.873
X170.18Y-81.28
X170.18Y-83.82
X170.18Y-86.36
X170.18Y-88.9
X170.18Y-91.44
X170.18Y-93.98
X170.18Y-96.52
X170.18Y-99.06
X172.72Y-81.28
X172.72Y-83.82
X172.72Y-86.36
X172.72Y-88.9
X172.72Y-91.44
X172.72Y-93.98
X172.72Y-96.52
X172.72Y-99.06
X113.919Y-110.363
X113.919Y-112.903
X113.919Y-115.443
X116.459Y-110.363
X116.459Y-112.903
X116.459Y-115.443
X113.919Y-82.423
X113.919Y-84.963
X113.919Y-87.503
X116.459Y-82.423
X116.459Y-84.963
X116.459Y-87.503
X113.919Y-93.853
X113.919Y-96.393
X113.919Y-98.933
X116.459Y-93.853
X116.459Y-96.393
X116.459Y-98.933
X170.18Y-107.95
X170.18Y-110.49
X170.18Y-113.03
X170.18Y-115.57
X170.18Y-118.11
X170.18Y-120.65
X170.18Y-123.19
X170.18Y-125.73
X172.72Y-107.95
X172.72Y-110.49
X172.72Y-113.03
X172.72Y-115.57
X172.72Y-118.11
X172.72Y-120.65
X172.72Y-123.19
X172.72Y-125.73
T4
X139.7Y-50.8
X139.7Y-60.96
X149.86Y-50.8
X149.86Y-60.96
X114.3Y-50.8
X114.3Y-60.96
X124.46Y-50.8
X124.46Y-60.96
X165.1Y-50.8
X165.1Y-60.96
X175.26Y-50.8
X175.26Y-60.96
T5
X144.78Y-57.15
X119.38Y-57.15
X170.18Y-57.15
T0
M30
radiation_tests/PSI_June_2020/helper_designs/buck_patch/buck_patch.kicad_pcb 0 → 100644
View file @ 0a190869
This source diff could not be displayed because it is too large. You can view the blob instead.
radiation_tests/PSI_June_2020/helper_designs/buck_patch/buck_patch.kicad_pcb-bak 0 → 100644
View file @ 0a190869
This source diff could not be displayed because it is too large. You can view the blob instead.
radiation_tests/PSI_June_2020/helper_designs/buck_patch/buck_patch.pro 0 → 100644
View file @ 0a190869
update=Wed Jun 17 11:42:53 2020
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
TrackWidth2=0.508
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0.05
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
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