Power backplane V0.2 review
Items on discussion
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Power Integrity simulations -
Heat dissipation simulations -
Compliance to IPC class 3 -
Increase of safe areas and spacing to allow for degradation effects -
For better thermal behavior, should the power plane be on the outer layer, and with increased thickness (e.g. 70 or 100um); currently it is an internal layer at 35um
Comments
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DRC errors on stackup drawing -
Power supply connector is too close to the edge of the backplane, please compare with off the shelf Schroff backplane -
Elimination of sharp edges on copper areas (ex L2_PWR) -
Bottom layer: Elimination of the "islands" that are created between the pins of the UTIL1 and UTIL2 connectors -
PE/N/L silkscreen text should be in the back -
PE/N/L silkscreen text is pointing to wrong faston contacts. "L" is P1 contact, "N" is P2, "PE" is P3. You can also compare with off-the-shelf Schroff backplane -
Mark "top"/ "bottom" on the silkscreen -
Silkscreen "J2" on the top layer is on top of other writing -
Addition of a rectangle around PSU on the silkscreen of the bottom layer -
2 mounting holes with optional GND (to chassis earth) contact shall have the GND contact exposed in on the bottom layer only, not in the Top layer (see Main backplane, there is is done correctly). -
JP1 does not come from the CERN libraries, please change it for consistency - all components should come from the same set of libraries -
Util1, Util2 seem too close to each other for the connectors and cables to fit properly; to check with a mockup once the pcb is ready