Main backplane V0.1 review
New feature to be added
-
Length matching for clk lines between slots. In principle this does not require re-routing, as there is plenty of space around the n_CLK_P/N pairs on the respective layers to match all slots with the length of the last slot.
Comments
-
Align guide elements. -
Addition of a table with "Layer stack-up details", board dimensions and a mark for each layer; please refer to this project: https://edms.cern.ch/nav/P:EDA-03613:V0/P:EDA-03613:V0 -
Board thickness should be ¬4 mm -
DCR errors "two track errors too close". This should be coming from a rounding error, as the DRC and the track router use different algorithms. Would it still be possible to expand the distance between those signals, so that the DRC is clean? -
DCR errors "footprint has incorrect courtyard". Our colleague that used to work on KiCad will have a look at this. -
Skew matching for all diff pairs -
Generally please visually check all diff pairs, as the DRC is not too smart -
When the layout is finished, sprinkle the pcb with vias to stitch all GND layers together -
For the power aux slot and the power bushing connectors, thermal reliefs might be required around the pads. Currently only P2 (12V) in the power aux slot seem to have thermal reliefs. -
J25, J26 are too close to the edges; to be moved more inside -
PWRBTN_N is <0.5mm from the edge; rerouting if possible -
Addition of the guiding element on all the slots in the front between P3 and P4 and on slots 2-9 in the back; the element is mounted on the front of Slot 1, and it is marked as unmounted for the rest of the slots. This will change slightly the routing below the P4 connectors. -
Alignment of the height of the utility connector with the utility connectors of the power backplane -
Addition of fiducials -
Vias for +12V_Sense/RTN_Sense/RTM_SHARED_BUSn to be larger than the others to reflect bigger track size -
Improvement of Slot 6 length matching of MGT diff pairs(220mm vs 215mm) -
Moving of 5_CLK_P/N further form Vaux1 plane as there is space -
Top Silkscreen to be similar to the off-the-shelf backplane; mainly addition of: "DI/OT CPCI-serial 9 Slot backplane" (larger font) "Licensed under CERN OHL v.1.2” (smaller font) add slot number for each slot (1..9) above P6 mark "Fan tray", "PSU", "Aux", "Power Aux" connectors mark P5V, P12V, GND mark Layer number, or 'Top' -
Bottom silkscreen to be similar to the off-the-shelf backplane; mainly addition of: add slot number for each slot (1..9) above P6 mark "Fan tray", "PSU", "Aux", "Power Aux" connectors mark P5V (instead of 5V), P12V mark Layer number, or 'Bottom'
Routing recommendations
-
Alignment of groups of vias, if possible; e.g. around X:100mm; Y:118mm and some other areas -
In locations where there is only 1 signal line/diff pair routed between connector pads, if possible make the routing in the middle of the space between the connector pads (e.g. in Sig2 H2@J21 (P1 of Slot 6) RST line is very close to pads I1/J1/K1/L1 while could be routed in the middle between row 1 and row 2). -
Just to keep the pattern: in the distribution of diff pairs of P6, 1_DIFF_13_P/N can be moved from layer Sig3 to Sig1; same for 1_DIFF_14_P/N: moving from layer Sig5 to Sig3
Sig1:
-
SHARED_BUS_0 avoiding "going down" between Slot 1 and Slot 2 -
sig from K2@J8 is quite close to L2, to be moved further as there is space -
same for sig left from H2@J8 -
(X:152 Y:106): improvement of transition meander between sig1 and sig5 before vias; it could be straight to vias and then sig5
Sig2:
-
Improvement of track shape at I2@J39 (P4 of Slot 7) -
Correction of routing of SHARED_BUS_2 H3@J41 (P1 of Slot 8); escape line not straight
Sig3:
-
(X:41.9 mm Y:140.11 mm): track angle improvement -
(X:264 mm Y: 124.24 mm): improvement of spacing as tracks are very close to each other; the same spacing like for neighboring tracks can be used -
(X:24 mm Y: 116 mm): moving track further away from the connector pads -
(X:186 mm Y: 136.45 mm): moving track further away from the connector pads; putting more in the middle between pads
Sig5:
-
(X:46 Y:60): moving of diff pair to Sig1, just for consistency
Bottom:
-
SHARED_BUS_3 to arrive to the center of J3@J41 (P1 of slot 8) -
Fixing of track shape right from C2@J12 (P4 of slot 3)
--------------- *** THANK YOU *** ---------------