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memory (GE property though). The possibilities can be remarkable.
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The CUTEWR-DP board can also be used as normal WR node when only one
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port is used. Check the
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[Github](https://github.com/leehongming/cutewr_dp) to get more
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port is used. Currently, the CUTEWR-DPV2 is published. Check the
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[Github](https://github.com/leehongming/cutewr_dp_v2) to get more
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information.
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## 2.Hardware
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- Spartan 6 (XC6SLX45T-4CSG324C);
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- 32MBit SPI FLASH (M25P32-VMF6P);
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- 64Kbit I2C EEPROM (24AA64T-I/MC);
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- FMC LPC interface;
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- FMC LPC interface following the VITA standard;
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- Addition Low-cost connector on FMC Region3
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- JTAG and RS232;
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- External CLK reference (work in master mode);
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- 2 USER IO on front panel, LEMO interface
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- 2 front panel LEDs;
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- 2 Pmod Interfaces for debug
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- 2 LEMO Interfaces for debug
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- 3 LEMO Interfaces for
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debug
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### 2.2 Design Files
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### 3.2 Design Files
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git clone --recursive https://github.com/leehongming/cutedp.git
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git clone --recursive https://github.com/leehongming/cutewr_dp_v2.git
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The branch master contains the project which supports the one port
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synchronization (normal CUTEWR).
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The branch master\_dp contains the project which supports the dual port
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synchronization (chain mode).
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## 4.Demo
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The Demo contains one WR switch and three CUTEWR-DP boards. The WR
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The Demo contains one WR switch and three CUTEWR-DPV2 boards. The WR
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switch acts as the Grandmaster(Layer 1) in this small network, and three
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CUTEWR-DP boards are connected one by one. They are in Layer 2/3/4 of
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CUTEWR-DPV2 boards are connected one by one. They are in Layer 2/3/4 of
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this network seperately.
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In each board, use the blue SFP (AXGE-1254-0531) in SFP0 and red SFP
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(AXGE-3454-0531) in SFP1. (The label of each SFP is on the PCB)
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<td>25-Jan-2017</td>
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<td>Publish the simple dual port demo</td>
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</tr>
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<tr class="odd">
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<td>04-Apr-2017</td>
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<td>Publish the CUTEWR-DPV2</td>
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</tr>
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</tbody>
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</table>
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| ... | ... | @@ -137,7 +147,3 @@ boards: |
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- [China Spallation Neutron
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Source](http://csns.ihep.ac.cn/english/index.htm)
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## 7\. Acknowledgements
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7s WR-LEN project
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