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## Introduction
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The Cute-WR-DP is the enhanced version of the [CUTE-WR-DP](https://www.ohwr.org/project/cute-wr-dp/wiki) with an Xilinx Artix7 series FPGA.
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The Cute-WR-A7 is the enhanced version of the [CUTE-WR-DP](https://www.ohwr.org/project/cute-wr-dp/wiki) with an Xilinx Artix7 series FPGA. It inherits similar interfaces with Cute-WR-DP: two SFP ports, two SMA/LEMO connectors, FMC form factor with LPC connector that is compatible with VITA-57 standard.
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**BELOW IS A TEMPLATE. PLEASE UPDATE**
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The three function modes of Cute-WR-DP is also possible on Cute-WR-A7:
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There are three function modes for Cute-WR-DP.
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1. **Normal mode (Cute-WR-DP-NM)**
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- In Normal mode, Cute-WR-DP acts as a normal WR node with one SFP
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1. **Normal mode (Cute-WR-A7-NM)**
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- In Normal mode, Cute-WR-A7 acts as a normal WR node with one SFP
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port (SFP0).
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2. **Cascade mode (Cute-WR-DP-CM)**
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2. **Cascade mode (Cute-WR-A7-CM)**
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- In CM mode, two ports act as one down-link (SFP1) and one
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up-link (SFP0) to support cascade topology. Two ports also
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support a simple switch function for normal Ethernet packets.
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3. **Parallel mode (Cute-WR-DP-PM)**
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3. **Parallel mode (Cute-WR-A7-PM)**
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- In PM mode both port act as down-link port connect to different
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WRS, provide redundancy to improve the reliability for safety
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related applications. The current firmware doesn't support this
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function.
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## Hardware
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![image](uploads/e8883c7811f9019eb7d42ee11dc86cbe/image.png)
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![](/uploads/c9c1d06426079bf7f5ff1b1fc5b0c25d/Cute-WR-DP__block_diagram.jpg.png)
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**Block diagram**
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**Cute-WR-A7 Block diagram**
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![](/uploads/11d4896e49baeec8c6e61c50b99e9a24/Cute-WR-DP2_s.jpg)
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**Cute-WR-DP**
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**Cute-WR-A7**
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## Hardware Features:
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