Implement 50Hz PPS-aligned PMU pulse

717c46cb · Dimitris Lampridis · e1e6b1cd · b1c8072c · 717c46cb · 717c46cb
Commit 717c46cb authored May 29, 2017 by Dimitris Lampridis
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Showing with 58 additions and 7 deletions

wr-cores hdl/ip_cores/wr-cores +1 -1

crio_wr_pmu.ucf hdl/syn/crio_wr_pmu/crio_wr_pmu.ucf +5 -3

crio_wr_pmu_top.vhd hdl/top/crio_wr_pmu/crio_wr_pmu_top.vhd +52 -3

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--- a/wr-cores @ b1c8072c
+++ b/wr-cores @ b1c8072c
-Subproject commit 3589794b7ba369849db05a4b75c4811c1c4b9e5b
+Subproject commit b1c8072cd4496a68f63373a0d6c52fac935fb2c1
--- a/hdl/syn/crio_wr_pmu/crio_wr_pmu.ucf
+++ b/hdl/syn/crio_wr_pmu/crio_wr_pmu.ucf
@@ -134,6 +134,11 @@ NET "led_3_o" IOSTANDARD = "LVCMOS33";
 NET "led_4_o" LOC = A18;
 NET "led_4_o" IOSTANDARD = "LVCMOS33";

+NET "userio_1_o" LOC = B2;
+NET "userio_1_o" IOSTANDARD = "LVCMOS33";
+NET "userio_2_o" LOC = A2;
+NET "userio_2_o" IOSTANDARD = "LVCMOS33";
+
 #NET "userio_1_p_b" LOC = B2;
 #NET "userio_1_p_b" IOSTANDARD = "LVDS_33";
 #NET "userio_1_n_b" LOC = A2;
@@ -190,6 +195,3 @@ INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit
 INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;

 TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;
-
-# Force PPS output to always be placed as IOB register
-#INST "cmp_board_common/cmp_xwr_core/WRPC/PPS_GEN/WRAPPED_PPSGEN/pps_out_o" IOB = FORCE;
--- a/hdl/top/crio_wr_pmu/crio_wr_pmu_top.vhd
+++ b/hdl/top/crio_wr_pmu/crio_wr_pmu_top.vhd
@@ -156,6 +156,8 @@ entity crio_wr_pmu_top is
    --userio_4_n_b : out std_logic;  -- CON730_4  front panel (DSUB HD15)
    --userio_5_p_b : out std_logic;  -- CON730_10 front panel (DSUB HD15), GCLK
    --userio_5_n_b : out std_logic;  -- CON730_5  front panel (DSUB HD15), GCLK
+    userio_1_o : out std_logic;  -- CON730_6 PPS output
+    userio_2_o : out std_logic;  -- CON730_1 PMU output (PPS-aligned)

    -- Front panel LEDs
    led_1_o : out std_logic;  -- LED750 (quad) front panel top
@@ -193,6 +195,8 @@ end entity crio_wr_pmu_top;

 architecture top of crio_wr_pmu_top is

+  attribute iob : string;
+
  -----------------------------------------------------------------------------
  -- Constants
  -----------------------------------------------------------------------------
@@ -287,6 +291,7 @@ architecture top of crio_wr_pmu_top is
  signal onewire_en : std_logic_vector(1 downto 0);

  -- WRPC
+  signal pps_csync     : std_logic;
  signal pps_pulse     : std_logic;
  signal pps_led       : std_logic;
  signal pps_led_ext   : std_logic;
@@ -296,6 +301,13 @@ architecture top of crio_wr_pmu_top is
  signal tm_tai        : std_logic_vector(39 downto 0);
  signal tm_cycles     : std_logic_vector(27 downto 0);

+  -- PMU
+  signal pmu_pulse : std_logic;
+
+  -- Force PPS and PMU pulses to IOBs
+  attribute IOB of pps_pulse : signal is "FORCE";
+  attribute IOB of pmu_pulse : signal is "FORCE";
+
 begin  -- architecture top

  ------------------------------------------------------------------------------
@@ -446,6 +458,7 @@ begin  -- architecture top
      tm_cycles_o          => tm_cycles,
      led_act_o            => led_act,
      led_link_o           => led_link,
+      pps_csync_o          => pps_csync,
      pps_p_o              => pps_pulse,
      pps_led_o            => pps_led);

@@ -526,9 +539,42 @@ begin  -- architecture top
      data_reg_scratch2_o => open
      );

-  ------------------------------------------------------------------------------
-  -- Front panel
-  ------------------------------------------------------------------------------
+  -----------------------------------------------------------------------------
+  -- PMU pulse generation
+  -- for now this is 50Hz, 50% duty cycle, in the future we can make
+  -- it configurable.
+  -- A better implementation could be to borrow the 10MHz
+  -- clock generation module from the WR Switch project, which makes use
+  -- of an OSERDES and ODELAY block (to allow fine alignment of the PMU pulse
+  -- to the actual PPS).
+  -- Don't forget to force the placement of the output to an IOB, to get
+  -- consistent timing.
+  -----------------------------------------------------------------------------
+  p_pmu_pulse_gen : process (clk_pll_125m) is
+    variable v_pmu_cnt : unsigned(21 downto 0);
+
+  begin  -- process p_pmu_pulse_gen
+    if rising_edge(clk_pll_125m) then
+      -- in case of reset, pps_csync or PMU pulse period
+      -- reset the counter, otherwise inc by 1
+      if (rst_ref_125m_n = '0') or (pps_csync = '1') or
+        (v_pmu_cnt = to_unsigned(2500000, v_pmu_cnt'length)) then
+        v_pmu_cnt := to_unsigned(1, v_pmu_cnt'length);
+      else
+        v_pmu_cnt := v_pmu_cnt + 1;
+      end if;
+      -- drive the PMU pulse based on the counter value
+      if v_pmu_cnt > to_unsigned(1250000, v_pmu_cnt'length) then
+        pmu_pulse <= '0';
+      else
+        pmu_pulse <= '1';
+      end if;
+    end if;
+  end process p_pmu_pulse_gen;
+
+------------------------------------------------------------------------------
+-- Front panel
+------------------------------------------------------------------------------

  cmp_extend_pps : gc_extend_pulse
    generic map (
@@ -546,4 +592,7 @@ begin  -- architecture top
  led_3_o <= not tm_time_valid;  -- LED is active L
  led_4_o <= not pps_led_ext;    -- LED is active L, at the bottom

+  userio_1_o <= pps_pulse;
+  userio_2_o <= pmu_pulse;
+
 end architecture top;