... | @@ -9,32 +9,36 @@ module. The module complies with NI CompactRIO specification (exceptions |
... | @@ -9,32 +9,36 @@ module. The module complies with NI CompactRIO specification (exceptions |
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see below).
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see below).
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https://www.ohwr.org/3300
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https://www.ohwr.org/3300
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*CRIO-WR 1.0 production board**
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*CRIO-WR 1.0 production
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board**
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https://www.ohwr.org/3300
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https://www.ohwr.org/3298
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*CRIO-WR module
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*CRIO-WR module
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prototype**
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prototype**
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-----
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## Block Diagram
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## Block Diagram
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![](/uploads/53e483d47e3d91b35f5ae1b607fcaa3b/crio-wr_1_00_block_diagram.png)
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![](/uploads/53e483d47e3d91b35f5ae1b607fcaa3b/crio-wr_1_00_block_diagram.png)
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The connector at the front panel provides 10 user I/O, connected
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CRIO-WR is originally derived from and keeps firmware compatibly with
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directly to the FPGA (i.e. programmable as input / output, LVDS / CMOS,
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the [SPEC](https://www.ohwr.org/project/spec/wiki) /
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SERDES etc.). The module is connected over SPI to the CompactRIO
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[CUTE-WR](https://www.ohwr.org/project/cute-wr/wiki) boards. The
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backplane/chassis/controller. The functionality in Labview is to read
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connector at the front panel provides 10 user I/O, connected directly to
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the status of a [White Rabbit (WR)
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the FPGA (i.e. programmable as input / output, LVDS / CMOS, SERDES
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link](https://www.ohwr.org/project/white-rabbit/wiki) /
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etc.). The module is connected over SPI to the CompactRIO
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WR-timecode validity, externally triggered WR-timestamps etc. into a
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backplane/chassis/controller. The functionality in Labview is for
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GUI, which is used for other slow control tasks using other cRIO
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example reading the status of WR-link, validity of WR-timecode and
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modules.
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externally triggered WR-timestamps.
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## Main Features
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-----
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*Sample text - to be replaced\>**
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## Main Features
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- VME64x interface
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- VME64x interface
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- Two Low-Pin Count FMC slots
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- 1x Xilinx Spartan6 FPGA (XC6SLX45T-3FGG484C)
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- 1x 32MBit SPI FLASH (M25P32-VMF6P)
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- Vadj fixed to 2.5V
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- Vadj fixed to 2.5V
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- No dedicated clock signals from Carrier to FMC (as only
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- No dedicated clock signals from Carrier to FMC (as only
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available on HPC pins and use LPC)
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available on HPC pins and use LPC)
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... | @@ -49,7 +53,7 @@ modules. |
... | @@ -49,7 +53,7 @@ modules. |
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- Configuration Flash memory for both Main FPGA and
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- Configuration Flash memory for both Main FPGA and
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Application FPGA configuration
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Application FPGA configuration
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- FPGA configuration
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- FPGA configuration
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- From SPI flash or via VME
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- From SPI flash or via JTAG
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- Clocking resources
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- Clocking resources
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- 1x 10-280 MHz I2C Programmable XO Oscillator, starts up at 100
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- 1x 10-280 MHz I2C Programmable XO Oscillator, starts up at 100
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MHz (Silicon Labs Si570, freely usable)
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MHz (Silicon Labs Si570, freely usable)
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