... | ... | @@ -54,11 +54,11 @@ CRIO-WR is based on a FPGA with WR PTP Core plus required hardware to |
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implement a standalone WR node.
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CompactRIO functionality is ensured by a dedicated power supply with
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sleep-mode, a separate EEPROM and an SPI plus some glue logic in the
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FPGA's CRIO User Core. A connector at the front panel provides up to 10
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user I/O signals (5 x LVDS) protected by TVS, programmable as input or
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output, with or without SERDES. The 4 LEDs at the front panel may be
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used as status
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sleep-mode, a separate EEPROM for module identification parameters and
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an SPI plus some glue logic in the FPGA's CRIO User Core. A connector at
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the front panel provides up to 10 user I/O signals (5 x LVDS) protected
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by TVS, programmable as input or output, with or without SERDES. The 4
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LEDs at the front panel may be used as status
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indicators.
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![](/uploads/53e483d47e3d91b35f5ae1b607fcaa3b/crio-wr_1_00_block_diagram.png)
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... | ... | @@ -73,7 +73,10 @@ More information: |
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## Main Features
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- VME64x interface
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- Standalone WR node (grand-master, master or slave)
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- Complies to NI CompactRIO specification, except for:
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- Current consumption (typ. 475 mA operational)
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- Power dissipation (typ. 2.4 W operational)
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- 1x Xilinx Spartan6 FPGA (XC6SLX45T-3FGG484C)
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- 1x 32MBit SPI FLASH (M25P32-VMF6P)
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- Vadj fixed to 2.5V
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