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# CompactRIO White Rabbit
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## Project description
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*Sample text - to be replaced\>**
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The crio-wr module is connected over SPI to the CRIO
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backplane/chassis/controller. The functionality in Labview is to read
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the status of a [White Rabbit (WR)
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link](https://www.ohwr.org/project/white-rabbit/wiki) /
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WR-timecode validity, externally triggered WR-timestamps etc. into a
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GUI, which is used for other slow control tasks using other cRIO
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modules.
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The module complies with the cRIO spec, except for current consumption
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and dissipation power. The connector at the front panel provides 10 user
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I/O, connected directly to the FPGA to be flexible (input / output, LVDS
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/ CMOS, SERDES
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etc.).
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[![](/project/white-rabbit/uploads/11578355de03b7cc74a366b23b508c48/svectop_s.png)](/project/white-rabbit/uploads/0eeb5b430351eca8a4e76a5af3892c2c/svectop_l.png)
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*SVEC V1 production board**
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## Main Features
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*Sample text - to be replaced\>**
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- VME64x interface
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- Two Low-Pin Count FMC slots
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- Vadj fixed to 2.5V
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- No dedicated clock signals from Carrier to FMC (as only
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available on HPC pins and use LPC)
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- FMC connectivity: all 34 differential pairs connected, 1 GTP
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transceiver with clock, 2 clock pairs, JTAG
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- Xilinx FPGAs
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- Application FPGA: Spartan-6 XC6SLX150T-FGG900
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- Direct connection to all resources such as VME64x, memories
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and FMC connectors
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- System FPGA: Spartan-6 XC6SLX9-2FTG256C
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- Provides VME bootloader, early oscillator/PLL config
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- Configuration Flash memory for both Main FPGA and
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Application FPGA configuration
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- FPGA configuration
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- From SPI flash or via VME
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- Clocking resources
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- 1x 10-280 MHz I2C Programmable XO Oscillator, starts up at 100
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MHz (Silicon Labs Si570, freely usable)
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- 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662,
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used by [White Rabbit PTP
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core](https://www.ohwr.org/wr-cores/wikis/Wrpc-core))
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- 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662,
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used by [White Rabbit PTP
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core](https://www.ohwr.org/wr-cores/wikis/Wrpc-core))
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- 2x low-jitter frequency synthesizer/fanout (TI CDCM61004, fixed
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configuration, Fout=125 MHz, used by [White Rabbit PTP
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core](https://www.ohwr.org/wr-cores/wikis/Wrpc-core))
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- On-board memories
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- 2x 256 MByte (2 Gbit) DDR3 (16-bit bus, MT41J128M16HA-15E)
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- 1x 128 Mbit SPI flash for FPGA firmware storage
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- 64kbit EEPROM (24AA64T-I/MC) connected for storing application
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parameters
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- 1x I2C configuration EEPROM (24LC64)
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- Miscellaneous
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- On-board thermometer IC (DS18B20U+)
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- Unique 64-bit identifier (DS18B20U+)
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- Front panel
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- 1x SFP port ([White
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Rabbit](https://www.ohwr.org/project/white-rabbit/wikis/)
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compatible)
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- 4x LEMO/SMC programmable I/Os capable of driving 3.3V @ 50 ohm
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- 2x mini displayPort connectors for high-speed serial GTP links
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(not for video)
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- 8x Programmable LED
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- Reset push button
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- Internal connectors
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- VME P2 connector provides access to a Rear Transition Module
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(compatible to
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[VFC](https://www.ohwr.org/project/fmc-vme-carrier/wiki))
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- 40 user defined single ended (Vcco=2.5V) signals (or 20 LVDS
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pairs) connected to the Application FPGA
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- 2x 125 MHz LVDS clocks provided to the RTM
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- Xilinx-style JTAG connector
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- Internal mini USB 2.0 High Speed connector for stand-alone
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applications (CP2103)
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- Optional features, check with vendor
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- Internal 2 x SATA connector for stand-alone PCI Express
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connectivity (clock + data)
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- Internal 4 x UFL connectors with low-jitter clock for FMC cards
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- Internal additional USB 2.0 on 4-pin header (FT2232HL)
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- Battery for secure storage of FPGA configuration data
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- Stand-alone features
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- External supply connector (3.3V, 5V) on internal SATA
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connector
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- PCIe interface on internal SATA connector
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- 10-layer PCB
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-----
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## Project information
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- Official production documentation:
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[EDA-0](http://edms.cern.ch/nav/eda-0)
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- [Users](Users)
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- [Software](Software)
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- [Frequently Asked Questions](FAQ)
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-----
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## Contacts
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### Commercial producers
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-
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### General question about project
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- [Daniel Florin](mailto:florin@physik.uzh.ch), Universitaet Zuerich,
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Switzerland.
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-----
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## Status
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<table>
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<tbody>
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<tr class="odd">
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<td><strong>Date</strong></td>
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<td><b> Event </b></td>
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</tr>
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<tr class="even">
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<td>19-07-2011</td>
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<td>Main features specification written.</td>
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</tr>
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</tbody>
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</table>
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-----
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30 July 2014
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