Adding first prototype Altium Files

77798839 · Carlos Gil Soriano · 151ac6a5 · 77798839 · 77798839 · 77798839
Commit 77798839 authored Jan 27, 2012 by Carlos Gil Soriano
94 changed files
--- a/pcb/CONV-TTL-RS485/Clocks&Monitor.SchDoc
+++ b/pcb/CONV-TTL-RS485/Clocks&Monitor.SchDoc
--- a/pcb/CONV-TTL-RS485/Communication.SchDoc
+++ b/pcb/CONV-TTL-RS485/Communication.SchDoc
--- a/pcb/CONV-TTL-RS485/FPGAbank01.SchDoc
+++ b/pcb/CONV-TTL-RS485/FPGAbank01.SchDoc
--- a/pcb/CONV-TTL-RS485/FPGAbank23.SchDoc
+++ b/pcb/CONV-TTL-RS485/FPGAbank23.SchDoc
--- a/pcb/CONV-TTL-RS485/FPGAps.SchDoc
+++ b/pcb/CONV-TTL-RS485/FPGAps.SchDoc
--- a/pcb/CONV-TTL-RS485/FrontPanelLeds.SchDoc
+++ b/pcb/CONV-TTL-RS485/FrontPanelLeds.SchDoc
--- a/pcb/CONV-TTL-RS485/FrontTTL.SchDoc
+++ b/pcb/CONV-TTL-RS485/FrontTTL.SchDoc
--- a/pcb/CONV-TTL-RS485/History/Clocks&Monitor.~(1).SchDoc.Zip
+++ b/pcb/CONV-TTL-RS485/History/Clocks&Monitor.~(1).SchDoc.Zip
--- a/pcb/CONV-TTL-RS485/History/Clocks&Monitor.~(2).SchDoc.Zip
+++ b/pcb/CONV-TTL-RS485/History/Clocks&Monitor.~(2).SchDoc.Zip
--- a/pcb/CONV-TTL-RS485/History/Communication.~(1).SchDoc.Zip
+++ b/pcb/CONV-TTL-RS485/History/Communication.~(1).SchDoc.Zip
--- a/pcb/CONV-TTL-RS485/History/FPGAbank01.~(1).SchDoc.Zip
+++ b/pcb/CONV-TTL-RS485/History/FPGAbank01.~(1).SchDoc.Zip
--- a/pcb/CONV-TTL-RS485/History/FPGAps.~(1).SchDoc.Zip
+++ b/pcb/CONV-TTL-RS485/History/FPGAps.~(1).SchDoc.Zip
--- a/pcb/CONV-TTL-RS485/History/FPGAps.~(3).SchDoc.Zip
+++ b/pcb/CONV-TTL-RS485/History/FPGAps.~(3).SchDoc.Zip
--- a/pcb/CONV-TTL-RS485/History/FrontPanelLeds.~(1).SchDoc.Zip
+++ b/pcb/CONV-TTL-RS485/History/FrontPanelLeds.~(1).SchDoc.Zip
--- a/pcb/CONV-TTL-RS485/History/JTAG&Button.~(1).SchDoc.Zip
+++ b/pcb/CONV-TTL-RS485/History/JTAG&Button.~(1).SchDoc.Zip
--- a/pcb/CONV-TTL-RS485/History/VME64xConn.~(1).SchDoc.Zip
+++ b/pcb/CONV-TTL-RS485/History/VME64xConn.~(1).SchDoc.Zip
--- a/pcb/CONV-TTL-RS485/History/VME64xConn.~(2).SchDoc.Zip
+++ b/pcb/CONV-TTL-RS485/History/VME64xConn.~(2).SchDoc.Zip
--- a/pcb/CONV-TTL-RS485/History/convTTLRS485.~(1).PrjPcb.Zip
+++ b/pcb/CONV-TTL-RS485/History/convTTLRS485.~(1).PrjPcb.Zip
--- a/pcb/CONV-TTL-RS485/History/convTTLRS485_top.~(1).SchDoc.Zip
+++ b/pcb/CONV-TTL-RS485/History/convTTLRS485_top.~(1).SchDoc.Zip
--- a/pcb/CONV-TTL-RS485/History/convTTLRS485_top.~(2).SchDoc.Zip
+++ b/pcb/CONV-TTL-RS485/History/convTTLRS485_top.~(2).SchDoc.Zip
--- a/pcb/CONV-TTL-RS485/History/convTTLRS485_top.~(3).SchDoc.Zip
+++ b/pcb/CONV-TTL-RS485/History/convTTLRS485_top.~(3).SchDoc.Zip
--- a/pcb/CONV-TTL-RS485/History/convTTLRS485_top.~(4).SchDoc.Zip
+++ b/pcb/CONV-TTL-RS485/History/convTTLRS485_top.~(4).SchDoc.Zip
--- a/pcb/CONV-TTL-RS485/History/convTTLRS485_top.~(5).SchDoc.Zip
+++ b/pcb/CONV-TTL-RS485/History/convTTLRS485_top.~(5).SchDoc.Zip
--- a/pcb/CONV-TTL-RS485/JTAG&Button.Harness
+++ b/pcb/CONV-TTL-RS485/JTAG&Button.Harness
+HEADER_TRIGGERS=FPGA_TRIG_LD_1,FPGA_TRIG_LD_2,FPGA_TRIG_LD_3,FPGA_TRIG_LD_4,FPGA_TRIG_LD_5,FPGA_TRIG_LD_6
--- a/pcb/CONV-TTL-RS485/JTAG&Button.SchDoc
+++ b/pcb/CONV-TTL-RS485/JTAG&Button.SchDoc
--- a/pcb/CONV-TTL-RS485/VME64xConn.SchDoc
+++ b/pcb/CONV-TTL-RS485/VME64xConn.SchDoc
--- a/pcb/CONV-TTL-RS485/convTTLRS485.PrjPcb
+++ b/pcb/CONV-TTL-RS485/convTTLRS485.PrjPcb
--- a/pcb/CONV-TTL-RS485/convTTLRS485.PrjPcbStructure
+++ b/pcb/CONV-TTL-RS485/convTTLRS485.PrjPcbStructure
+Record=TopLevelDocument|FileName=Clocks&Monitor.SchDoc
--- a/pcb/CONV-TTL-RS485/convTTLRS485_top.SchDoc
+++ b/pcb/CONV-TTL-RS485/convTTLRS485_top.SchDoc
--- a/pcb/proto1/History/Library_proto1.~(1).SchLib.Zip
+++ b/pcb/proto1/History/Library_proto1.~(1).SchLib.Zip
--- a/pcb/proto1/History/Proto1.~(1).SchDoc.Zip
+++ b/pcb/proto1/History/Proto1.~(1).SchDoc.Zip
--- a/pcb/proto1/History/Proto1.~(10).SchDoc.Zip
+++ b/pcb/proto1/History/Proto1.~(10).SchDoc.Zip
--- a/pcb/proto1/History/Proto1.~(11).SchDoc.Zip
+++ b/pcb/proto1/History/Proto1.~(11).SchDoc.Zip
--- a/pcb/proto1/History/Proto1.~(12).SchDoc.Zip
+++ b/pcb/proto1/History/Proto1.~(12).SchDoc.Zip
--- a/pcb/proto1/History/Proto1.~(13).SchDoc.Zip
+++ b/pcb/proto1/History/Proto1.~(13).SchDoc.Zip
--- a/pcb/proto1/History/Proto1.~(14).SchDoc.Zip
+++ b/pcb/proto1/History/Proto1.~(14).SchDoc.Zip
--- a/pcb/proto1/History/Proto1.~(15).SchDoc.Zip
+++ b/pcb/proto1/History/Proto1.~(15).SchDoc.Zip
--- a/pcb/proto1/History/Proto1.~(16).SchDoc.Zip
+++ b/pcb/proto1/History/Proto1.~(16).SchDoc.Zip
--- a/pcb/proto1/History/Proto1.~(2).SchDoc.Zip
+++ b/pcb/proto1/History/Proto1.~(2).SchDoc.Zip
--- a/pcb/proto1/History/Proto1.~(3).SchDoc.Zip
+++ b/pcb/proto1/History/Proto1.~(3).SchDoc.Zip
--- a/pcb/proto1/History/Proto1.~(4).SchDoc.Zip
+++ b/pcb/proto1/History/Proto1.~(4).SchDoc.Zip
--- a/pcb/proto1/History/Proto1.~(5).SchDoc.Zip
+++ b/pcb/proto1/History/Proto1.~(5).SchDoc.Zip
--- a/pcb/proto1/History/Proto1.~(6).SchDoc.Zip
+++ b/pcb/proto1/History/Proto1.~(6).SchDoc.Zip
--- a/pcb/proto1/History/Proto1.~(7).SchDoc.Zip
+++ b/pcb/proto1/History/Proto1.~(7).SchDoc.Zip
--- a/pcb/proto1/History/Proto1.~(8).SchDoc.Zip
+++ b/pcb/proto1/History/Proto1.~(8).SchDoc.Zip
--- a/pcb/proto1/History/Proto1.~(9).SchDoc.Zip
+++ b/pcb/proto1/History/Proto1.~(9).SchDoc.Zip
--- a/pcb/proto1/History/Proto1PCB.~(1).PcbDoc.Zip
+++ b/pcb/proto1/History/Proto1PCB.~(1).PcbDoc.Zip
--- a/pcb/proto1/History/Proto1PCB.~(10).PcbDoc.Zip
+++ b/pcb/proto1/History/Proto1PCB.~(10).PcbDoc.Zip
--- a/pcb/proto1/History/Proto1PCB.~(11).PcbDoc.Zip
+++ b/pcb/proto1/History/Proto1PCB.~(11).PcbDoc.Zip
--- a/pcb/proto1/History/Proto1PCB.~(12).PcbDoc.Zip
+++ b/pcb/proto1/History/Proto1PCB.~(12).PcbDoc.Zip
--- a/pcb/proto1/History/Proto1PCB.~(13).PcbDoc.Zip
+++ b/pcb/proto1/History/Proto1PCB.~(13).PcbDoc.Zip
--- a/pcb/proto1/History/Proto1PCB.~(14).PcbDoc.Zip
+++ b/pcb/proto1/History/Proto1PCB.~(14).PcbDoc.Zip
--- a/pcb/proto1/History/Proto1PCB.~(15).PcbDoc.Zip
+++ b/pcb/proto1/History/Proto1PCB.~(15).PcbDoc.Zip
--- a/pcb/proto1/History/Proto1PCB.~(16).PcbDoc.Zip
+++ b/pcb/proto1/History/Proto1PCB.~(16).PcbDoc.Zip
--- a/pcb/proto1/History/Proto1PCB.~(17).PcbDoc.Zip
+++ b/pcb/proto1/History/Proto1PCB.~(17).PcbDoc.Zip
--- a/pcb/proto1/History/Proto1PCB.~(2).PcbDoc.Zip
+++ b/pcb/proto1/History/Proto1PCB.~(2).PcbDoc.Zip
--- a/pcb/proto1/History/Proto1PCB.~(3).PcbDoc.Zip
+++ b/pcb/proto1/History/Proto1PCB.~(3).PcbDoc.Zip
--- a/pcb/proto1/History/Proto1PCB.~(4).PcbDoc.Zip
+++ b/pcb/proto1/History/Proto1PCB.~(4).PcbDoc.Zip
--- a/pcb/proto1/History/Proto1PCB.~(5).PcbDoc.Zip
+++ b/pcb/proto1/History/Proto1PCB.~(5).PcbDoc.Zip
--- a/pcb/proto1/History/Proto1PCB.~(6).PcbDoc.Zip
+++ b/pcb/proto1/History/Proto1PCB.~(6).PcbDoc.Zip
--- a/pcb/proto1/History/Proto1PCB.~(7).PcbDoc.Zip
+++ b/pcb/proto1/History/Proto1PCB.~(7).PcbDoc.Zip
--- a/pcb/proto1/History/Proto1PCB.~(8).PcbDoc.Zip
+++ b/pcb/proto1/History/Proto1PCB.~(8).PcbDoc.Zip
--- a/pcb/proto1/History/Proto1PCB.~(9).PcbDoc.Zip
+++ b/pcb/proto1/History/Proto1PCB.~(9).PcbDoc.Zip
--- a/pcb/proto1/History/Proto1_project.~(1).PrjPcb.Zip
+++ b/pcb/proto1/History/Proto1_project.~(1).PrjPcb.Zip
--- a/pcb/proto1/History/Proto1_project.~(2).PrjPcb.Zip
+++ b/pcb/proto1/History/Proto1_project.~(2).PrjPcb.Zip
--- a/pcb/proto1/History/Proto1_project.~(3).PrjPcb.Zip
+++ b/pcb/proto1/History/Proto1_project.~(3).PrjPcb.Zip
--- a/pcb/proto1/Library_proto1.SchLib
+++ b/pcb/proto1/Library_proto1.SchLib
--- a/pcb/proto1/Project Logs for Proto1_project/Proto1 SCH ECO 26-01-2012 12-07-24.LOG
+++ b/pcb/proto1/Project Logs for Proto1_project/Proto1 SCH ECO 26-01-2012 12-07-24.LOG
+Change Component Designator: Old Designator=C? New Designator=C1
+Change Component Designator: Old Designator=C? New Designator=C2
+Change Component Designator: Old Designator=C? New Designator=C3
+Change Component Designator: Old Designator=C? New Designator=C4
+Change Component Designator: Old Designator=IC? New Designator=IC3
+Change Component Designator: Old Designator=IC? New Designator=IC3
+Change Component Designator: Old Designator=IC? New Designator=IC3
+Change Component Designator: Old Designator=IC? New Designator=IC3
+Change Component Designator: Old Designator=IC? New Designator=IC1
+Change Component Designator: Old Designator=IC? New Designator=IC2
+Change Component Designator: Old Designator=IC? New Designator=IC4
+Change Component Designator: Old Designator=J? New Designator=J1
+Change Component Designator: Old Designator=J? New Designator=J2
+Change Component Designator: Old Designator=J? New Designator=J3
+Change Component Designator: Old Designator=J? New Designator=J4
+Change Component Designator: Old Designator=P? New Designator=P1
+Change Component Designator: Old Designator=P? New Designator=P2
+Change Component Designator: Old Designator=P? New Designator=P3
+Change Component Designator: Old Designator=R? New Designator=R1
+Change Component Designator: Old Designator=W? New Designator=W1
+Change Component Designator: Old Designator=W? New Designator=W2
+Change Component Designator: Old Designator=W? New Designator=W3
+Change Component Designator: Old Designator=W? New Designator=W4
+Change Component Designator: Old Designator=W? New Designator=W1
+Change Component Designator: Old Designator=W? New Designator=W2
+Change Component Designator: Old Designator=W? New Designator=W3
+Change Component Designator: Old Designator=W? New Designator=W4
--- a/pcb/proto1/Project Logs for Proto1_project/Proto1PCB PCB ECO 26-01-2012 12-19-43.LOG
+++ b/pcb/proto1/Project Logs for Proto1_project/Proto1PCB PCB ECO 26-01-2012 12-19-43.LOG
+Added Component: Designator=C1(CAPC3216X140N)
+Added Component: Designator=C2(CAPC3216X140N)
+Added Component: Designator=C3(CAPC3216X140N)
+Added Component: Designator=C4(CAPC3216X140N)
+Added Component: Designator=IC1(SOIC127P600X330-8N)
+Added Component: Designator=IC2(SOIC127P600X330-8N)
+Added Component: Designator=IC3(SOIC127P600X175-14N)
+Added Component: Designator=IC4(SOIC127P600X330-8N)
+Added Component: Designator=J1(LEMO_EPL.0S.302.HLN)
+Added Component: Designator=J2(LEMO_EPL.0S.302.HLN)
+Added Component: Designator=J3(LEMO_EPL.00.250.NTN)
+Added Component: Designator=J4(COMATEL_389.0358.1.06.400)
+Added Component: Designator=P1(TRIM_BOURNS_3266W)
+Added Component: Designator=P2(TRIM_BOURNS_3266W)
+Added Component: Designator=P3(TRIM_BOURNS_3266W)
+Added Component: Designator=R1(RESC3216X65N)
+Added Component: Designator=W1(COMATEL_385.0358.1.02.400)
+Added Component: Designator=W2(COMATEL_385.0358.1.02.400)
+Added Component: Designator=W3(COMATEL_385.0358.1.02.400)
+Added Component: Designator=W4(COMATEL_385.0358.1.02.400)
+Added Pin To Net: NetName=A_RX Pin=IC2-7
+Added Pin To Net: NetName=A_RX Pin=IC4-6
+Added Pin To Net: NetName=A_RX Pin=J2-1
+Added Pin To Net: NetName=A_RX Pin=P2-1
+Added Pin To Net: NetName=A_RX Pin=W4-1
+Added Net: Name=A_RX
+Added Pin To Net: NetName=A_TX Pin=J1-1
+Added Pin To Net: NetName=A_TX Pin=P1-2
+Added Pin To Net: NetName=A_TX Pin=W3-1
+Added Net: Name=A_TX
+Added Pin To Net: NetName=B_RX Pin=IC2-6
+Added Pin To Net: NetName=B_RX Pin=IC4-7
+Added Pin To Net: NetName=B_RX Pin=J2-2
+Added Pin To Net: NetName=B_RX Pin=P2-3
+Added Pin To Net: NetName=B_RX Pin=W4-2
+Added Net: Name=B_RX
+Added Pin To Net: NetName=B_TX Pin=J1-2
+Added Pin To Net: NetName=B_TX Pin=P3-2
+Added Pin To Net: NetName=B_TX Pin=W3-2
+Added Net: Name=B_TX
+Added Pin To Net: NetName=FAILSAFE Pin=IC3-3
+Added Pin To Net: NetName=FAILSAFE Pin=J4-5
+Added Net: Name=FAILSAFE
+Added Pin To Net: NetName=GND_RX Pin=C2-1
+Added Pin To Net: NetName=GND_RX Pin=C3-1
+Added Pin To Net: NetName=GND_RX Pin=C4-1
+Added Pin To Net: NetName=GND_RX Pin=IC2-2
+Added Pin To Net: NetName=GND_RX Pin=IC2-3
+Added Pin To Net: NetName=GND_RX Pin=IC2-5
+Added Pin To Net: NetName=GND_RX Pin=IC3-4
+Added Pin To Net: NetName=GND_RX Pin=IC3-5
+Added Pin To Net: NetName=GND_RX Pin=IC3-9
+Added Pin To Net: NetName=GND_RX Pin=IC3-10
+Added Pin To Net: NetName=GND_RX Pin=IC3-12
+Added Pin To Net: NetName=GND_RX Pin=IC3-13
+Added Pin To Net: NetName=GND_RX Pin=IC4-2
+Added Pin To Net: NetName=GND_RX Pin=IC4-3
+Added Pin To Net: NetName=GND_RX Pin=IC4-5
+Added Pin To Net: NetName=GND_RX Pin=J2-3
+Added Pin To Net: NetName=GND_RX Pin=J2-3
+Added Pin To Net: NetName=GND_RX Pin=J2-3
+Added Pin To Net: NetName=GND_RX Pin=J2-3
+Added Pin To Net: NetName=GND_RX Pin=J4-2
+Added Pin To Net: NetName=GND_RX Pin=J4-4
+Added Pin To Net: NetName=GND_RX Pin=J4-6
+Added Pin To Net: NetName=GND_RX Pin=P2-2
+Added Pin To Net: NetName=GND_RX Pin=W2-2
+Added Net: Name=GND_RX
+Added Pin To Net: NetName=GND_TX Pin=C1-1
+Added Pin To Net: NetName=GND_TX Pin=IC1-3
+Added Pin To Net: NetName=GND_TX Pin=IC1-5
+Added Pin To Net: NetName=GND_TX Pin=J1-3
+Added Pin To Net: NetName=GND_TX Pin=J1-3
+Added Pin To Net: NetName=GND_TX Pin=J1-3
+Added Pin To Net: NetName=GND_TX Pin=J1-3
+Added Pin To Net: NetName=GND_TX Pin=J3-2
+Added Pin To Net: NetName=GND_TX Pin=J3-2
+Added Pin To Net: NetName=GND_TX Pin=J3-2
+Added Pin To Net: NetName=GND_TX Pin=J3-2
+Added Pin To Net: NetName=GND_TX Pin=R1-1
+Added Pin To Net: NetName=GND_TX Pin=W1-2
+Added Net: Name=GND_TX
+Added Pin To Net: NetName=GND Pin=IC3-7
+Added Net: Name=GND
+Added Pin To Net: NetName=NetIC1_4 Pin=IC1-4
+Added Pin To Net: NetName=NetIC1_4 Pin=J3-1
+Added Pin To Net: NetName=NetIC1_4 Pin=R1-2
+Added Net: Name=NetIC1_4
+Added Pin To Net: NetName=NetIC1_6 Pin=IC1-6
+Added Pin To Net: NetName=NetIC1_6 Pin=P3-1
+Added Net: Name=NetIC1_6
+Added Pin To Net: NetName=NetIC1_7 Pin=IC1-7
+Added Pin To Net: NetName=NetIC1_7 Pin=P1-1
+Added Net: Name=NetIC1_7
+Added Pin To Net: NetName=RX2_TTL Pin=IC3-2
+Added Pin To Net: NetName=RX2_TTL Pin=IC4-1
+Added Pin To Net: NetName=RX2_TTL Pin=J4-3
+Added Net: Name=RX2_TTL
+Added Pin To Net: NetName=RX_TTL Pin=IC2-1
+Added Pin To Net: NetName=RX_TTL Pin=IC3-1
+Added Pin To Net: NetName=RX_TTL Pin=J4-1
+Added Net: Name=RX_TTL
+Added Pin To Net: NetName=VCC_RX Pin=C2-2
+Added Pin To Net: NetName=VCC_RX Pin=C3-2
+Added Pin To Net: NetName=VCC_RX Pin=C4-2
+Added Pin To Net: NetName=VCC_RX Pin=IC2-8
+Added Pin To Net: NetName=VCC_RX Pin=IC4-8
+Added Pin To Net: NetName=VCC_RX Pin=W2-1
+Added Net: Name=VCC_RX
+Added Pin To Net: NetName=VCC_TX Pin=C1-2
+Added Pin To Net: NetName=VCC_TX Pin=IC1-2
+Added Pin To Net: NetName=VCC_TX Pin=IC1-8
+Added Pin To Net: NetName=VCC_TX Pin=W1-1
+Added Net: Name=VCC_TX
+Added Pin To Net: NetName=VCC Pin=IC3-14
+Added Net: Name=VCC
+Added Class: Name=Proto1
+Added Room: Name=Proto1
--- a/pcb/proto1/Project Logs for Proto1_project/Proto1PCB PCB ECO 26-01-2012 17-32-35.LOG
+++ b/pcb/proto1/Project Logs for Proto1_project/Proto1PCB PCB ECO 26-01-2012 17-32-35.LOG
+Added Pin To Net: NetName=GND_RX Pin=IC3-7
+Added Pin To Net: NetName=VCC_RX Pin=IC3-14
+Added Member To Class: ClassName=Proto1 Member=Component IC2 SN65HVD3088ED
+Added Room: Name=Proto1
--- a/pcb/proto1/Project Logs for Proto1_project/Proto1PCB PCB ECO 26-01-2012 17-33-50.LOG
+++ b/pcb/proto1/Project Logs for Proto1_project/Proto1PCB PCB ECO 26-01-2012 17-33-50.LOG
+Removed Pin From Net: NetName=RX_TTL Pin=IC3-1
+Removed Pin From Net: NetName=RX2_TTL Pin=IC3-2
+Removed Pin From Net: NetName=FAILSAFE Pin=IC3-3
+Removed Pin From Net: NetName=GND_RX Pin=IC3-12
+Removed Pin From Net: NetName=GND_RX Pin=IC3-13
+Added Pin To Net: NetName=GND_RX Pin=IC3-1
+Added Pin To Net: NetName=GND_RX Pin=IC3-2
+Added Pin To Net: NetName=GND Pin=IC3-7
+Added Pin To Net: NetName=FAILSAFE Pin=IC3-11
+Added Pin To Net: NetName=RX_TTL Pin=IC3-12
+Added Pin To Net: NetName=RX2_TTL Pin=IC3-13
+Added Pin To Net: NetName=VCC Pin=IC3-14
--- a/pcb/proto1/Project Logs for Proto1_project/Proto1PCB PCB ECO 26-01-2012 17-36-13.LOG
+++ b/pcb/proto1/Project Logs for Proto1_project/Proto1PCB PCB ECO 26-01-2012 17-36-13.LOG
+Added Pin To Net: NetName=GND_RX Pin=IC3-7
+Added Pin To Net: NetName=VCC_RX Pin=IC3-14
+Change Net Name : Old Net Name=VCC_RX New Net Name=VCC
+Added Room: Name=Proto1
--- a/pcb/proto1/Project Logs for Proto1_project/Proto1PCB PCB ECO 26-01-2012 17-37-40.LOG
+++ b/pcb/proto1/Project Logs for Proto1_project/Proto1PCB PCB ECO 26-01-2012 17-37-40.LOG
+Removed Pin From Net: NetName=RX_TTL Pin=IC3-12
+Removed Pin From Net: NetName=RX2_TTL Pin=IC3-13
+Added Pin To Net: NetName=GND Pin=IC3-7
+Added Pin To Net: NetName=RX2_TTL Pin=IC3-12
+Added Pin To Net: NetName=RX_TTL Pin=IC3-13
+Added Room: Name=Proto1
--- a/pcb/proto1/Project Logs for Proto1_project/Proto1PCB PCB ECO 27-01-2012 9-52-43.LOG
+++ b/pcb/proto1/Project Logs for Proto1_project/Proto1PCB PCB ECO 27-01-2012 9-52-43.LOG
+Added Pin To Net: NetName=GND_RX Pin=IC3-7
+Change Net Name : Old Net Name=GND_RX New Net Name=GND
+Added Room: Name=Proto1
--- a/pcb/proto1/Project Outputs for Proto1_project/LPFKProto.LMD
+++ b/pcb/proto1/Project Outputs for Proto1_project/LPFKProto.LMD
--- a/pcb/proto1/Project Outputs for Proto1_project/LPFKProto.cam
+++ b/pcb/proto1/Project Outputs for Proto1_project/LPFKProto.cam
--- a/pcb/proto1/Project Outputs for Proto1_project/Proto1PCB-macro.APR_LIB
+++ b/pcb/proto1/Project Outputs for Proto1_project/Proto1PCB-macro.APR_LIB
--- a/pcb/proto1/Project Outputs for Proto1_project/Proto1PCB.DRL
+++ b/pcb/proto1/Project Outputs for Proto1_project/Proto1PCB.DRL
+TT#v  2  s k #v  2  s k #v  2  s k # 7 8 7 8 7 8 7 8 7 8 8 7 7 8 7 8 # 7 8 7 8 7 8 7 8 7 8 8 7 8 7 8 7 8 7 7 8 7 8 7 7 8 8 7 7 8 7 7 7 8 8 7 8 7 8 7  8 7 7 8 # 7 8 7  7 8 7 T 
\ No newline at end of file
--- a/pcb/proto1/Project Outputs for Proto1_project/Proto1PCB.DRR
+++ b/pcb/proto1/Project Outputs for Proto1_project/Proto1PCB.DRR
+---------------------------------------------------------------------------
+NCDrill File Report For: Proto1PCB.PcbDoc   27/01/2012  11:47:16
+---------------------------------------------------------------------------
+
+Layer Pair : Top Layer to Bottom Layer
+ASCII RoundHoles File : Proto1PCB.TXT
+EIA File   : Proto1PCB.DRL
+
+Tool         Hole Size           Hole Type     Hole Count Plated       Tool Travel
+---------------------------------------------------------------------------
+T1        31.5mil (0.8001mm)       Round          9                3.11 Inch (78.94 mm)
+T2        35.4mil (0.89916mm)      Round          31               9.84 Inch (249.96 mm)
+T3        126mil (3.2004mm)        Round          4                6.07 Inch (154.25 mm)
+---------------------------------------------------------------------------
+Totals                                            44               19.02 Inch (483.14 mm)
+
+Total Processing Time (hh:mm:ss) : 00:00:00
--- a/pcb/proto1/Project Outputs for Proto1_project/Proto1PCB.EXTREP
+++ b/pcb/proto1/Project Outputs for Proto1_project/Proto1PCB.EXTREP
+------------------------------------------------------------------------------------------
+Gerber File Extension Report For: Proto1PCB.GBR   27/01/2012  11:46:51
+------------------------------------------------------------------------------------------
+
+
+------------------------------------------------------------------------------------------
+Layer Extension     Layer Description                      
+------------------------------------------------------------------------------------------
+.GM1                Mechanical 1                            
+------------------------------------------------------------------------------------------
--- a/pcb/proto1/Project Outputs for Proto1_project/Proto1PCB.GM1
+++ b/pcb/proto1/Project Outputs for Proto1_project/Proto1PCB.GM1
+%FSLAX24Y24*%
+%MOIN*%
+G70*
+G01*
+G75*
+G04 Layer_Color=16711935*
+%ADD10C,0.0394*%
+D10*
+X9700Y29800D02*
+X40600D01*
+Y10100D02*
+Y29800D01*
+X9700Y10100D02*
+X40600D01*
+X9700D02*
+Y29800D01*
+M02*
--- a/pcb/proto1/Project Outputs for Proto1_project/Proto1PCB.GTL
+++ b/pcb/proto1/Project Outputs for Proto1_project/Proto1PCB.GTL
--- a/pcb/proto1/Project Outputs for Proto1_project/Proto1PCB.LDP
+++ b/pcb/proto1/Project Outputs for Proto1_project/Proto1PCB.LDP
+Layer Pairs Export File for PCB: D:\CERN\contrib\ohwr\conv-ttl-rs485\pcb\proto1\Proto1PCB.PcbDoc
+LayersSetName=Top_Bot_Thru_Holes|DrillFile=proto1pcb.txt|LayerPairs=gtl,gbl
--- a/pcb/proto1/Project Outputs for Proto1_project/Proto1PCB.REP
+++ b/pcb/proto1/Project Outputs for Proto1_project/Proto1PCB.REP
+*************************************************************
+FileName = Proto1PCB.GBR
+AutoAperture = True
+*************************************************************
+Generating : Mechanical 1
+      File : Proto1PCB.GM1
+
+    Adding Layer      : Mechanical 1
+
+
+Used DCodes :
+    D10
+*************************************************************
+
--- a/pcb/proto1/Project Outputs for Proto1_project/Proto1PCB.RUL
+++ b/pcb/proto1/Project Outputs for Proto1_project/Proto1PCB.RUL
+DRC Rules Export File for PCB: D:\CERN\contrib\ohwr\conv-ttl-rs485\pcb\proto1\Proto1PCB.PcbDoc
+RuleKind=ShortCircuit|RuleName=ShortCircuit|Scope=Board|Allowed=0
+RuleKind=Clearance|RuleName=Clearance|Scope=Board|Minimum=10.00
+RuleKind=Width|RuleName=Width|Scope=Board|Minimum=4.94
+RuleKind=SolderMaskExpansion|RuleName=SolderMaskExpansion|Scope=Board|Minimum=4.00
--- a/pcb/proto1/Project Outputs for Proto1_project/Proto1PCB.TXT
+++ b/pcb/proto1/Project Outputs for Proto1_project/Proto1PCB.TXT
+M48
+;Layer_Color=9474304
+;FILE_FORMAT=2:4
+INCH,LZ
+;TYPE=PLATED
+T1F00S00C0.0315
+T2F00S00C0.0354
+T3F00S00C0.1260
+%
+T01
+X037Y0175
+X038Y0185
+X037Y0195
+X018Y019
+X017Y02
+Y018
+X014
+X015Y019
+X014Y02
+T02
+X0145Y0115
+X0155Y0135
+X0145Y0145
+X0165Y0135
+X0175Y0145
+Y0115
+X028Y013
+X029
+Y014
+X028
+Y015
+X029
+X036Y0145
+X037Y0135
+X038
+X039Y0145
+Y0115
+X036
+X029Y022
+X028
+X024
+X023
+Y027
+Y028
+X029
+Y027
+X0125Y025
+X0105
+Y023
+X0125
+X0115Y024
+T03
+X019967Y01131
+X033707
+X039586Y028747
+X011
+M30
--- a/pcb/proto1/Project Outputs for Proto1_project/Proto1PCB.apr
+++ b/pcb/proto1/Project Outputs for Proto1_project/Proto1PCB.apr
+D10   ROUNDED            39.370      39.370       0.000  LINE       0.000
--- a/pcb/proto1/Project Outputs for Proto1_project/ProtoMech.cam
+++ b/pcb/proto1/Project Outputs for Proto1_project/ProtoMech.cam
--- a/pcb/proto1/Project Outputs for Proto1_project/ProtoTOP.cam
+++ b/pcb/proto1/Project Outputs for Proto1_project/ProtoTOP.cam
--- a/pcb/proto1/Project Outputs for Proto1_project/Status Report.Txt
+++ b/pcb/proto1/Project Outputs for Proto1_project/Status Report.Txt
+Output: NC Drill Files
+Type  : NC Drill
+From  : Project [Proto1_project.PrjPcb]
+   Generated File[Proto1PCB.TXT]
+   Generated File[Proto1PCB.DRL]
+   Generated File[Proto1PCB.LDP]
+   Generated File[Proto1PCB.DRR]
+
+
+Files Generated   : 4
+Documents Printed : 0
+
+Finished Output Generation At 11:47:16 On 27/01/2012
--- a/pcb/proto1/Proto1.SchDoc
+++ b/pcb/proto1/Proto1.SchDoc
--- a/pcb/proto1/Proto1PCB.PcbDoc
+++ b/pcb/proto1/Proto1PCB.PcbDoc
--- a/pcb/proto1/Proto1_project.PrjPcb
+++ b/pcb/proto1/Proto1_project.PrjPcb
--- a/pcb/proto1/Proto1_project.PrjPcbStructure
+++ b/pcb/proto1/Proto1_project.PrjPcbStructure
+Record=TopLevelDocument|FileName=Proto1.SchDoc