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Conv TTL RS485
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Conv TTL RS485
Commits
47ecbadb
Commit
47ecbadb
authored
Jan 22, 2015
by
Theodor-Adrian Stana
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cern-title.tex
doc/ug/cern-title.tex
+1
-1
front-panel.svg
doc/ug/fig/front-panel.svg
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invttl-chan.svg
doc/ug/fig/invttl-chan.svg
+60444
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oterm.svg
doc/ug/fig/oterm.svg
+202
-0
rear-panel.svg
doc/ug/fig/rear-panel.svg
+30
-17
ug-conv-ttl-rs485.tex
doc/ug/ug-conv-ttl-rs485.tex
+70
-34
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doc/ug/cern-title.tex
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47ecbadb
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@@ -9,7 +9,7 @@
\noindent
\rule
{
\textwidth
}{
.1cm
}
\hfill
August 12, 2014
\hfill
January 22, 2015
\vspace*
{
3cm
}
...
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doc/ug/fig/front-panel.svg
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doc/ug/fig/invttl-chan.svg
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doc/ug/fig/oterm.svg
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47ecbadb
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doc/ug/ug-conv-ttl-rs485.tex
View file @
47ecbadb
...
...
@@ -46,11 +46,26 @@
\include
{
cern-title
}
%------------------------------------------------------------------------------
%
Revision history
%
Licensing info
%------------------------------------------------------------------------------
\pagebreak
\addcontentsline
{
toc
}{
section
}{
Revision history
}
\thispagestyle
{
empty
}
\addcontentsline
{
toc
}{
section
}{
Licensing information
}
\section*
{
Licensing information
}
\noindent
This document is licensed under a Creative Commons Attribution-ShareAlike 4.0
International License. If you have not received a copy of the license along with this
work, see
\\
\url
{
http://creativecommons.org/licenses/by-sa/4.0/
}
%------------------------------------------------------------------------------
% Revision history
%------------------------------------------------------------------------------
\section*
{
Revision history
}
\addcontentsline
{
toc
}{
section
}{
Revision history
}
\centerline
{
...
...
@@ -63,6 +78,7 @@
12-08-2014
&
1.0
&
First release, after small error corrections (
\textit
{
writereg
}
instead of
\textit
{
readreg
}
in Section~
\ref
{
sec:diag-remote-reset
}
, and typo in Section~
\ref
{
sec:reprog-bitstreams
}
), and
addition of how to read gateware version in Section~
\ref
{
sec:reprog-bitstreams
}
\\
22-01-2015
&
1.1
&
\textcolor
{
red
}{
\textbf
{
WHAT?
}}
\\
\hline
\end{tabular}
}
...
...
@@ -120,27 +136,27 @@ pulses, or for timing distribution. The main features of the board are:
\item
RS-485 to TTL-BAR
\item
RS-485 to RS-485
\end{itemize}
\item
Four general-purpose inverter channels
\begin{itemize}
\item
TTL to TTL-BAR
\item
TTL-BAR to TTL
\end{itemize}
\item
Four general-purpose inverter channels, for conversion from TTL to TTL-BAR and viceversa
\item
Each TTL and inverter channel has 50~
$
\Omega
$
input termination
\item
Each TTL and inverter channel capable of driving 50~
$
\Omega
$
load
\item
Each RS-485 channel capable of driving up to 256 nodes
\item
Each RS-485 channel contains lack of signal detection logic
\item
SFP connector
\item
Diagnostics
\begin{itemize}
\item
converter board ID
\item
gateware version
\item
state of on-board switches and RTM detection lines
\item
line state at board input
\item
input pulse counters
\item
input pulse time-stamping with dedicated per-channel latest timestamp
readout
\item
manual pulse triggering
\item
remotely reset the FPGA logic
\end{itemize}
\item
Remote reprogramming over I
$^
2
$
C lines on VME P1 connector
\item
Status LEDs
\item
Pulse LEDs for each replication channel
\item
SFP connector
\end{itemize}
Pulse conversion is obtained by combining the CONV-TTL-RS485 front module (FM) board
...
...
@@ -192,7 +208,7 @@ It consists of several ports and status LEDs, which are detailed in the followin
subsections.
\begin{figure}
\centerline
{
\includegraphics
[scale=.
7
5]
{
fig/front-panel
}}
\centerline
{
\includegraphics
[scale=.
8
5]
{
fig/front-panel
}}
\caption
{
Front panel
}
\label
{
fig:fp
}
\end{figure}
...
...
@@ -209,25 +225,28 @@ LEDs are \textit{off}.
\centerline
{
\rowcolors
{
2
}{
white
}{
gray!25
}
\begin{tabular}
{
l p
{
.
75
\textwidth
}}
\begin{tabular}
{
l p
{
.
9
\textwidth
}}
\hline
\multicolumn
{
1
}{
c
}{
\textbf
{
LED
}}
&
\multicolumn
{
1
}{
c
}{
\textbf
{
Description
}}
\\
\hline
\textit
{
PW
}
&
Power LED
\newline
--
\textbf
{
Green
}
when a valid CONV-TTL-RS485 gateware is loaded
to the FPGA
\\
--
\textbf
{
Green
}
when a valid CONV-TTL-RS485 gateware is loaded to the FPGA
\\
\textit
{
ERR
}
&
Error LED
\newline
--
\textbf
{
Red
}
when a system error occured (see Section~
\ref
{
sec:diag-syserr
}
)
\newline
--
\textbf
{
Off
}
otherwise
\\
--
\textbf
{
Red
}
when a system error occured (see Section~
\ref
{
sec:diag-syserr
}
)
\\
\textit
{
I2C
}
&
I
$^
2
$
C status LED
\newline
--
\textbf
{
Flashes green
}
when an I
$^
2
$
C transfer takes places
\\
\textit
{
GF
}
&
Glitch filter state
\newline
--
\textbf
{
Green
}
when the pulse channel glitch filters are enabled
\\
\textit
{
ITERM
}
&
State of input terminations (Section~
\ref
{
sec:rp
}
)
\newline
--
\textbf
{
Green
}
when the channel input terminations are enabled via the
on-board enable switch (see Section~
\ref
{
sec:switches
}
)
\\
\textit
{
OTERM
}
&
State of output terminations (Section~
\ref
{
sec:rp
}
)
\newline
--
\textbf
{
Green
}
when the channel output terminations are enabled via the
on-board enable switch (see Section~
\ref
{
sec:switches
}
)
\\
\textit
{
TTL
}
&
TTL status LED
\newline
--
\textbf
{
Green
}
when TTL logic is selected via the on-board selection switch
\newline
--
\textbf
{
Green
}
when TTL logic is selected via the on-board selection switch
(see Section~
\ref
{
sec:switches
}
)
\newline
--
\textbf
{
Off
}
when TTL-BAR logic is selected.
\\
\textit
{
I2C
}
&
I
$^
2
$
C status LED
\newline
--
\textbf
{
Flashes green
}
when an I
$^
2
$
C transfer takes places
\newline
--
\textbf
{
Off
}
otherwise
\\
\textit
{
MULTICAST
}
&
Multicast switch status LEDs
\newline
--
\textbf
{
Green
}
when the corresponding multicast switch is ON
\newline
--
\textbf
{
Off
}
otherwise
\\
\hline
\end{tabular}
}
...
...
@@ -241,11 +260,12 @@ outputs can be either TTL or TTL-BAR, as selected by the TTL switch (SW2.4, see
Section~
\ref
{
sec:pulse-ttl-vs-ttlbar
}
).
A simplified diagram of pulse repetition is shown in Figure~
\ref
{
fig:ttl-chan
}
,
more details can be found in Section~
\ref
{
sec:pulse-rep
}
. If a TTL (TTL-BAR) pulse arrives
on a channel input, it is regenerated on the output of the same channel in TTL (TTL-BAR),
as well as the RS-485 outputs of the same channel on the rear panel, if an RTM
board with an attached RS-485 piggyback is present. Similarly, if an RS-485 pulse arrives
on the rear panel, it is replicated on the TTL output channel.
more details can be found in Section~
\ref
{
sec:pulse-rep
}
.
If a TTL (TTL-BAR) pulse arrives on a channel input, it is regenerated on the output of
the same channel in TTL (TTL-BAR), as well as the RS-485 outputs of the same channel on the
rear panel, if an RTM board with an attached RS-485 piggyback is present. Similarly, if an
RS-485 pulse arrives on the rear panel, it is replicated on the TTL output channel.
Each TTL replication channel has a pulse LED which flashes shortly whenever a pulse is replicated
on the channel.
...
...
@@ -254,7 +274,7 @@ All TTL input channels are terminated with 50$\Omega$ resistors; TTL output chan
not terminated.
\begin{figure}
[h]
\centerline
{
\includegraphics
[width=.
8
\textwidth]
{
fig/ttl-chan
}}
\centerline
{
\includegraphics
[width=.
5
\textwidth]
{
fig/ttl-chan
}}
\caption
{
Pulse repetition on front panel
}
\label
{
fig:ttl-chan
}
\end{figure}
...
...
@@ -267,11 +287,14 @@ No regeneration is performed on the input signal, nor is it in any way connected
on the RTM. The input signal is simply passed through an inverter and the FPGA, and presented at the
channel output.
Each INV-TTL channel has one LED which flashes shortly on every falling edge of the input
signal.
All general-purpose inputs are terminated with 50
$
\Omega
$
resistors; the outputs are not
terminated.
\begin{figure}
[h]
\centerline
{
\includegraphics
[width=.
6
\textwidth]
{
fig/invttl-chan
}}
\centerline
{
\includegraphics
[width=.
4
\textwidth]
{
fig/invttl-chan
}}
\caption
{
TTL general-purpose inverter channel
}
\label
{
fig:invttl-chan
}
\end{figure}
...
...
@@ -280,6 +303,7 @@ terminated.
% SUBSEC: Rear panel
%--------------------------------------------------------------------------------------
\subsection
{
Rear panel
}
\label
{
sec:rp
}
The rear panel on CONV-TTL-RTM-RS485 boards is shown in Figure~
\ref
{
fig:rear-panel
}
. It contains the
input and output connectors, as well as pulse status LEDs for the six RS-485 pulse channels. An RS-485
...
...
@@ -287,16 +311,28 @@ pulse at the input connector of a channel is passed through the FPGA and regener
of the same channel in RS-485 level, as well as in TTL level at the output connector of the corresponding
TTL channel on the front panel.
Each RS-485 output on a channel has its dedicated transceiver capable of driving 256 nodes.
When a pulse is repeated on the output connector of a channel, the pulse status LED flashes briefly.
\begin{figure}
[htbp]
\centerline
{
\includegraphics
[scale=.75]
{
fig/rear-panel
}}
\begin{figure}
[h]
\centerline
{
\includegraphics
[scale=.83]
{
fig/rear-panel
}}
\caption
{
Rear panel
}
\label
{
fig:rear-panel
}
\end{figure}
Each RS-485 output on a channel has its dedicated transceiver capable of driving 256 nodes. Additionally,
each input and output channel has a selectable 100~
$
\Omega
$
termination, which can be enabled by the
input and output termination switches (see Section~
\ref
{
sec:switches
}
). Setting the input or output
termination enable switch to the ON position enables a connection via a solid-state relay, which in turns
enables the termination connection as shown in Figures~
\ref
{
fig:iterm
}
~and~
\ref
{
fig:oterm
}
.
Finally, when a pulse is repeated on the output connector of a channel, the pulse status LED flashes briefly.
\begin{figure}
[h]
% \centerline{\includegraphics[width=.6\textwidth]{fig/iterm}}
% \caption{\label{fig:iterm} Input termination enable}
\centerline
{
\includegraphics
[width=.6\textwidth]
{
fig/oterm
}}
\caption
{
\label
{
fig:iterm
}
Output termination enable
}
\end{figure}
%======================================================================================
% SEC: Switches
%======================================================================================
...
...
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