[RS-485] Mainboard power-on reset circuit has long timing constant
The POR circuit on the RS-485 converter mainboards have 24.2s time constants. This POR circuit is only used for resetting the internal FPGA logic. The issue should be fixed in V2 by either:
- lowering the time constant (100ms should be a good starting point), or
- changing it with a button reset circuit, or
- removing it altogether and relying on internal logic reset from a
counter implemented in VHDL.
In the meantime, reset will be generated using a counter, similar to the V1 implementation, where a POR reset circuit was not included.