hdl: Negated RS-485 input line and added description in header of top-level file

56b56b7d · Theodor-Adrian Stana · 7a145ab6 · 56b56b7d
Commit 56b56b7d authored Nov 17, 2014 by Theodor-Adrian Stana
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Showing with 13 additions and 2 deletions

pts.vhd hdl/top/pts.vhd +13 -2

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--- a/hdl/top/pts.vhd
+++ b/hdl/top/pts.vhd
@@ -9,11 +9,22 @@
 --
 -- version: 1.0
 --
-- description:
+--    Top-level file of the HDL for the CONV-TTL-RS485 front-module PTS. All the
+--    modules used within the PTS are instantiated and connected here. The logic
+--    implemented here will work together with the PTS (Python) software.
 --
 -- dependencies:
+--    - converter board common gateware [1]
+--    - general-cores repository [2]
+--    - White Rabbit core collection [3]
 --
 -- references:
+--    [1] Converter board common gateware on OHWR,
+--        http://www.ohwr.org/projects/conv-common-gw/repository
+--    [2] Platform-independent core collection on OHWR,
+--        http://www.ohwr.org/projects/general-cores/repository
+--    [3] White Rabbit Core Collection on OHWR,
+--        http://www.ohwr.org/projects/wr-cores/repository
 --
 --==============================================================================
 -- GNU LESSER GENERAL PUBLIC LICENSE
@@ -1630,7 +1641,7 @@ end generate gen_other_front_pulse_logic;
  tester_ctrl <= tester_s1 & tester_s0 & tester_mux_en & tester_vcc;

  -- Assign rear panel inputs to local signals
-  rear_trigs_a <= rs485_n_i;
+  rear_trigs_a <= not rs485_n_i;

  -- And now generate the logic for six pulse rep channels
 gen_rear_test_logic : for i in 0 to 5 generate