Adding waveform files for ModelSim.

c0db0c26 · gilsoriano · 1ea34945 · c0db0c26 · c0db0c26
Commit c0db0c26 authored Aug 22, 2012 by gilsoriano
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wave.do hdl/m25p32/project/waveform/wave.do +90 -0

wave.do hdl/spi_master_multifield/project/waveform/wave.do +79 -0

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--- a/hdl/m25p32/project/waveform/wave.do
+++ b/hdl/m25p32/project/waveform/wave.do
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /m25p32_top_tb/uut/wb_rst_i
+add wave -noupdate /m25p32_top_tb/uut/wb_clk
+add wave -noupdate -divider -height 38 m25p32_core
+add wave -noupdate -expand -group SPI /m25p32_top_tb/uut/inst_m25p32_core/mosi_o
+add wave -noupdate -expand -group SPI /m25p32_top_tb/uut/inst_m25p32_core/miso_i
+add wave -noupdate -expand -group SPI /m25p32_top_tb/uut/inst_m25p32_core/sclk_o
+add wave -noupdate -expand -group SPI /m25p32_top_tb/uut/inst_m25p32_core/ss_n_o
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_db_i
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/addr_db_i
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/data_db_i
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/MEM_fsm
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/s_CTR0
+add wave -noupdate /m25p32_top_tb/uut/inst_m25p32_core/s_CTR1
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/s_FMOH
+add wave -noupdate /m25p32_top_tb/uut/inst_m25p32_core/s_SPI0
+add wave -noupdate /m25p32_top_tb/uut/inst_m25p32_core/s_SPI1
+add wave -noupdate /m25p32_top_tb/uut/inst_m25p32_core/s_SPI2
+add wave -noupdate /m25p32_top_tb/uut/inst_m25p32_core/s_SPI2_slv
+add wave -noupdate -divider spi_master_core
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_SPI0
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_SPI1
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_SPI2
+add wave -noupdate /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_STATUS
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/inst_i
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/addr_i
+add wave -noupdate -label PUSH_DATA -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_SPI1.PUSH_DATA
+add wave -noupdate -label PULL_DATA /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_STATUS.PULL_DATA
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/data_i
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_data_reg_o
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_inst_reg_o
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_addr_reg_o
+add wave -noupdate -radix unsigned /m25p32_top_tb/uut/inst_m25p32_core/inst_spi_master_core/s_spi_counter_cnt
+add wave -noupdate -group spi_buff -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/s_inst_spi
+add wave -noupdate -group spi_buff -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/s_addr_spi
+add wave -noupdate -group spi_buff -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/s_data_spi
+add wave -noupdate -group spi_buff_regs -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/s_inst_m25p32_regs
+add wave -noupdate -group spi_buff_regs -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/s_addr_m25p32_regs
+add wave -noupdate -group spi_buff_regs -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/s_data_m25p32_regs
+add wave -noupdate -group spi_buff_core -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_core/s_inst_m25p32_core
+add wave -noupdate -divider -height 38 m25p32_regs
+add wave -noupdate -group Wishbone /m25p32_top_tb/uut/inst_m25p32_regs/wb_we_i
+add wave -noupdate -group Wishbone /m25p32_top_tb/uut/inst_m25p32_regs/wb_stb_i
+add wave -noupdate -group Wishbone /m25p32_top_tb/uut/inst_m25p32_regs/wb_cyc_i
+add wave -noupdate -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_regs/wb_sel_i
+add wave -noupdate -group Wishbone -radix hexadecimal -radixenum symbolic /m25p32_top_tb/uut/inst_m25p32_regs/wb_data_i
+add wave -noupdate -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_regs/wb_data_o
+add wave -noupdate -group Wishbone -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_regs/wb_addr_i
+add wave -noupdate -group Wishbone /m25p32_top_tb/uut/inst_m25p32_regs/wb_ack_o
+add wave -noupdate -group Wishbone /m25p32_top_tb/uut/inst_m25p32_regs/wb_rty_o
+add wave -noupdate -group Wishbone /m25p32_top_tb/uut/inst_m25p32_regs/wb_err_o
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_regs/s_FMOH
+add wave -noupdate /m25p32_top_tb/uut/inst_m25p32_regs/s_CTR0
+add wave -noupdate /m25p32_top_tb/uut/inst_m25p32_regs/s_CTR1
+add wave -noupdate /m25p32_top_tb/uut/inst_m25p32_regs/s_CTR1_buff
+add wave -noupdate /m25p32_top_tb/uut/inst_m25p32_regs/s_SR_m25p32
+add wave -noupdate -divider m25p32_buff
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_regs/inst_tbuff/inst_i
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_regs/inst_tbuff/addr_i
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_regs/inst_tbuff/data_i
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_regs/inst_tbuff/inst_db_o
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_regs/inst_tbuff/addr_db_o
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_regs/inst_tbuff/s_CTR1
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_regs/inst_tbuff/s_DBUF
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/uut/inst_m25p32_regs/inst_tbuff/s_data_db
+add wave -noupdate -divider -height 38 m25p32_top_tb
+add wave -noupdate -radix hexadecimal /m25p32_top_tb/s_FMOH
+add wave -noupdate /m25p32_top_tb/s_inst_rcved
+add wave -noupdate /m25p32_top_tb/s_addr_rcved
+add wave -noupdate /m25p32_top_tb/s_data_rcved
+add wave -noupdate -divider serializer_sim
+add wave -noupdate /m25p32_top_tb/tester_uut/s_counter
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {120377115 ps} 0}
+configure wave -namecolwidth 274
+configure wave -valuecolwidth 88
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {444018750 ps}
--- a/hdl/spi_master_multifield/project/waveform/wave.do
+++ b/hdl/spi_master_multifield/project/waveform/wave.do
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /spi_master_core_tb/rst_i
+add wave -noupdate /spi_master_core_tb/clk_i
+add wave -noupdate -expand -group SPI -radix hexadecimal /spi_master_core_tb/spi_miso_i
+add wave -noupdate -expand -group SPI -radix hexadecimal /spi_master_core_tb/spi_mosi_o
+add wave -noupdate -expand -group SPI -radix hexadecimal /spi_master_core_tb/spi_clk_o
+add wave -noupdate -expand -group SPI -radix hexadecimal /spi_master_core_tb/spi_cs_n_o
+add wave -noupdate -radix hexadecimal /spi_master_core_tb/inst_i
+add wave -noupdate -radix hexadecimal /spi_master_core_tb/addr_i
+add wave -noupdate -radix hexadecimal /spi_master_core_tb/data_i
+add wave -noupdate -expand /spi_master_core_tb/uut/s_STATUS
+add wave -noupdate -radix hexadecimal /spi_master_core_tb/s_SPI0
+add wave -noupdate -radix hexadecimal /spi_master_core_tb/s_SPI1
+add wave -noupdate -expand -subitemconfig {/spi_master_core_tb/uut/s_SPI2.x {-height 17 -radix hexadecimal} /spi_master_core_tb/uut/s_SPI2.CLK_DIV {-height 17 -radix unsigned}} /spi_master_core_tb/uut/s_SPI2
+add wave -noupdate -group {Timing counter} /spi_master_core_tb/uut/s_timing_counter_en
+add wave -noupdate -group {Timing counter} /spi_master_core_tb/uut/s_timing_counter_manual_rst_i
+add wave -noupdate -group {Timing counter} /spi_master_core_tb/uut/s_timing_counter_rst_i
+add wave -noupdate -group {Timing counter} -radix unsigned /spi_master_core_tb/uut/s_timing_counter_cnt
+add wave -noupdate -expand -group {SPI counter} /spi_master_core_tb/uut/s_spi_counter_en
+add wave -noupdate -expand -group {SPI counter} /spi_master_core_tb/uut/s_spi_counter_manual_rst_clk
+add wave -noupdate -expand -group {SPI counter} -radix unsigned /spi_master_core_tb/uut/s_spi_counter_cnt
+add wave -noupdate -group {Clk divider} /spi_master_core_tb/uut/spi_cclk/clk_i
+add wave -noupdate -group {Clk divider} /spi_master_core_tb/uut/spi_cclk/rst_i
+add wave -noupdate -group {Clk divider} /spi_master_core_tb/uut/spi_cclk/oe_n_i
+add wave -noupdate -group {Clk divider} /spi_master_core_tb/uut/spi_cclk/clk_o
+add wave -noupdate -group {Clk divider} /spi_master_core_tb/uut/spi_cclk/s_clk_o
+add wave -noupdate -group {Clk divider} /spi_master_core_tb/uut/spi_cclk/divider_i
+add wave -noupdate -group {Clk divider} -radix unsigned /spi_master_core_tb/uut/spi_cclk/clk_i_count
+add wave -noupdate -group inst_fifo /spi_master_core_tb/uut/clk_i
+add wave -noupdate -group inst_fifo /spi_master_core_tb/uut/rst_i
+add wave -noupdate -group inst_fifo -label s_SPI1.PUSH_INST -radix hexadecimal /spi_master_core_tb/s_SPI1.PUSH_INST
+add wave -noupdate -group inst_fifo -label s_STATUS.PULL_INST /spi_master_core_tb/uut/s_STATUS.PULL_INST
+add wave -noupdate -group inst_fifo -radix hexadecimal /spi_master_core_tb/uut/inst_i
+add wave -noupdate -group inst_fifo -radix hexadecimal /spi_master_core_tb/uut/s_inst_reg_o
+add wave -noupdate -group addr_fifo /spi_master_core_tb/uut/clk_i
+add wave -noupdate -group addr_fifo /spi_master_core_tb/uut/rst_i
+add wave -noupdate -group addr_fifo -label s_SPI1.PUSH_ADDR -radix hexadecimal /spi_master_core_tb/s_SPI1.PUSH_ADDR
+add wave -noupdate -group addr_fifo -label s_STATUS.PULL_ADDR /spi_master_core_tb/uut/s_STATUS.PULL_ADDR
+add wave -noupdate -group addr_fifo -radix hexadecimal /spi_master_core_tb/uut/addr_i
+add wave -noupdate -group addr_fifo -radix hexadecimal /spi_master_core_tb/uut/s_addr_reg_o
+add wave -noupdate -group data_fifo /spi_master_core_tb/uut/clk_i
+add wave -noupdate -group data_fifo /spi_master_core_tb/uut/rst_i
+add wave -noupdate -group data_fifo -label s_SPI1.PUSH_DATA -radix hexadecimal /spi_master_core_tb/s_SPI1.PUSH_DATA
+add wave -noupdate -group data_fifo -label s_STATUS.PULL_DATA /spi_master_core_tb/uut/s_STATUS.PULL_DATA
+add wave -noupdate -group data_fifo /spi_master_core_tb/uut/data_i
+add wave -noupdate -group data_fifo /spi_master_core_tb/uut/s_data_reg_o
+add wave -noupdate /spi_master_core_tb/uut/s_STATUS_pull_byte_already
+add wave -noupdate -expand -group Testbench /spi_master_core_tb/s_rst_spi_analyser
+add wave -noupdate -expand -group Testbench /spi_master_core_tb/s_spi_count
+add wave -noupdate -expand -group Testbench /spi_master_core_tb/s_end_inst_flag
+add wave -noupdate -expand -group Testbench /spi_master_core_tb/s_end_addr_flag
+add wave -noupdate -expand -group Testbench /spi_master_core_tb/s_end_data_flag
+add wave -noupdate -expand -group Testbench -radix hexadecimal /spi_master_core_tb/inst_check
+add wave -noupdate -expand -group Testbench -radix hexadecimal /spi_master_core_tb/addr_check
+add wave -noupdate -expand -group Testbench -radix hexadecimal /spi_master_core_tb/data_check
+add wave -noupdate /spi_master_core_tb/uut/s_spi_clk
+add wave -noupdate /spi_master_core_tb/uut/s_spi_clk_d0
+add wave -noupdate /spi_master_core_tb/uut/s_spi_clk_n
+add wave -noupdate /spi_master_core_tb/uut/s_spi_clk_n_d0
+add wave -noupdate /spi_master_core_tb/uut/s_spi_clk_tmp
+add wave -noupdate /spi_master_core_tb/uut/s_spi_start_stop_spi_tx
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1023076 ps} 0}
+configure wave -namecolwidth 260
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {3482416 ps}