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Conv TTL Blocking
Commit 82641202 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Renamed pulse generators to ctb_pulse_gen[_gp] 

Also deleted old_rep_test folder and recompiled (and tested)
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hdl/old_rep_test/README.txt deleted 100644 → 0
View file @ a75842b3
This project is used to generate variable-length pulses for testing the old
repeater boards.
hdl/old_rep_test/rtl/pulse_gen.vhd deleted 100644 → 0
View file @ a75842b3
--==============================================================================
-- CERN (BE-CO-HT)
-- Test module for old repeater boards
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-02-28
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-02-28 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_gen is
generic
(
g_pwidth : natural := 200;
g_freq : natural := 400
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
pulse_o : out std_logic
);
end entity pulse_gen;
architecture behav of pulse_gen is
--============================================================================
-- Type declarations
--============================================================================
--============================================================================
-- Function and procedure declarations
--============================================================================
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
--============================================================================
-- Constant declarations
--============================================================================
--============================================================================
-- Component declarations
--============================================================================
--============================================================================
-- Signal declarations
--============================================================================
signal freq_cnt : unsigned(f_log2_size(g_freq)-1 downto 0);
signal pulse : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- I/O logic
--============================================================================
pulse_o <= pulse;
p_gen_pulse: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
freq_cnt <= (others => '0');
pulse <= '0';
else
freq_cnt <= freq_cnt + 1;
pulse <= '0';
if (freq_cnt < g_pwidth) then
pulse <= '1';
elsif (freq_cnt = g_freq-1) then
freq_cnt <= (others => '0');
end if;
end if;
end if;
end process p_gen_pulse;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
hdl/old_rep_test/sim/Makefile deleted 100644 → 0
View file @ a75842b3
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
## variables #############################
PWD := $(shell pwd)
MODELSIM_INI_PATH := /opt/modelsim_10.0d/modeltech
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := ../rtl/old_rep_test.vhd \
testbench.vhd \
VHDL_OBJ := work/old_rep_test/.old_rep_test_vhd \
work/testbench/.testbench_vhd \
LIBS := work
LIB_IND := work/.work
## rules #################################
sim: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): $(VHDL_OBJ)
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< .
clean:
rm -rf ./modelsim.ini $(LIBS)
.PHONY: clean
work/.work:
(vlib work && vmap -modelsimini modelsim.ini work && touch work/.work )|| rm -rf work
work/old_rep_test/.old_rep_test_vhd: ../rtl/old_rep_test.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
work/testbench/.testbench_vhd: testbench.vhd
vcom $(VCOM_FLAGS) -work work $<
@mkdir -p $(dir $@) && touch $@
hdl/old_rep_test/sim/Manifest.py deleted 100644 → 0
View file @ a75842b3
target = "xilinx"
action = "simulation"
files = [
"../rtl/old_rep_test.vhd",
"testbench.vhd"
];
hdl/old_rep_test/sim/run.do deleted 100644 → 0
View file @ a75842b3
vlib work
vcom -explicit -93 "../rtl/old_rep_test.vhd"
vcom -explicit -93 "testbench.vhd"
vsim -voptargs="+acc" -lib work work.testbench
# log -r /*
radix -hexadecimal
# add wave *
do wave.do
run 100 us
wave zoomfull
hdl/old_rep_test/sim/testbench.vhd deleted 100644 → 0
View file @ a75842b3
--==============================================================================
-- CERN (BE-CO-HT)
-- Testbench for old repeater design
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-02-28
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-02-28 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity testbench is
end entity testbench;
architecture behav of testbench is
--============================================================================
-- Type declarations
--============================================================================
--============================================================================
-- Constant declarations
--============================================================================
constant c_clk_per : time := 10 ns;
constant c_reset_width : time := 31 ns;
--============================================================================
-- Component declarations
--============================================================================
component old_rep_test is
generic
(
g_pwidth : natural := 200;
g_freq : natural := 200000000
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
pulse_o : out std_logic
);
end component old_rep_test;
--============================================================================
-- Signal declarations
--============================================================================
signal clk, rst, pulse : std_logic := '0';
--==============================================================================
-- architecture begin
--==============================================================================
begin
DUT: old_rep_test
generic map
(
g_pwidth => 1,
g_freq => 13
)
port map
(
clk_i => clk,
rst_i => rst,
pulse_o => pulse
);
p_clk: process
begin
clk <= not clk;
wait for c_clk_per/2;
end process p_clk;
p_rst: process
begin
rst <= '1';
wait for c_reset_width;
rst <= '0';
wait;
end process p_rst;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
hdl/old_rep_test/sim/transcript deleted 100644 → 0
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hdl/old_rep_test/sim/wave.do deleted 100644 → 0
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onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/rst
add wave -noupdate /testbench/pulse
add wave -noupdate -divider internal
add wave -noupdate /testbench/DUT/pulse_cnt
add wave -noupdate /testbench/DUT/pulse
add wave -noupdate /testbench/DUT/freq_cnt
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {40 ns} 0}
configure wave -namecolwidth 194
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {18484 ns} {20080 ns}
hdl/old_rep_test/syn/Makefile deleted 100644 → 0
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########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := conv_ttl_blo_v2.xise
ISE_CRAP := *.b conv_ttl_blo_v2_summary.html *.tcl conv_ttl_blo_v2.bld conv_ttl_blo_v2.cmd_log *.drc conv_ttl_blo_v2.lso *.ncd conv_ttl_blo_v2.ngc conv_ttl_blo_v2.ngd conv_ttl_blo_v2.ngr conv_ttl_blo_v2.pad conv_ttl_blo_v2.par conv_ttl_blo_v2.pcf conv_ttl_blo_v2.prj conv_ttl_blo_v2.ptwx conv_ttl_blo_v2.stx conv_ttl_blo_v2.syr conv_ttl_blo_v2.twr conv_ttl_blo_v2.twx conv_ttl_blo_v2.gise conv_ttl_blo_v2.unroutes conv_ttl_blo_v2.ut conv_ttl_blo_v2.xpi conv_ttl_blo_v2.xst conv_ttl_blo_v2_bitgen.xwbt conv_ttl_blo_v2_envsettings.html conv_ttl_blo_v2_guide.ncd conv_ttl_blo_v2_map.map conv_ttl_blo_v2_map.mrp conv_ttl_blo_v2_map.ncd conv_ttl_blo_v2_map.ngm conv_ttl_blo_v2_map.xrpt conv_ttl_blo_v2_ngdbuild.xrpt conv_ttl_blo_v2_pad.csv conv_ttl_blo_v2_pad.txt conv_ttl_blo_v2_par.xrpt conv_ttl_blo_v2_summary.xml conv_ttl_blo_v2_usage.xml conv_ttl_blo_v2_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
USER:=$(HDLMAKE_USER)#take the value from the environment
SERVER:=$(HDLMAKE_SERVER)#take the value from the environment
R_NAME:=conv_ttl_blo_v2
__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
endif
ifeq (x$(SERVER),x)
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
endif
CWD := $(shell pwd)
FILES := ../rtl/pulse_gen.vhd \
../top/conv_ttl_blo_v2.ucf \
../top/conv_ttl_blo_v2.vhd \
run.tcl \
conv_ttl_blo_v2.xise
#target for running simulation in the remote location
remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
__send_back:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
hdl/old_rep_test/syn/Manifest.py deleted 100644 → 0
View file @ a75842b3
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "conv_ttl_blo_v2"
syn_project = "conv_ttl_blo_v2.xise"
modules = {
"local" : [
"../rtl",
"../top"
]
}
hdl/old_rep_test/syn/conv_ttl_blo_v2.xise deleted 100644 → 0
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hdl/old_rep_test/syn/old_rep_test.ppr deleted 100644 → 0
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<?xml version="1.0"?>
<Project Version="4" Minor="36">
<FileSet Dir="sources_1" File="fileset.xml"/>
<FileSet Dir="constrs_1" File="fileset.xml"/>
<FileSet Dir="sim_1" File="fileset.xml"/>
<RunSet Dir="runs" File="runs.xml"/>
<DefaultLaunch Dir="$PRUNDIR"/>
<DefaultPromote Dir="$PROMOTEDIR"/>
<Config>
<Option Name="Id" Val="bcf2b3838fb34eacb774368959fa1ec4"/>
<Option Name="Part" Val="xc6slx45tfgg484-3"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compxlib"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="TargetSimulator" Val="ModelSim"/>
<Option Name="Board" Val=""/>
<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
<Option Name="ActiveSimSet" Val=""/>
<Option Name="CxlOverwriteLibs" Val="1"/>
<Option Name="CxlFuncsim" Val="1"/>
<Option Name="CxlTimesim" Val="1"/>
<Option Name="CxlCore" Val="1"/>
<Option Name="CxlEdk" Val="0"/>
<Option Name="CxlExcludeCores" Val="1"/>
<Option Name="CxlExcludeSubLibs" Val="0"/>
</Config>
</Project>
hdl/old_rep_test/syn/run.tcl deleted 100644 → 0
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project open conv_ttl_blo_v2.xise
process run {Generate Programming File} -force rerun_all
hdl/old_rep_test/top/Manifest.py deleted 100644 → 0
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files = [
"conv_ttl_blo_v2.ucf",
"conv_ttl_blo_v2.vhd"
]
hdl/old_rep_test/top/conv_ttl_blo_v2.ucf deleted 100644 → 0
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hdl/old_rep_test/top/conv_ttl_blo_v2.vhd deleted 100644 → 0
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hdl/pulse_gen/rtl/pulse_gen.vhd deleted 100644 → 0
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--==============================================================================
-- CERN (BE-CO-HT)
-- Test module for old repeater boards
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-02-28
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-02-28 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_gen is
generic
(
g_pwidth : natural := 200;
g_freq : natural := 400;
g_delay : natural := 0
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic;
pulse_o : out std_logic
);
end entity pulse_gen;
architecture behav of pulse_gen is
--============================================================================
-- Function and procedure declarations
--============================================================================
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
--============================================================================
-- Signal declarations
--============================================================================
signal freq_cnt : unsigned(f_log2_size(g_freq)-1 downto 0);
signal delay_cnt : unsigned(f_log2_size(g_delay)-1 downto 0);
signal delay_en : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Delay logic
--============================================================================
gen_nodelay: if (g_delay = 0) generate
delay_en <= '0';
end generate gen_nodelay;
gen_delay: if (g_delay > 0) generate
p_delay: process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
delay_en <= '1';
delay_cnt <= (others => '0');
elsif (en_i = '1') and (delay_en = '1') then
delay_cnt <= delay_cnt + 1;
if (delay_cnt = g_delay-1) then
delay_en <= '0';
delay_cnt <= (others => '0');
end if;
end if;
end if;
end process p_delay;
end generate gen_delay;
--============================================================================
-- Pulse generation logic
--============================================================================
p_gen_pulse: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
freq_cnt <= (others => '0');
pulse_o <= '0';
elsif (en_i = '1') and (delay_en = '0') then
freq_cnt <= freq_cnt + 1;
pulse_o <= '0';
if (freq_cnt < g_pwidth) then
pulse_o <= '1';
elsif (freq_cnt = g_freq-1) then
freq_cnt <= (others => '0');
end if;
end if;
end if;
end process p_gen_pulse;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
hdl/pulse_generator/Manifest.py deleted 100644 → 0
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modules = {
"local" : "rtl"
}
hdl/pulse_generator/rtl/Manifest.py deleted 100644 → 0
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files = "pulse_generator.vhd"
modules = {
"local" : [
"../../glitch_filt",
"../../../../ip_cores/general-cores"
]
}
hdl/pulse_generator/rtl/pulse_generator.vhd deleted 100644 → 0
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hdl/pulse_generator/sim/run.do deleted 100644 → 0
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vlib work
vcom -explicit -93 "../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vcom -explicit -93 "../../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vcom -explicit -93 "../../old_rep_test/rtl/pulse_gen.vhd"
vcom -explicit -93 "../../glitch_filt/rtl/glitch_filt.vhd"
vcom -explicit -93 "../rtl/pulse_generator.vhd"
vcom -explicit -93 "testbench.vhd"
vsim -t 1ps -voptargs="+acc" -lib work work.testbench
radix -hexadecimal
# add wave *
do wave.do
run 100 us
wave zoomfull
hdl/pulse_generator/sim/testbench.vhd deleted 100644 → 0
View file @ a75842b3
--==============================================================================
-- CERN (BE-CO-HT)
-- Testbench for old repeater design
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-02-28
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-02-28 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity testbench is
end entity testbench;
architecture behav of testbench is
--============================================================================
-- Type declarations
--============================================================================
--============================================================================
-- Constant declarations
--============================================================================
constant c_clk_per : time := 8 ns;
constant c_reset_width : time := 31 ns;
--============================================================================
-- Component declarations
--============================================================================
component pulse_generator is
generic
(
g_pulse_width : natural := 15;
g_glitch_filt_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
pulse_type_i : in std_logic;
trig_i : in std_logic;
pulse_o : out std_logic
);
end component pulse_generator;
component pulse_gen is
generic
(
g_pwidth : natural := 200;
g_freq : natural := 400
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
pulse_o : out std_logic
);
end component pulse_gen;
--============================================================================
-- Signal declarations
--============================================================================
signal clk, clk2, rst_n, pulse, trig, lvl, lvl_n : std_logic := '0';
signal actual_trig : std_logic := '0';
signal actual_pulse : std_logic := '0';
signal ptype : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
-- DUT INSTANTIATION
DUT: pulse_generator
generic map
(
g_pulse_width => 125,
g_glitch_filt_len => 4
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
pulse_type_i => ptype,
trig_i => actual_trig,
pulse_o => pulse
);
-- CLOCK GENERATION
p_clk: process
begin
clk <= not clk;
wait for c_clk_per/2;
end process p_clk;
-- SECOND CLOCK GENERATION
p_clk2: process
begin
clk2 <= not clk2;
wait for 2 ns;
end process p_clk2;
-- RESET GENERATION
p_rst_n: process
begin
rst_n <= '0';
wait for c_reset_width;
rst_n <= '1';
wait;
end process p_rst_n;
-- PULSE GENERATOR FOR TRIGGER
cmp_pulse_gen: pulse_gen
generic map
(
g_pwidth => 100,
g_freq => 2000
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
pulse_o => trig
);
actual_trig <= trig;
actual_pulse <= pulse;
cmp_pulse_gen2: pulse_gen
generic map
(
g_pwidth => 1033,
g_freq => 2066
)
port map
(
clk_i => clk,
rst_n_i => rst_n,
pulse_o => ptype
);
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
hdl/pulse_generator/sim/transcript deleted 100644 → 0
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# // ModelSim SE 10.1 Dec 5 2011 Linux 3.2.0-38-generic-pae
# //
# // Copyright 1991-2011 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
#
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] ../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] ../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package gencores_pkg
# -- Compiling package body gencores_pkg
# -- Loading package gencores_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity gc_sync_ffs
# -- Compiling architecture behavioral of gc_sync_ffs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen
# -- Compiling architecture behav of pulse_gen
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity glitch_filt
# -- Compiling architecture behav of glitch_filt
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_generator
# -- Compiling architecture behav of pulse_generator
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "pulse_generator(behav)".
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.glitch_filt(behav)#1
# Loading work.pulse_gen(behav)#1
# Loading work.pulse_gen(behav)#2
# hexadecimal
# 0 ps
# 105 us
write format wave -window .main_pane.wave.interior.cs.body.pw.wf /home/tstana/Projects/conv-ttl-blo/hdl/pulse_generator/sim/wave.do
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] ../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] ../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package gencores_pkg
# -- Compiling package body gencores_pkg
# -- Loading package gencores_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity gc_sync_ffs
# -- Compiling architecture behavioral of gc_sync_ffs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen
# -- Compiling architecture behav of pulse_gen
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity glitch_filt
# -- Compiling architecture behav of glitch_filt
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_generator
# -- Compiling architecture behav of pulse_generator
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "pulse_generator(behav)".
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(behav)#1
# Loading work.pulse_generator(behav)#1
# Loading work.glitch_filt(behav)#1
# Loading work.pulse_gen(behav)#1
# Loading work.pulse_gen(behav)#2
# hexadecimal
# 0 ps
# 105 us
hdl/pulse_generator/sim/wave.do deleted 100644 → 0
View file @ a75842b3
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/rst_n
add wave -noupdate /testbench/trig
add wave -noupdate /testbench/actual_trig
add wave -noupdate /testbench/ptype
add wave -noupdate /testbench/pulse
add wave -noupdate -divider internal
add wave -noupdate /testbench/DUT/width_cnt
add wave -noupdate /testbench/DUT/state
add wave -noupdate /testbench/DUT/pulse_o
add wave -noupdate /testbench/DUT/pulse_type1
add wave -noupdate /testbench/DUT/pulse_type1_d0
add wave -noupdate /testbench/DUT/pulse_type1_d1
add wave -noupdate /testbench/DUT/pulse_type1_d2
add wave -noupdate /testbench/DUT/pulse_rst
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 2} {16080000 ps} 0}
configure wave -namecolwidth 233
configure wave -valuecolwidth 132
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {102112676 ps}
hdl/pulse_generator/syn/Makefile deleted 100644 → 0
View file @ a75842b3
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := conv_ttl_blo_v2.xise
ISE_CRAP := *.b conv_ttl_blo_v2_summary.html *.tcl conv_ttl_blo_v2.bld conv_ttl_blo_v2.cmd_log *.drc conv_ttl_blo_v2.lso *.ncd conv_ttl_blo_v2.ngc conv_ttl_blo_v2.ngd conv_ttl_blo_v2.ngr conv_ttl_blo_v2.pad conv_ttl_blo_v2.par conv_ttl_blo_v2.pcf conv_ttl_blo_v2.prj conv_ttl_blo_v2.ptwx conv_ttl_blo_v2.stx conv_ttl_blo_v2.syr conv_ttl_blo_v2.twr conv_ttl_blo_v2.twx conv_ttl_blo_v2.gise conv_ttl_blo_v2.unroutes conv_ttl_blo_v2.ut conv_ttl_blo_v2.xpi conv_ttl_blo_v2.xst conv_ttl_blo_v2_bitgen.xwbt conv_ttl_blo_v2_envsettings.html conv_ttl_blo_v2_guide.ncd conv_ttl_blo_v2_map.map conv_ttl_blo_v2_map.mrp conv_ttl_blo_v2_map.ncd conv_ttl_blo_v2_map.ngm conv_ttl_blo_v2_map.xrpt conv_ttl_blo_v2_ngdbuild.xrpt conv_ttl_blo_v2_pad.csv conv_ttl_blo_v2_pad.txt conv_ttl_blo_v2_par.xrpt conv_ttl_blo_v2_summary.xml conv_ttl_blo_v2_usage.xml conv_ttl_blo_v2_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
USER:=$(HDLMAKE_USER)#take the value from the environment
SERVER:=$(HDLMAKE_SERVER)#take the value from the environment
R_NAME:=conv_ttl_blo_v2
__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
endif
ifeq (x$(SERVER),x)
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
endif
CWD := $(shell pwd)
FILES := ../rtl/pulse_generator.vhd \
../top/conv_ttl_blo_v2.ucf \
../top/conv_ttl_blo_v2.vhd \
run.tcl \
conv_ttl_blo_v2.xise
#target for running simulation in the remote location
remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
__send_back:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
hdl/pulse_generator/syn/Manifest.py deleted 100644 → 0
View file @ a75842b3
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "conv_ttl_blo_v2"
syn_project = "conv_ttl_blo_v2.xise"
modules = {
"local" : [
"../rtl",
"../top"
]
}
hdl/pulse_generator/syn/conv_ttl_blo_v2.gise deleted 100644 → 0
View file @ a75842b3
This diff is collapsed.
hdl/pulse_generator/syn/conv_ttl_blo_v2.ppr deleted 100644 → 0
View file @ a75842b3
<?xml version="1.0"?>
<Project Version="4" Minor="36">
<FileSet Dir="sources_1" File="fileset.xml"/>
<FileSet Dir="constrs_1" File="fileset.xml"/>
<FileSet Dir="sim_1" File="fileset.xml"/>
<RunSet Dir="runs" File="runs.xml"/>
<DefaultLaunch Dir="$PRUNDIR"/>
<DefaultPromote Dir="$PROMOTEDIR"/>
<Config>
<Option Name="Id" Val="c08f74f5ee304d6b8a6ee13247e8885d"/>
<Option Name="Part" Val="xc6slx45tfgg484-3"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compxlib"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="TargetSimulator" Val="ISim"/>
<Option Name="Board" Val=""/>
<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
<Option Name="ActiveSimSet" Val=""/>
<Option Name="CxlOverwriteLibs" Val="1"/>
<Option Name="CxlFuncsim" Val="1"/>
<Option Name="CxlTimesim" Val="1"/>
<Option Name="CxlCore" Val="1"/>
<Option Name="CxlEdk" Val="0"/>
<Option Name="CxlExcludeCores" Val="1"/>
<Option Name="CxlExcludeSubLibs" Val="0"/>
</Config>
</Project>
hdl/pulse_generator/syn/conv_ttl_blo_v2.xise deleted 100644 → 0
View file @ a75842b3
This diff is collapsed.
hdl/pulse_generator/syn/run.tcl deleted 100644 → 0
View file @ a75842b3
project open conv_ttl_blo_v2.xise
process run {Generate Programming File} -force rerun_all
hdl/pulse_generator/top/Manifest.py deleted 100644 → 0
View file @ a75842b3
files = [
"conv_ttl_blo_v2.ucf",
"conv_ttl_blo_v2.vhd"
]
hdl/pulse_generator/top/conv_ttl_blo_v2.ucf deleted 100644 → 0
View file @ a75842b3
This diff is collapsed.
hdl/pulse_generator/top/conv_ttl_blo_v2.vhd deleted 100644 → 0
View file @ a75842b3
This diff is collapsed.
hdl/release/syn/Makefile
View file @ 82641202
......@@ -45,7 +45,7 @@ FILES := ../top/conv_ttl_blo_v2.ucf \
../../vme64x_i2c/rtl/i2c_slave.vhd \
../../vme64x_i2c/rtl/vme64x_i2c.vhd \
../../glitch_filt/rtl/glitch_filt.vhd \
../../pulse_generator/rtl/pulse_generator.vhd \
../../ctb_pulse_gen/rtl/ctb_pulse_gen.vhd \
../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
......
hdl/release/syn/conv_ttl_blo_v2.gise
View file @ 82641202
......@@ -72,35 +72,34 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1368794212" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1368794212">
<transform xil_pn:end_ts="1369926617" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1369926617">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368794212" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1368794212">
<transform xil_pn:end_ts="1369926617" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="3482918740615751616" xil_pn:start_ts="1369926617">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368794212" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1368794212">
<transform xil_pn:end_ts="1369926617" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-1032337062829449789" xil_pn:start_ts="1369926617">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368794212" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1368794212">
<transform xil_pn:end_ts="1369926617" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1369926617">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368794212" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1368794212">
<transform xil_pn:end_ts="1369926617" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="6739244360423696002" xil_pn:start_ts="1369926617">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368794212" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1368794212">
<transform xil_pn:end_ts="1369926617" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1369926617">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368794212" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1368794212">
<transform xil_pn:end_ts="1369926617" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-5613713180460514355" xil_pn:start_ts="1369926617">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368794227" xil_pn:in_ck="6309703152952971517" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1368794212">
<transform xil_pn:end_ts="1369926637" xil_pn:in_ck="1856640128136744979" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-5659100974288834190" xil_pn:start_ts="1369926617">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -118,11 +117,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1368794227" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1368794227">
<transform xil_pn:end_ts="1369926637" xil_pn:in_ck="9180755367508499589" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1934330619683713069" xil_pn:start_ts="1369926637">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1368794236" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1368794227">
<transform xil_pn:end_ts="1369926648" xil_pn:in_ck="-3184428132143472969" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="7619738475395271108" xil_pn:start_ts="1369926637">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -131,7 +130,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_v2_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1368794274" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1368794236">
<transform xil_pn:end_ts="1369926688" xil_pn:in_ck="-3184428132143472968" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1369926648">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -144,7 +143,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_v2_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1368794312" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1368794274">
<transform xil_pn:end_ts="1369926727" xil_pn:in_ck="-7407895592276768303" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1369926688">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -158,7 +157,7 @@
<outfile xil_pn:name="conv_ttl_blo_v2_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_v2_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1368794333" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1368794312">
<transform xil_pn:end_ts="1369926749" xil_pn:in_ck="-7071212854459536945" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1369926727">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -170,7 +169,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1368794312" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1368794301">
<transform xil_pn:end_ts="1369926727" xil_pn:in_ck="-3184428132143473100" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1369926716">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/release/syn/conv_ttl_blo_v2.xise
View file @ 82641202
......@@ -370,7 +370,7 @@
<file xil_pn:name="../../glitch_filt/rtl/glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../pulse_generator/rtl/pulse_generator.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ctb_pulse_gen/rtl/ctb_pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
......
hdl/release/top/Manifest.py
View file @ 82641202
......@@ -8,7 +8,7 @@ modules = {
"../../reset_gen",
"../rtl",
"../../vme64x_i2c",
"../../pulse_generator",
"../../ctb_pulse_gen",
"../../rtm_detector",
"../../bicolor_led_ctrl",
]
......
hdl/release/top/conv_ttl_blo_v2.vhd
View file @ 82641202
......@@ -162,7 +162,7 @@ architecture behav of conv_ttl_blo_v2 is
-- Pulse generator component
-- (use: output pulse generation, pulse status LEDs)
component pulse_generator is
component ctb_pulse_gen is
generic
(
-- Pulse width, in number of clk_i cycles
......@@ -198,7 +198,7 @@ architecture behav of conv_ttl_blo_v2 is
-- TYPE 2 pulse: g_glitch_filt_len+3 clk_i cycles
pulse_o : out std_logic
);
end component pulse_generator;
end component ctb_pulse_gen;
-- RTM detector component
-- (use: detect the presence of an RTM/P module)
......@@ -212,11 +212,12 @@ architecture behav of conv_ttl_blo_v2 is
);
end component rtm_detector;
component pulse_gen is
component ctb_pulse_gen_gp is
generic
(
g_pwidth : natural := 200;
g_freq : natural := 400
g_freq : natural := 400;
g_delay : natural := 0
);
port
(
......@@ -225,7 +226,7 @@ architecture behav of conv_ttl_blo_v2 is
en_i : in std_logic;
pulse_o : out std_logic
);
end component pulse_gen;
end component ctb_pulse_gen_gp;
-- I2C bridge
-- (use: convert I2C transfers into WB transfers on memmapped registers)
......@@ -513,7 +514,7 @@ begin
gen_ttl_pulse_generators: for i in 1 to g_nr_ttl_chan generate
-- Output pulse generators
cmp_ttl_pulse_gen : pulse_generator
cmp_ttl_pulse_gen : ctb_pulse_gen
generic map
(
g_pulse_width => 125,
......@@ -530,7 +531,7 @@ begin
);
-- Status LED pulse generators
cmp_led_pulse_gen : pulse_generator
cmp_led_pulse_gen : ctb_pulse_gen
generic map
(
g_pulse_width => 12*(10**6),
......@@ -566,7 +567,7 @@ begin
-- Instantiate the necessary number of pulse generator components
gen_inv_pulse_generators : for i in 1 to g_nr_inv_chan generate
cmp_inv_pulse_gen : pulse_generator
cmp_inv_pulse_gen : ctb_pulse_gen
generic map
(
g_pulse_width => 125,
......@@ -586,7 +587,7 @@ begin
-- Output assignment
inv_out_o <= not inv_outputs;
-- cmp_tmp_pulse_gen : pulse_gen
-- cmp_tmp_pulse_gen : ctb_pulse_gen_gp
-- generic map
-- (
-- g_pwidth => 100,
......
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