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Conv TTL Blocking
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Conv TTL Blocking
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7ed3567e
Commit
7ed3567e
authored
Nov 15, 2013
by
Theodor-Adrian Stana
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Final version of pres-2.txt
The file contains comments during the meeting useful in the code review.
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design-review/pres-2.txt
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7ed3567e
1. Review discussion
====================
1.1. Folder structure
---------------------
conv-ttl-blo/
- conv-ttl-blo-gw/
...
...
@@ -35,14 +37,16 @@ conv-ttl-blo/
- software/
1.2. reset_gen
--------------
- reset bit already available, only needs to be connected
1.3. i2c_slave & glitch_filt
- add synchronizer to glitch_filt
----------------------------
- added synchronizer to glitch_filt
- SCL line sampling
-- will change to rising edge sampling
-- (tom, eva) sampled on falling edge to avoid incompliant masters
-- (javier) tapped delay line makes design too complex
-- will change to rising edge sampling
- (tom) will change sda_o and sda_en_o assignment
- (eva) agreed with clearer `falling' and `rising' signal naming
- (eva) FSM seems clearer if the outputs are set in same process as
...
...
@@ -50,39 +54,88 @@ the states
- (javier) misalignment margin in i2c master?
1.4. vbcp_wb
------------
- (eva, javier) will change signal names to reflect they are pulses
- (tom) i2c master informed about WB error by NACK
- watchdog addition (wait for 2.)
1.5. ctb_pulse_gen
------------------
- (javier) constant naming -- prefer `hardcoded' constants in code?
- rename constants to reflect clearer that it is NOT the pulse width,
but a value leading to the pulse width/reject
- constrain minimum pulse value by synthesis error (ASSERT)
1.6. multiboot
--------------
- watchdog (wait for 2.)
- will retry the .wb
- no other additions?
- add more comments for hex values written to icap
1.7. bicolor_led_ctrl
---------------------
1.8. rtm_detector
-----------------
- (eva) rtmm signals can already be read in the register, think it's
a good idea to also have separate rtmm_ok signal in reg?
- add rtmm_ok to stat reg
1.8. top-level
--------------
- (eva) making the top level only consist of instantiations would
complicate design
- (eva) switches are not meant to be changed in operation, but synchronizer
might still be a good idea
- (tom) suggest declaring constants instead of hard-coded constants?
1.9. constraints
----------------
- will add clock constraint to .ucf
- drive unused outputs
2. Block replacement proposal
=============================
2.1. Watchdog
-------------
- separate module per FSM
- just reset to IDLE if too long
2.2. Pulse generator
--------------------
----o-----------------------------------+
| |
| +-------+
| +------+ +-----+ '1' | R | +-----+
+---| SYNC |----| FSM |---------|D Q|----| not |----
+------+ +-----+ | | +-----+
clk125 --|C |
| |
+-------+
3. Add modules to own projects/general-cores
============================================
3.1. MultiBoot to general-cores?
--------------------------------
- problem: only for Spartan-6
add to general-cores
3.2. VBCP bridge to own project
-------------------------------
add to general-cores
4. Documentation
================
- multiboot.py -- read binary directly
5. Discuss about meeting with FE people
=======================================
- who should be in it
4. Discuss about meeting with FE people
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