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Conv TTL Blocking
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Conv TTL Blocking
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7e1f2435
Commit
7e1f2435
authored
Jun 22, 2012
by
gilsoriano
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Synchronizing fsm for the hold times and send frames.
parent
2276a22c
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3 changed files
with
209 additions
and
130 deletions
+209
-130
spi_master_core.vhd
hdl/spi_master_multifield/rtl/spi_master_core.vhd
+184
-120
spi_master_pkg.vhd
hdl/spi_master_multifield/rtl/spi_master_pkg.vhd
+22
-0
spi_master_regs.vhd
hdl/spi_master_multifield/rtl/spi_master_regs.vhd
+3
-10
No files found.
hdl/spi_master_multifield/rtl/spi_master_core.vhd
View file @
7e1f2435
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hdl/spi_master_multifield/rtl/spi_master_pkg.vhd
View file @
7e1f2435
...
...
@@ -79,6 +79,25 @@ package spi_master_pkg is
constant
c_ADDR_LENGTH
:
NATURAL
:
=
3
;
constant
c_DATA_LENGTH
:
NATURAL
:
=
256
;
constant
c_SPI0_default
:
r_SPI0
:
=
(
x
=>
(
others
=>
'0'
),
BDATA
=>
to_unsigned
(
c_DATA_LENGTH
,
8
),
BADDR
=>
to_unsigned
(
c_ADDR_LENGTH
,
8
),
BINST
=>
to_unsigned
(
c_INST_LENGTH
,
8
));
constant
c_SPI1_default
:
r_SPI1
:
=
(
PUSH_DATA
=>
'0'
,
PUSH_ADDR
=>
'0'
,
PUSH_INST
=>
'0'
,
PULL_DATA
=>
'0'
,
PULL_ADDR
=>
'0'
,
PULL_INST
=>
'0'
,
SEND_DATA
=>
'0'
,
SEND_ADDR
=>
'0'
,
SEND_INST
=>
'0'
,
SEND_OP
=>
'0'
,
x
=>
(
others
=>
'0'
),
CLK_DIV
=>
X"2"
,
y
=>
(
others
=>
'0'
));
constant
c_CLK_DIVISION_LOGSIZE
:
NATURAL
:
=
2
;
constant
c_COUNTER_DATA_WIDTH
:
NATURAL
:
=
8
;
...
...
@@ -94,6 +113,9 @@ package spi_master_pkg is
function
f_SPI0
(
signal
r_register
:
in
STD_LOGIC_VECTOR
(
31
downto
0
))
return
r_SPI0
;
function
f_SPI1
(
signal
r_register
:
in
STD_LOGIC_VECTOR
(
31
downto
0
))
return
r_SPI1
;
function
f_STD_LOGIC_VECTOR
(
signal
r_register
:
in
r_SPI0
)
return
STD_LOGIC_VECTOR
;
function
f_STD_LOGIC_VECTOR
(
signal
r_register
:
in
r_SPI1
)
return
STD_LOGIC_VECTOR
;
end
spi_master_pkg
;
package
body
spi_master_pkg
is
...
...
hdl/spi_master_multifield/rtl/spi_master_regs.vhd
View file @
7e1f2435
...
...
@@ -76,22 +76,19 @@ begin
s_wb_rty
<=
'0'
;
s_wb_err
<=
'0'
;
else
s_wb_ack
<=
'0'
;
s_wb_rty
<=
'0'
;
s_wb_err
<=
'0'
;
case
wb_we_i
is
when
'1'
=>
case
wb_addr_i
is
when
c_SPI0_addr
=>
s_SPI0
<=
wb_data_i
;
s_wb_ack
<=
'1'
;
s_wb_rty
<=
'0'
;
s_wb_err
<=
'0'
;
when
c_SPI1_addr
=>
s_SPI1
<=
wb_data_i
;
s_wb_ack
<=
'1'
;
s_wb_rty
<=
'0'
;
s_wb_err
<=
'0'
;
when
others
=>
s_wb_ack
<=
'0'
;
s_wb_rty
<=
'0'
;
s_wb_err
<=
'1'
;
end
case
;
when
others
=>
...
...
@@ -99,13 +96,9 @@ begin
when
c_SPI0_addr
=>
wb_data_o
<=
s_SPI0
;
s_wb_ack
<=
'1'
;
s_wb_rty
<=
'0'
;
s_wb_err
<=
'0'
;
when
c_SPI1_addr
=>
wb_data_o
<=
s_SPI1
;
s_wb_ack
<=
'1'
;
s_wb_rty
<=
'0'
;
s_wb_err
<=
'0'
;
when
others
=>
end
case
;
end
case
;
...
...
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