Updated ctdah_lib.

5b72c846 · gilsoriano · 1f9155f5 · 5b72c846 · 5b72c846
Commit 5b72c846 authored Aug 22, 2012 by gilsoriano
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FIFO_simple.vhd hdl/ctdah_lib/rtl/FIFO_simple.vhd +60 -0

ctdah_pkg.vhd hdl/ctdah_lib/rtl/ctdah_pkg.vhd +14 -0

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--- a/hdl/ctdah_lib/rtl/FIFO_simple.vhd
+++ b/hdl/ctdah_lib/rtl/FIFO_simple.vhd
+----------------------------------------------------------------------------------
+-- Company:        CERN, BE-CO-HT 
+-- Engineer:       Carlos Gil Soriano
+-- 
+-- Create Date:    10:33:33 31/06/2012
+-- Design Name:    FIFO, fixed depth to one
+-- Module Name:    FIFO_simple - Behavioral 
+-- Project Name:   CTDAH
+-- Target Devices: Spartan 6
+-- Tool versions: 
+-- Description:    This module implements a generic FIFO of lenght one.
+--
+--    input--->    
+--             |   REG 0  | ---> reg_o LSB
+--             |__________|
+--          
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+
+entity FIFO_simple is
+   generic(
+      g_data_width  : NATURAL := 8
+   );
+   port (
+      reg_i  : in   STD_LOGIC_VECTOR (g_data_width - 1 downto 0);
+      clk    : in   STD_LOGIC;
+      push   : in   STD_LOGIC;
+      flush  : in   STD_LOGIC;
+      reg_o  : out  STD_LOGIC_VECTOR (g_data_width - 1 downto 0)
+   );
+end FIFO_simple;
+
+architecture Behavioral of FIFO_simple is
+
+begin
+  
+   reg_proc: process(clk)
+   begin
+
+      if rising_edge(clk) then
+         if flush = '1' then
+            reg_o      <= (others => '0');
+         elsif push = '1' then
+            reg_o      <= reg_i;
+         else
+         end if;
+      end if;
+
+   end process;
+
+end Behavioral;
--- a/hdl/ctdah_lib/rtl/ctdah_pkg.vhd
+++ b/hdl/ctdah_lib/rtl/ctdah_pkg.vhd
@@ -73,6 +73,20 @@ package ctdah_pkg is
           );
   end component;

+   component FIFO_simple is
+      generic(
+                g_data_width  : NATURAL := 8
+             );
+      port (
+              reg_i  : in   STD_LOGIC_VECTOR (g_data_width-1 downto 0);
+              clk    : in   STD_LOGIC;
+              push   : in   STD_LOGIC;
+              flush  : in   STD_LOGIC;
+              reg_o  : out  STD_LOGIC_VECTOR (g_data_width - 1 downto 0)
+           );
+   end component;
+
+
 end ctdah_pkg;

 package body ctdah_pkg is