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spi master update: 

- Added documentation in pdf about register and memory map.
- Added testbench of the spi_master_core.
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hdl/spi_master_multifield/doc/spiSpecs.tex 0 → 100755
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%%This is a very basic article template.
%%There is just one section and two subsections.
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
%%\usepackage{draftwatermark}
%%\SetWatermarkLightness{0.9}
%%\SetWatermarkScale{5}
\begin{document}
\title{SPI multifield HDL core}
\author{Carlos Gil Soriano\\BE-CO-HT\\
\href{mailto:carlos.gil.soriano@cern.ch}{\textbf{\textit{carlos.gil.soriano@cern.ch}}}}
\date{July 20, 2012}
\maketitle
\begin{abstract}
A configurable SPI multifield HDL core is shown. This core is able to
specify three kind of fields to be sent according to SPI communication and
been able to configure independently the lenght of every field.\\
The core is targeted for complexer uses of SPI communications, like writing
blocks of EEPROM memories which typically requiere three fields.\\
The following subjects are addressed:
\begin{itemize}
\item The registers to control the module.
\item Step-by-step instructions for proper use.
access.
\end{itemize}
\end{abstract}
\vspace{2cm}
\begin{center}
\begin{tabular}{|p{2.5cm}|p{3.5cm}|p{3cm}|}
\hline
\multicolumn{3}{|c|}{\textbf{Revision history}}\\
\hline
\hline
\textbf{HDL version} & \textbf{Module} & \textbf{Date}\\
\hline
0.1 & SPI master multifield & July 20, 2012\\
\hline
\end{tabular}
\end{center}
\pagebreak
\tableofcontents
\pagebreak
\section{Structure}
The SPI module contains several blocks related the following way:\\
-- spi\_master\_top.vhd
----- spi\_master\_regs.vhd
----- spi\_master\_slave\_core.vhd
--------- FIFO\_dispatcher.vhd
--------- gc\_counter.vhd
--------- gc\_clk\_divider.vhd\\
The top module combines two components:
\textit{spi\_master\_core} and \textit{spi\_master\_regs}.
The first one can be used independently from thei the top module, saving some
interconnection lines and allowing a direct way of using the module. If access
to the control registers \textit{SPI[X]} through classic Wishbone interface is
desired, then the top module must be used.\\
Due to the target use of this SPI core (block transfers for memory interfaces) all
the three input fields are offered in both the top and the core modules.
Internally, the data in every of the three set of fields is registered by the
control registers, either by directly writing into the \textit{SPI[X]} register
(in the case of \textit{spi\_master\_core}) or through wishbone
(\textit{spi\_master\_top}).
\subsection{Dependencies}
Three components used in this core belongs to general use in CTDAH board.
Due to that they are packed inside \textbf{ctdah\_lib}. The required components
to be imported are:\\
-- FIFO\_dispatcher.vhd
-- gc\_counter.vhd
-- gc\_clk\_divider.vhd
\section{Registers}
\subsection{SPI0}
The SPI0 is a write-read register.\\
\begin{tabular}{| l | c | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning} & \textbf{Default}\\
\hline
\hline
4-0 & x & Reserved & \textbf{"00000"} \\
\hline
13-5 & \textbf{BDATA} & Bytes of DATA to be sent & \textbf{c\_INST\_LENGTH}\\
\hline
22-14 & \textbf{BADDR} & Bytes of ADDRess to be sent & \textbf{c\_ADDR\_LENGTH}\\
\hline
31-23 & \textbf{BINST} & Bytes of INSTruction to be sent& \textbf{c\_DATA\_LENGTH}\\
\hline
\end{tabular}
\subsection{SPI1}
The SPI1 is a write-read register.\\
\begin{tabular}{| l | c | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning} & \textbf{Default}\\
\hline
\hline
0 & \textbf{PUSH\_DATA} & PUSH DATA bytes into & \textbf{'0'} \\
& & internal SPI core memory & \\
\hline
1 & \textbf{PUSH\_ADDR} & PUSH ADDRess bytes into & \textbf{'0'} \\
& & internal SPI core memory & \\
\hline
2 & \textbf{PUSH\_INST} & PUSH INSTruction bytes into& \textbf{'0'} \\
& & internal SPI core memory & \\
\hline
5-3 & x & Reserved & \textbf{"000"} \\
\hline
6 & \textbf{SEND\_DATA} & DATA bytes will be sent in & \textbf{'0'} \\
& & a write operation & \\
\hline
7 & \textbf{SEND\_ADDR} & ADDR bytes will be sent in & \textbf{'0'} \\
& & a write operation & \\
\hline
8 & \textbf{SEND\_INST} & INST bytes will be sent in & \textbf{'0'} \\
& & a write operation & \\
\hline
9 & \textbf{SEND\_OP} & perform a SEND OPeration & \textbf{'0'} \\
\hline
11-10 & y & Reserved & \textbf{"00"} \\
\hline
15-12 & \textbf{CLK\_DIV} & CLocK DIVider & \textbf{X"0"} \\
\hline
31-16 & z & Reserved & \textbf{X"0000"}\\
\hline
\end{tabular}
\subsection{SPI2}
The SPI2 register is a read-only register.\\
\begin{tabular}{| l | c | c | c |}
\hline
\textbf{Bits} & \textbf{Field} & \textbf{Meaning} & \textbf{Default}\\
\hline
\hline
0 & \textbf{SENT\_DATA} & DATA was SENT & \textbf{'0'} \\
\hline
1 & \textbf{SENT\_ADDR} & ADDRess was SENT & \textbf{'0'} \\
\hline
2 & \textbf{SENT\_INST} & INSTruction was SENT & \textbf{'0'} \\
\hline
3 & \textbf{SENT\_OP } & OPeration was SENT & \textbf{'0'} \\
\hline
11-4 & x & Reserved & \textbf{X"00"} \\
\hline
15-12 & \textbf{CLK\_DIV} & CLocK DIVision & \textbf{X"0"} \\
\hline
\end{tabular}
\section{Internal memory mapping}
The internal registers map is as follow:\\
\begin{tabular}{| c | c | c |}
\hline
\textbf{Address} & \textbf{Register} & \textbf{Access} \\
\hline
\hline
\textbf{0x0} & \textit{SPI0} & Write-read \\
\hline
\textbf{0x1} & \textit{SPI1} & Write-read \\
\hline
\textbf{0x2} & \textit{SPI2} & Read-only \\
\hline
\end{tabular}
\section{How to use it}
\subsection{Outputting a stream of data through SPI}
\begin{enumerate}
\item Specify the divider it will be used to construct the SPI clk signal out
of the general clk signal.
\item Place the values to be sent in \textit{inst\_i}, \textit{addr\_i} and
\textit{data\_i}.
\item Register their values by one-clock asserting \textit{PUSH\_[X]} bits in
\textit{SPI1} register.
\item Specify which fields must be sent by asserting \textit{SEND\_[X]} bits in
\textit{SPI1} register. This bits must keep asserted during the whole
send operation.
\item Specify the length in bytes of every field by writing \textit{SPI0}.
\item Assert \textit{SEND\_OP} bit field in \textit{SPI1} register. It must be
keep asserted until \textit{SENT\_OP} is received.
\end{enumerate}
\end{document}
hdl/spi_master_multifield/rtl/spi_master_pkg.vhd
View file @ 470753fc
----------------------------------------------------------------------------------
--
-- Package File Template
-- Copyright CERN 2011.
--
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
-- You may redistribute and modify this documentation under the terms of the CERN
-- OHL v.1.1. (http://ohwr.org/cernohl).
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
-- This documentation is distributed WITHOUT
-- ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY
-- QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.1 for
-- applicable conditions.
--
----------------------------------------------------------------------------------
--
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 11:03:11 06/19/2012
-- Design Name:
-- Module Name: spi_master_pkg - Behavioral
-- Project Name: CTDAH/SVEC
-- Target Devices: Spartan 6
-- Tool versions: Xilinx ISE 13.4
-- Description: Package providing all the register configurations for the
-- SPI core.
--
-- Dependencies:
--
-- Revision: 0.1
-- 0.01 + File Created
-- 0.1 - Alpha version. Able to write and output data correctly at
-- different configurations.
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
......@@ -133,24 +163,37 @@ package spi_master_pkg is
constant c_SPI0_addr : STD_LOGIC_VECTOR (3 downto 0) := X"0";
constant c_SPI1_addr : STD_LOGIC_VECTOR (3 downto 0) := X"1";
constant c_SPI2_addr : STD_LOGIC_VECTOR (3 downto 0) := X"2";
function f_SPI0 (signal r_register : in STD_LOGIC_VECTOR(31 downto 0)) return r_SPI0;
function f_SPI1 (signal r_register : in STD_LOGIC_VECTOR(31 downto 0)) return r_SPI1;
function f_SPI2 (signal r_register : in STD_LOGIC_VECTOR(15 downto 0)) return r_SPI2;
function f_STD_LOGIC_VECTOR(signal r_register : in r_SPI0) return STD_LOGIC_VECTOR;
function f_STD_LOGIC_VECTOR(signal r_register : in r_SPI1) return STD_LOGIC_VECTOR;
function f_STD_LOGIC_VECTOR(signal r_register : in r_SPI2) return STD_LOGIC_VECTOR;
function f_STD_LOGIC_VECTOR(r_register : in r_SPI0) return STD_LOGIC_VECTOR;
function f_STD_LOGIC_VECTOR(r_register : in r_SPI1) return STD_LOGIC_VECTOR;
function f_STD_LOGIC_VECTOR(r_register : in r_SPI2) return STD_LOGIC_VECTOR;
function f_min(a: NATURAL; b: NATURAL) return NATURAL;
end spi_master_pkg;
package body spi_master_pkg is
function f_min(a: NATURAL; b: NATURAL) return NATURAL is
variable ret: NATURAL;
begin
if a < b then
ret := a;
else
ret := b;
end if;
return ret;
end f_min;
-----------------------------------------------------------------------------
--! @brief SPI0 record type translation to STD_LOGIC_VECTOR
--! @param r_register r_SPI0 record type to be translated
-----------------------------------------------------------------------------
function f_STD_LOGIC_VECTOR (signal r_register : in r_SPI0) return STD_LOGIC_VECTOR is
function f_STD_LOGIC_VECTOR (r_register : in r_SPI0) return STD_LOGIC_VECTOR is
begin
return ( std_logic_vector(r_register.BINST)
& std_logic_vector(r_register.BADDR)
......@@ -178,7 +221,7 @@ package body spi_master_pkg is
--! @brief SPI1 record type translation to STD_LOGIC_VECTOR
--! @param r_register r_CTR0 record type to be translated
-----------------------------------------------------------------------------
function f_STD_LOGIC_VECTOR (signal r_register : in r_SPI1) return STD_LOGIC_VECTOR is
function f_STD_LOGIC_VECTOR (r_register : in r_SPI1) return STD_LOGIC_VECTOR is
begin
return ( r_register.z & std_logic_vector(r_register.CLK_DIV)
& r_register.y & r_register.SEND_OP
......@@ -216,7 +259,7 @@ package body spi_master_pkg is
--! @brief SPI2 record type translation to STD_LOGIC_VECTOR
--! @param r_register r_SPI2 record type to be translated
-----------------------------------------------------------------------------
function f_STD_LOGIC_VECTOR (signal r_register : in r_SPI2) return STD_LOGIC_VECTOR is
function f_STD_LOGIC_VECTOR (r_register : in r_SPI2) return STD_LOGIC_VECTOR is
begin
return ( std_logic_vector(r_register.CLK_DIV)
& r_register.x
......
hdl/spi_master_multifield/rtl/spi_master_regs.vhd
View file @ 470753fc
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Copyright CERN 2011.
--
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
-- You may redistribute and modify this documentation under the terms of the CERN
-- OHL v.1.1. (http://ohwr.org/cernohl).
--
-- This documentation is distributed WITHOUT
-- ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY
-- QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.1 for
-- applicable conditions.
--
----------------------------------------------------------------------------------
--
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 17:34:08 06/14/2012
-- Design Name:
-- Module Name: spi_master_regs - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- Design Name:
-- Module Name: spi_master_core - Behavioral
-- Project Name: CTDAH/SVEC
-- Target Devices: Spartan 6
-- Tool versions: Xilinx ISE 13.4
-- Description: Wishbone access for SPI core.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision: 0.1
-- 0.01 + File Created
-- 0.1 - Alpha version. Able to write and output data correctly at
-- different configurations.
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
......@@ -40,7 +59,8 @@ entity spi_master_regs is
wb_err_o : out STD_LOGIC;
SPI0_o : out STD_LOGIC_VECTOR (31 downto 0);
SPI1_o : out STD_LOGIC_VECTOR (31 downto 0)
SPI1_o : out STD_LOGIC_VECTOR (31 downto 0);
SPI2_i : in STD_LOGIC_VECTOR (15 downto 0)
);
end spi_master_regs;
......@@ -48,6 +68,7 @@ architecture Behavioral of spi_master_regs is
signal s_SPI0 : STD_LOGIC_VECTOR (31 downto 0);
signal s_SPI1 : STD_LOGIC_VECTOR (31 downto 0);
signal s_SPI2 : STD_LOGIC_VECTOR (15 downto 0);
signal s_wb_ack : STD_LOGIC;
signal s_wb_rty : STD_LOGIC;
......@@ -61,11 +82,14 @@ begin
SPI0_o <= s_SPI0;
SPI1_o <= s_SPI1;
s_SPI2 <= SPI2_i;
p_wb: process (wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i = '1' then
s_SPI0 <= f_STD_LOGIC_VECTOR(c_SPI0_default);
s_SPI1 <= f_STD_LOGIC_VECTOR(c_SPI1_default);
elsif (wb_stb_i = '1' and wb_cyc_i = '1') then
if (s_wb_ack or s_wb_rty or s_wb_err) = '1' then
s_wb_ack <= '0';
......@@ -95,7 +119,11 @@ begin
when c_SPI1_addr =>
wb_data_o <= s_SPI1;
s_wb_ack <= '1';
when others =>
when c_SPI2_addr =>
wb_data_o(15 downto 0) <= s_SPI2;
wb_data_o(31 downto 16) <= (others => '0');
s_wb_ack <= '1';
when others =>
end case;
end case;
end if;
......
hdl/spi_master_multifield/rtl/spi_master_top.vhd
View file @ 470753fc
----------------------------------------------------------------------------------
--
-- Copyright CERN 2011.
--
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
-- You may redistribute and modify this documentation under the terms of the CERN
-- OHL v.1.1. (http://ohwr.org/cernohl).
--
-- This documentation is distributed WITHOUT
-- ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY
-- QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.1 for
-- applicable conditions.
--
----------------------------------------------------------------------------------
--
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
......@@ -13,11 +29,14 @@
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision: 0.1
-- 0.01 + File Created
-- 0.1 - Alpha version. Able to write and output data correctly at
-- different configurations.
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
......@@ -96,7 +115,8 @@ architecture Behavioral of spi_master_top is
wb_err_o : out STD_LOGIC;
SPI0_o : out STD_LOGIC_VECTOR (31 downto 0);
SPI1_o : out STD_LOGIC_VECTOR (31 downto 0)
SPI1_o : out STD_LOGIC_VECTOR (31 downto 0);
SPI2_i : in STD_LOGIC_VECTOR (15 downto 0)
);
end component;
......@@ -142,7 +162,8 @@ begin
wb_err_o => wb_err_o,
SPI0_o => s_SPI0,
SPI1_o => s_SPI1
SPI1_o => s_SPI1,
SPI2_i => s_SPI2
);
end Behavioral;
......
hdl/spi_master_multifield/test/spi_master_core_tb.vhd 0 → 100755
View file @ 470753fc
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