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3a931f62
Commit
3a931f62
authored
Sep 25, 2012
by
gilsoriano
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Plain Diff
Adapting m25p32 to spi modifications.
parent
d1d5a289
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9 changed files
with
1040 additions
and
1601 deletions
+1040
-1601
m25p32_core.vhd
hdl/m25p32/rtl/m25p32_core.vhd
+230
-247
m25p32_core_pkg.vhd
hdl/m25p32/rtl/m25p32_core_pkg.vhd
+0
-216
m25p32_pkg.vhd
hdl/m25p32/rtl/m25p32_pkg.vhd
+446
-353
m25p32_regs.vhd
hdl/m25p32/rtl/m25p32_regs.vhd
+72
-200
m25p32_top.vhd
hdl/m25p32/rtl/m25p32_top.vhd
+28
-74
m25p32_top_tb.vhd
hdl/m25p32/test/m25p32_top_tb.vhd
+126
-179
m25p32_top_tb_pkg.vhd
hdl/m25p32/test/m25p32_top_tb_pkg.vhd
+138
-0
serializer_sim.vhd
hdl/m25p32/test/serializer_sim.vhd
+0
-130
serializer_sim_pkg.vhd
hdl/m25p32/test/serializer_sim_pkg.vhd
+0
-202
No files found.
hdl/m25p32/rtl/m25p32_core.vhd
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3a931f62
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hdl/m25p32/rtl/m25p32_core_pkg.vhd
deleted
100755 → 0
View file @
d1d5a289
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hdl/m25p32/rtl/m25p32_pkg.vhd
View file @
3a931f62
This diff is collapsed.
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hdl/m25p32/rtl/m25p32_regs.vhd
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3a931f62
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hdl/m25p32/rtl/m25p32_top.vhd
View file @
3a931f62
...
...
@@ -64,52 +64,37 @@ end m25p32_top;
architecture
Behavioral
of
m25p32_top
is
signal
s_CTR0
:
STD_LOGIC_VECTOR
(
r_CTR0
'a_length
-
1
downto
0
);
signal
s_FMOH
:
STD_LOGIC_VECTOR
(
r_FMOH
'a_length
-
1
downto
0
);
signal
s_DBUF
:
STD_LOGIC_VECTOR
(
r_DBUF
'a_length
-
1
downto
0
);
signal
s_inst_db
:
STD_LOGIC_VECTOR
(
8
*
c_INST_LENGTH
-
1
downto
0
);
signal
s_addr_db
:
STD_LOGIC_VECTOR
(
8
*
c_ADDR_LENGTH
-
1
downto
0
);
signal
s_data_db
:
STD_LOGIC_VECTOR
(
8
*
c_DATA_LENGTH
-
1
downto
0
);
signal
s_inst_core
:
STD_LOGIC_VECTOR
(
8
*
c_INST_LENGTH
-
1
downto
0
);
signal
s_push_i_core
:
STD_LOGIC
;
signal
s_push_a_core
:
STD_LOGIC
;
signal
s_push_d_core
:
STD_LOGIC
;
signal
s_bov_core
:
STD_LOGIC
;
signal
s_wr_data
:
STD_LOGIC_VECTOR
(
c_DATA_LENGTH
*
8
-
1
downto
0
);
signal
s_rd_data
:
STD_LOGIC_VECTOR
(
c_DATA_LENGTH
*
8
-
1
downto
0
);
signal
s_FMOH
:
STD_LOGIC_VECTOR
(
r_FMOH
'a_length
-
1
downto
0
);
component
m25p32_core
is
generic
(
g_INST_LENGTH
:
NATURAL
:
=
c_INST_LENGTH
;
g_ADDR_LENGTH
:
NATURAL
:
=
c_ADDR_LENGTH
;
g_PAGE_SIZE
:
NATURAL
:
=
c_PAGE_SIZE
;
g_READ_LENGTH
:
NATURAL
:
=
c_READ_LENGTH
);
port
(
wb_rst_i
:
in
STD_LOGIC
;
wb_clk
:
in
STD_LOGIC
;
mosi_o
:
out
STD_LOGIC
;
miso_i
:
in
STD_LOGIC
;
sclk_o
:
out
STD_LOGIC
;
ss_n_o
:
out
STD_LOGIC
;
inst_db_i
:
in
STD_LOGIC_VECTOR
(
8
*
c_INST_LENGTH
-
1
downto
0
);
addr_db_i
:
in
STD_LOGIC_VECTOR
(
8
*
c_ADDR_LENGTH
-
1
downto
0
);
data_db_i
:
in
STD_LOGIC_VECTOR
(
8
*
c_DATA_LENGTH
-
1
downto
0
);
inst_core_o
:
out
STD_LOGIC_VECTOR
(
8
*
c_INST_LENGTH
-
1
downto
0
);
wb_rst_i
:
in
STD_LOGIC
;
wb_clk
:
in
STD_LOGIC
;
push_i_core_o
:
out
STD_LOGIC
;
push_a_core_o
:
out
STD_LOGIC
;
push_d_core_o
:
out
STD_LOGIC
;
bov_core
_o
:
out
STD_LOGIC
;
mosi_o
:
out
STD_LOGIC
;
miso_i
:
in
STD_LOGIC
;
sclk_o
:
out
STD_LOGIC
;
ss_n
_o
:
out
STD_LOGIC
;
CTR0_o
:
out
STD_LOGIC_VECTOR
(
r_CTR0
'a_length
-
1
downto
0
);
FMOH_i
:
in
STD_LOGIC_VECTOR
(
r_FMOH
'a_length
-
1
downto
0
)
FMOH_io
:
inout
STD_LOGIC_VECTOR
(
r_FMOH
'a_length
-
1
downto
0
)
);
end
component
;
component
m25p32_regs
is
generic
(
g_INST_LENGTH
:
NATURAL
:
=
c_INST_LENGTH
;
g_ADDR_LENGTH
:
NATURAL
:
=
c_ADDR_LENGTH
;
g_DATA_LENGTH
:
NATURAL
:
=
c_DATA_LENGTH
);
g_INST_LENGTH
:
NATURAL
:
=
c_INST_LENGTH
;
g_ADDR_LENGTH
:
NATURAL
:
=
c_ADDR_LENGTH
;
g_DATA_LENGTH
:
NATURAL
:
=
c_DATA_LENGTH
;
g_READ_LENGTH
:
NATURAL
:
=
c_READ_LENGTH
;
g_WB_ADDR_LENGTH
:
NATURAL
:
=
c_BYTES_PER_PAGE_BITS
+
1
);
port
(
wb_rst_i
:
in
STD_LOGIC
;
wb_clk
:
in
STD_LOGIC
;
...
...
@@ -125,20 +110,10 @@ architecture Behavioral of m25p32_top is
wb_rty_o
:
out
STD_LOGIC
;
wb_err_o
:
out
STD_LOGIC
;
inst_core_i
:
in
STD_LOGIC_VECTOR
(
8
*
g_INST_LENGTH
-
1
downto
0
);
wr_data_o
:
out
STD_LOGIC_VECTOR
(
c_DATA_LENGTH
*
8
-
1
downto
0
);
rd_data_i
:
in
STD_LOGIC_VECTOR
(
c_DATA_LENGTH
*
8
-
1
downto
0
);
inst_db_o
:
out
STD_LOGIC_VECTOR
(
8
*
g_INST_LENGTH
-
1
downto
0
);
addr_db_o
:
out
STD_LOGIC_VECTOR
(
8
*
g_ADDR_LENGTH
-
1
downto
0
);
data_db_o
:
out
STD_LOGIC_VECTOR
(
8
*
g_DATA_LENGTH
-
1
downto
0
);
push_i_core_i
:
in
STD_LOGIC
;
push_a_core_i
:
in
STD_LOGIC
;
push_d_core_i
:
in
STD_LOGIC
;
bov_core_i
:
in
STD_LOGIC
;
CTR0_i
:
in
STD_LOGIC_VECTOR
(
r_CTR0
'a_length
-
1
downto
0
);
FMOH_o
:
out
STD_LOGIC_VECTOR
(
r_FMOH
'a_length
-
1
downto
0
)
FMOH_io
:
inout
STD_LOGIC_VECTOR
(
r_FMOH
'a_length
-
1
downto
0
)
);
end
component
;
...
...
@@ -152,21 +127,9 @@ begin
mosi_o
=>
prom_mosi_o
,
miso_i
=>
prom_din_i
,
sclk_o
=>
prom_cclk_o
,
ss_n_o
=>
prom_cs0_b_n_o
,
inst_db_i
=>
s_inst_db
,
addr_db_i
=>
s_addr_db
,
data_db_i
=>
s_data_db
,
ss_n_o
=>
prom_cs0_b_n_o
,
inst_core_o
=>
s_inst_core
,
push_i_core_o
=>
s_push_i_core
,
push_a_core_o
=>
s_push_a_core
,
push_d_core_o
=>
s_push_d_core
,
bov_core_o
=>
s_bov_core
,
CTR0_o
=>
s_CTR0
,
FMOH_i
=>
s_FMOH
FMOH_io
=>
s_FMOH
);
inst_m25p32_regs
:
m25p32_regs
...
...
@@ -185,19 +148,10 @@ begin
wb_rty_o
=>
wb_rty_o
,
wb_err_o
=>
wb_err_o
,
inst_core_i
=>
s_inst_core
,
inst_db_o
=>
s_inst_db
,
addr_db_o
=>
s_addr_db
,
data_db_o
=>
s_data_db
,
push_i_core_i
=>
s_push_i_core
,
push_a_core_i
=>
s_push_a_core
,
push_d_core_i
=>
s_push_d_core
,
bov_core_i
=>
s_bov_core
,
wr_data_o
=>
s_wr_data_o
;
rd_data_i
=>
s_rd_data_i
;
CTR0_i
=>
s_CTR0
,
FMOH_o
=>
s_FMOH
FMOH_io
=>
s_FMOH
);
end
Behavioral
;
hdl/m25p32/test/m25p32_top_tb.vhd
View file @
3a931f62
This diff is collapsed.
Click to expand it.
hdl/m25p32/test/m25p32_top_tb_pkg.vhd
0 → 100755
View file @
3a931f62
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:31:47 06/20/2012
-- Design Name:
-- Module Name: /media/BACKUP/CERN/contrib/ohwr/conv-ttl-blo/hdl/spi_master_multifield/test/spi_master_core_tb.vhd
-- Project Name: spi_master_multifield
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: spi_master_core
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library
IEEE
;
library
work
;
use
IEEE
.
STD_LOGIC_1164
.
ALL
;
use
IEEE
.
NUMERIC_STD
.
ALL
;
use
work
.
spi_master_pkg
.
ALL
;
package
m25p32_top_tb_pkg
is
component
m25p32_top
is
port
(
wb_rst_i
:
in
STD_LOGIC
;
wb_clk
:
in
STD_LOGIC
;
wb_we_i
:
in
STD_LOGIC
;
wb_stb_i
:
in
STD_LOGIC
;
wb_cyc_i
:
in
STD_LOGIC
;
wb_sel_i
:
in
STD_LOGIC_VECTOR
(
3
downto
0
);
wb_data_i
:
in
STD_LOGIC_VECTOR
(
31
downto
0
);
wb_data_o
:
out
STD_LOGIC_VECTOR
(
31
downto
0
);
wb_addr_i
:
in
STD_LOGIC_VECTOR
(
3
downto
0
);
wb_ack_o
:
out
STD_LOGIC
;
wb_rty_o
:
out
STD_LOGIC
;
wb_err_o
:
out
STD_LOGIC
;
prom_mosi_o
:
out
STD_LOGIC
;
prom_cclk_o
:
out
STD_LOGIC
;
prom_cs0_b_n_o
:
out
STD_LOGIC
;
prom_din_i
:
in
STD_LOGIC
);
end
component
;
procedure
wishbone_write
(
signal
wb_we
:
out
STD_LOGIC
;
signal
wb_stb
:
out
STD_LOGIC
;
signal
wb_cyc
:
out
STD_LOGIC
;
signal
wb_sel
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
signal
wb_data
:
out
STD_LOGIC_VECTOR
(
31
downto
0
);
signal
wb_addr
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
reg_data
:
STD_LOGIC_VECTOR
(
31
downto
0
);
reg_addr
:
STD_LOGIC_VECTOR
(
1
downto
0
));
procedure
wishbone_read
(
signal
wb_we
:
out
STD_LOGIC
;
signal
wb_stb
:
out
STD_LOGIC
;
signal
wb_cyc
:
out
STD_LOGIC
;
signal
wb_sel
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
signal
wb_data
:
in
STD_LOGIC_VECTOR
(
31
downto
0
);
signal
wb_addr
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
signal
read_data
:
out
STD_LOGIC_VECTOR
(
31
downto
0
);
reg_addr
:
STD_LOGIC_VECTOR
(
1
downto
0
));
end
m25p32_top_tb_pkg
;
package
body
m25p32_top_tb_pkg
is
procedure
wishbone_write
(
signal
wb_we
:
out
STD_LOGIC
;
signal
wb_stb
:
out
STD_LOGIC
;
signal
wb_cyc
:
out
STD_LOGIC
;
signal
wb_sel
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
signal
wb_data
:
out
STD_LOGIC_VECTOR
(
31
downto
0
);
signal
wb_addr
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
reg_data
:
STD_LOGIC_VECTOR
(
31
downto
0
);
reg_addr
:
STD_LOGIC_VECTOR
(
1
downto
0
))
is
begin
wait
until
rising_edge
(
wb_clk
);
wb_we
<=
'1'
;
wb_stb
<=
'1'
;
wb_cyc
<=
'1'
;
wb_sel
<=
X"F"
;
wb_data
<=
reg_data
;
wb_addr
<=
reg_addr
;
wait
until
rising_edge
(
wb_clk
);
--! Here we wait for the ack and keep till operation is finished
wait
until
rising_edge
(
wb_clk
);
wb_we
<=
'0'
;
wb_stb
<=
'0'
;
wb_cyc
<=
'0'
;
wb_sel
<=
X"F"
;
end
procedure
;
procedure
wishbone_read
(
signal
wb_we
:
out
STD_LOGIC
;
signal
wb_stb
:
out
STD_LOGIC
;
signal
wb_cyc
:
out
STD_LOGIC
;
signal
wb_sel
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
signal
wb_data
:
in
STD_LOGIC_VECTOR
(
31
downto
0
);
signal
wb_addr
:
out
STD_LOGIC_VECTOR
(
3
downto
0
);
signal
read_data
:
out
STD_LOGIC_VECTOR
(
31
downto
0
);
reg_addr
:
STD_LOGIC_VECTOR
(
1
downto
0
))
is
begin
wait
until
rising_edge
(
wb_clk
);
wb_we
<=
'0'
;
wb_stb
<=
'1'
;
wb_cyc
<=
'1'
;
wb_sel
<=
X"F"
;
wb_addr
<=
reg_addr
;
wait
until
rising_edge
(
wb_clk
);
--! Here we wait for the ack and keep till operation is finished
read_data
<=
wb_data
;
wait
until
rising_edge
(
wb_clk
);
wb_stb
<=
'0'
;
wb_cyc
<=
'0'
;
wb_sel
<=
X"F"
;
end
procedure
;
end
m25p32_top_tb_pkg
;
hdl/m25p32/test/serializer_sim.vhd
deleted
100755 → 0
View file @
d1d5a289
----------------------------------------------------------------------------------
--
-- Copyright CERN 2011.
--
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
-- You may redistribute and modify this documentation under the terms of the CERN
-- OHL v.1.1. (http://ohwr.org/cernohl).
--
-- This documentation is distributed WITHOUT
-- ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY
-- QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.1 for
-- applicable conditions.
--
----------------------------------------------------------------------------------
--
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 17:09:09 08/08/2012
-- Design Name: Serializer
-- Module Name: serializer_sim.vhd
-- Project Name: Serializer
-- Target Devices: Spartan 6
-- Tool versions: Xilinx ISE 13.4
-- Description: Serializer to be gentlely used in simulation. No RTL model!
-- This is a parametrizable serializer that improves the
-- readability of the test vectors in simulation and
-- verification.
--
-- Dependencies:
--
-- Revision: 0.1
-- 0.01 + File Created
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library
IEEE
;
library
work
;
use
IEEE
.
STD_LOGIC_1164
.
ALL
;
use
work
.
serializer_sim_pkg
.
ALL
;
entity
serializer_sim
is
generic
(
g_SERIAL_LENGTH
:
NATURAL
:
=
c_SERIAL_LENGTH
);
port
(
rst_i
:
in
STD_LOGIC
;
enable_i
:
in
STD_LOGIC
;
serial_data_i
:
in
STD_LOGIC
;
serial_clock_i
:
in
STD_LOGIC
;
FMOH_i
:
in
STD_LOGIC_VECTOR
(
r_FMOH
'a_length
-
1
downto
0
);
clk_i
:
in
STD_LOGIC
;
serial_frame_rcved_o
:
out
STD_LOGIC
;
parallel_frame_o
:
out
STD_LOGIC_VECTOR
(
c_SERIAL_LENGTH
-
1
downto
0
)
);
end
serializer_sim
;
architecture
Behavioral
of
serializer_sim
is
signal
s_inst
:
inst_parallel
;
signal
s_addr
:
addr_parallel
;
signal
s_data
:
data_parallel
;
signal
s_counter
:
INTEGER
;
signal
reset_cnt
:
STD_LOGIC
;
begin
parallel_frame_o
(
c_SERIAL_LENGTH
-
1
downto
c_SERIAL_LENGTH
-
1
-
(
inst_parallel
'a_length
-
1
))
<=
f_STD_LOGIC_VECTOR
(
s_inst
);
parallel_frame_o
(
c_SERIAL_LENGTH
-
inst_parallel
'a_length
-
1
downto
c_SERIAL_LENGTH
-
1
-
inst_parallel
'a_length
-
(
addr_parallel
'a_length
-
1
))
<=
f_STD_LOGIC_VECTOR
(
s_addr
);
parallel_frame_o
(
data_parallel
'a_length
-
1
downto
0
)
<=
f_STD_LOGIC_VECTOR
(
s_data
);
p_serial_clock
:
process
(
serial_clock_i
,
reset_cnt
)
begin
--! We attended the reset strobe from the fast clk domain and reset the
--! counter.
if
reset_cnt
=
'1'
then
s_inst
<=
c_inst_paralell_default
;
s_addr
<=
c_addr_paralell_default
;
s_data
<=
c_data_paralell_default
;
s_counter
<=
0
;
end
if
;
if
rising_edge
(
serial_clock_i
)
then
s_counter
<=
s_counter
+
1
;
--! We capture the signal at the sampling time
if
s_counter
<
8
*
c_SIZE_BLOCKS
(
0
)
then
s_inst
.
inst
(
s_counter
)
<=
serial_data_i
;
elsif
(
s_counter
<
8
*
(
c_SIZE_BLOCKS
(
1
)
+
c_SIZE_BLOCKS
(
0
)))
and
(
s_counter
>=
8
*
c_SIZE_BLOCKS
(
0
))
then
s_addr
.
addr
(
s_counter
-
8
*
c_SIZE_BLOCKS
(
0
))
<=
serial_data_i
;
else
s_data
.
data
(
s_counter
-
8
*
(
c_SIZE_BLOCKS
(
1
)
+
c_SIZE_BLOCKS
(
0
)))
<=
serial_data_i
;
end
if
;
else
end
if
;
end
process
;
--! This process only targets for placing a reset in the other domain.
--! It was thought in the synthesizable way (which means this is the
--! registered process and the combinatorial part is placed in the process
--! above).
p_clk
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
reset_cnt
<=
'0'
;
if
rst_i
=
'1'
then
reset_cnt
<=
'1'
;
--! Add all the logic here to generate serial_frame_rcved_o
end
if
;
end
if
;
end
process
;
end
Behavioral
;
hdl/m25p32/test/serializer_sim_pkg.vhd
deleted
100755 → 0
View file @
d1d5a289
----------------------------------------------------------------------------------
--
-- Copyright CERN 2011.
--
-- This documentation describes Open Hardware and is licensed under the
-- CERN OHL v. 1.1.
--
-- You may redistribute and modify this documentation under the terms of the CERN
-- OHL v.1.1. (http://ohwr.org/cernohl).
--
-- This documentation is distributed WITHOUT
-- ANY EXPRESS OR IMPLIED WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY
-- QUALITY AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL v.1.1 for
-- applicable conditions.
--
----------------------------------------------------------------------------------
--
-- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano
--
-- Create Date: 17:09:09 08/08/2012
-- Design Name: Serializer package for simulation
-- Module Name: serializer_sim_pkg.vhd
-- Project Name: Serializer
-- Target Devices:Spartan 6
-- Tool versions: Xilinx ISE 13.4
-- Description: This is a parametrizable serializer that improves the
-- readability of the test vectors in simulation and
-- Dependencies: verification.
--
-- Revision: 0.1
-- 0.01 + File Created
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library
IEEE
;
library
work
;
use
IEEE
.
STD_LOGIC_1164
.
ALL
;
package
serializer_sim_pkg
is
--! For the SPI translation there are only three different fields
constant
c_SERIAL_BLOCKS
:
NATURAL
:
=
3
;
--! An array of naturals for storing the byte length of every field
type
size_blocks
is
array
(
0
to
c_SERIAL_BLOCKS
-
1
)
of
NATURAL
;
constant
c_SIZE_BLOCKS
:
size_blocks
:
=
(
0
=>
1
,
1
=>
3
,
-- => ,
c_SERIAL_BLOCKS
-
1
=>
256
);
constant
c_SERIAL_LENGTH
:
NATURAL
:
=
8
*
c_SIZE_BLOCKS
(
0
)
+
8
*
c_SIZE_BLOCKS
(
1
)
+
8
*
c_SIZE_BLOCKS
(
2
);
attribute
a_length
:
NATURAL
;
--! @brief Record type for the parallelized instruction field
type
inst_parallel
is
record
inst
:
STD_LOGIC_VECTOR
(
8
*
c_SIZE_BLOCKS
(
0
)
-
1
downto
0
);
end
record
;
attribute
a_length
of
inst_parallel
:
type
is
(
8
*
c_SIZE_BLOCKS
(
0
));
--! @brief Record type for the parallelized address field
type
addr_parallel
is
record
addr
:
STD_LOGIC_VECTOR
(
8
*
c_SIZE_BLOCKS
(
1
)
-
1
downto
0
);
end
record
;
attribute
a_length
of
addr_parallel
:
type
is
(
8
*
c_SIZE_BLOCKS
(
1
));
--! @brief Record type for the parallelized data field
type
data_parallel
is
record
data
:
STD_LOGIC_VECTOR
(
8
*
c_SIZE_BLOCKS
(
2
)
-
1
downto
0
);
end
record
;
attribute
a_length
of
data_parallel
:
type
is
(
8
*
c_SIZE_BLOCKS
(
2
));
--! Declaration of the default values
constant
c_inst_paralell_default
:
inst_parallel
:
=
(
inst
=>
(
others
=>
'0'
));
constant
c_addr_paralell_default
:
addr_parallel
:
=
(
addr
=>
(
others
=>
'0'
));
constant
c_data_paralell_default
:
data_parallel
:
=
(
data
=>
(
others
=>
'0'
));
function
f_INST_PARALLEL
(
inst_slv
:
STD_LOGIC_VECTOR
(
c_SERIAL_LENGTH
-
1
downto
0
))
return
inst_parallel
;
function
f_ADDR_PARALLEL
(
addr_slv
:
STD_LOGIC_VECTOR
(
c_SERIAL_LENGTH
-
1
downto
0
))
return
addr_parallel
;
function
f_DATA_PARALLEL
(
data_slv
:
STD_LOGIC_VECTOR
(
c_SERIAL_LENGTH
-
1
downto
0
))
return
data_parallel
;
function
f_STD_LOGIC_VECTOR
(
inst_part
:
inst_parallel
)
return
STD_LOGIC_VECTOR
;
function
f_STD_LOGIC_VECTOR
(
addr_part
:
addr_parallel
)
return
STD_LOGIC_VECTOR
;
function
f_STD_LOGIC_VECTOR
(
data_part
:
data_parallel
)
return
STD_LOGIC_VECTOR
;
component
serializer_sim
is
generic
(
g_SERIAL_LENGTH
:
NATURAL
:
=
c_SERIAL_LENGTH
);
port
(
rst_i
:
in
STD_LOGIC
;
enable_i
:
in
STD_LOGIC
;
serial_data_i
:
in
STD_LOGIC
;
serial_clock_i
:
in
STD_LOGIC
;
FMOH_i
:
in
STD_LOGIC_VECTOR
(
r_FMOH
'a_length
-
1
downto
0
);
clk_i
:
in
STD_LOGIC
;
serial_frame_rcved_o
:
out
STD_LOGIC
;
parallel_frame_o
:
out
STD_LOGIC_VECTOR
(
c_SERIAL_LENGTH
-
1
downto
0
)
);
end
component
;
end
serializer_sim_pkg
;
package
body
serializer_sim_pkg
is
function
f_INST_PARALLEL
(
inst_slv
:
STD_LOGIC_VECTOR
(
c_SERIAL_LENGTH
-
1
downto
0
))
return
inst_parallel
is
variable
v_inst_parallel
:
inst_parallel
;
begin
v_inst_parallel
.
inst
:
=
inst_slv
(
8
*
c_SERIAL_LENGTH
-
1
downto
c_SERIAL_LENGTH
-
8
*
c_SIZE_BLOCKS
(
0
));
return
v_inst_parallel
;
end
f_INST_PARALLEL
;
function
f_ADDR_PARALLEL
(
addr_slv
:
STD_LOGIC_VECTOR
(
c_SERIAL_LENGTH
-
1
downto
0
))
return
addr_parallel
is
variable
v_addr_parallel
:
addr_parallel
;
begin
v_addr_parallel
.
addr
:
=
addr_slv
(
c_SERIAL_LENGTH
-
8
*
c_SIZE_BLOCKS
(
0
)
-
1
downto
c_SERIAL_LENGTH
-
8
*
c_SIZE_BLOCKS
(
0
)
-
8
*
c_SIZE_BLOCKS
(
1
));
return
v_addr_parallel
;
end
f_ADDR_PARALLEL
;
function
f_DATA_PARALLEL
(
data_slv
:
STD_LOGIC_VECTOR
(
c_SERIAL_LENGTH
-
1
downto
0
))
return
data_parallel
is
variable
v_data_parallel
:
data_parallel
;
begin
v_data_parallel
.
data
:
=
data_slv
(
8
*
c_SIZE_BLOCKS
(
2
)
-
1
downto
0
);
return
v_data_parallel
;
end
f_DATA_PARALLEL
;
--! @brief This function translates inst_part into a STD_LOGIC_VECTOR
--! @param inst_part The parallelized serial instruction received.
function
f_STD_LOGIC_VECTOR
(
inst_part
:
inst_parallel
)
return
STD_LOGIC_VECTOR
is
variable
v_inst_slv
:
STD_LOGIC_VECTOR
(
inst_parallel
'a_length
-
1
downto
0
);
begin
v_inst_slv
:
=
inst_part
.
inst
;
return
v_inst_slv
;
end
f_STD_LOGIC_VECTOR
;
--! @brief This function translates addr_part into a STD_LOGIC_VECTOR
--! @param addr_part The parallelized serial address received.
function
f_STD_LOGIC_VECTOR
(
addr_part
:
addr_parallel
)
return
STD_LOGIC_VECTOR
is
variable
v_addr_slv
:
STD_LOGIC_VECTOR
(
addr_parallel
'a_length
-
1
downto
0
);
begin
v_addr_slv
:
=
addr_part
.
addr
;
return
v_addr_slv
;
end
f_STD_LOGIC_VECTOR
;
--! @brief This function translates data_part into a STD_LOGIC_VECTOR
--! @param data_part The parallelized serial data received.
function
f_STD_LOGIC_VECTOR
(
data_part
:
data_parallel
)
return
STD_LOGIC_VECTOR
is
variable
v_data_slv
:
STD_LOGIC_VECTOR
(
data_parallel
'a_length
-
1
downto
0
);
begin
v_data_slv
:
=
data_part
.
data
;
return
v_data_slv
;
end
f_STD_LOGIC_VECTOR
;
end
serializer_sim_pkg
;
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