Improving whole module: better reads and writes fsm

081d73c1 · gilsoriano · e4c9846a · 081d73c1 · 081d73c1
Commit 081d73c1 authored Sep 17, 2012 by gilsoriano
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Showing with 353 additions and 316 deletions

spi_master_core.vhd hdl/spi_master_multifield/rtl/spi_master_core.vhd +291 -315

spi_master_pkg.vhd hdl/spi_master_multifield/rtl/spi_master_pkg.vhd +62 -1

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--- a/hdl/spi_master_multifield/rtl/spi_master_core.vhd
+++ b/hdl/spi_master_multifield/rtl/spi_master_core.vhd
--- a/hdl/spi_master_multifield/rtl/spi_master_pkg.vhd
+++ b/hdl/spi_master_multifield/rtl/spi_master_pkg.vhd
@@ -216,6 +216,14 @@ package spi_master_pkg is
   function f_STD_LOGIC_VECTOR(r_register : in r_SPI2) return STD_LOGIC_VECTOR;
   function f_STD_LOGIC_VECTOR(r_register : in r_SPI3) return STD_LOGIC_VECTOR;

+   function f_read_edge(r_register : in r_SPI0;
+                        spi_clk    : in STD_LOGIC;
+                        spi_clk_d0 : in STD_LOGIC) return STD_LOGIC;
+
+   function f_write_edge(r_register : in r_SPI0;
+                         spi_clk    : in STD_LOGIC;
+                         spi_clk_d0 : in STD_LOGIC) return STD_LOGIC;
+
   function f_min(a: NATURAL; b: NATURAL) return NATURAL; 
 end spi_master_pkg;

@@ -365,5 +373,58 @@ package body spi_master_pkg is
      return v_SPI3;
   end f_SPI3;

+   -----------------------------------------------------------------------------
+   --! @brief Function that determines a read edge depending upon
+   --!        CPOL and CPHA values.
+   --! @param r_register  SPI0 register containing CPOL and CPHA 
+   --!        spi_clk     STD_LOGIC containing currently sampled spi clock value
+   --!        spi_clk_d0  STD_LOGIC containing previously sampled spi clock value
+   -----------------------------------------------------------------------------
+   function f_read_edge(r_register  : in r_SPI0;
+                         spi_clk    : in STD_LOGIC;
+                         spi_clk_d0 : in STD_LOGIC) return STD_LOGIC is
+      variable read_edge : STD_LOGIC;
+   begin
+      read_edge       := '0';
+      if (r_register.CPOL xor r_register.CPHA)  = '0' then
+      --! The read case is the rising_edge
+         if spi_clk = '1' and spi_clk_d0 = '0' then
+            read_edge       := '1';
+         end if;
+      else
+      --! The read case is the falling_edge
+         if spi_clk = '0' and spi_clk_d0 = '1' then
+            read_edge       := '1';
+         end if;
+      end if;
+      return read_edge;
+   end f_read_edge;
+
+   -----------------------------------------------------------------------------
+   --! @brief Function that determines a write edge depending upon
+   --!        CPOL and CPHA values.
+   --! @param r_register  SPI0 register containing CPOL and CPHA 
+   --!        spi_clk     STD_LOGIC containing currently sampled spi clock value
+   --!        spi_clk_d0  STD_LOGIC containing previously sampled spi clock value
+   -----------------------------------------------------------------------------
+   function f_write_edge(r_register  : in r_SPI0;
+                         spi_clk    : in STD_LOGIC;
+                         spi_clk_d0 : in STD_LOGIC) return STD_LOGIC is
+      variable write_edge : STD_LOGIC;
+   begin
+      write_edge       := '0';
+      if (r_register.CPOL xor r_register.CPHA)  = '0' then
+      --! The write case is the falling_edge
+         if spi_clk = '0' and spi_clk_d0 = '1' then
+            write_edge       := '1';
+         end if;
+      else
+      --! The write case is the rising_edge
+         if spi_clk = '1' and spi_clk_d0 = '0' then
+            write_edge       := '1';
+         end if;
+      end if;
+      return write_edge;
+   end f_write_edge;

-   end spi_master_pkg;
+end spi_master_pkg;