... | ... | @@ -11,8 +11,8 @@ the pulse conversion systems are envisioned to be placed. |
|
|
[CTDAH](https://cs-ccr-oas1.cern.ch/pls/htmldb_accdb/f?p=104:4:110849108995734::::P4_LETTER,P4_DETAILS,P4_CODE,P4_EC_ID:C,YES,CTDAH,7097)
|
|
|
- CONV-TTL-BLO-RTM:
|
|
|
[CTARA](https://cs-ccr-oas1.cern.ch/pls/htmldb_accdb/f?p=104:4:116527584417641::::P4_LETTER,P4_DETAILS,P4_CODE,P4_EC_ID:C,YES,CTARA,7098)
|
|
|
- [How to access the list of installed
|
|
|
modules](https://wikis.cern.ch/display/HT/Accessing+the+list+of+modules+in+CCDB+and+MTF)
|
|
|
- [Accessing the list of modules in CCDB and
|
|
|
MTF](https://wikis.cern.ch/display/HT/Accessing+the+list+of+modules+in+CCDB+and+MTF)
|
|
|
|
|
|
### Rationale behind new TTL to pulse converter system design
|
|
|
|
... | ... | @@ -39,7 +39,22 @@ the pulse conversion systems are envisioned to be placed. |
|
|
- [ELMA 041-270 Index A](https://edms.cern.ch/document/1160627/1)
|
|
|
- [ELMA 041-271 Index A](https://edms.cern.ch/document/1160626/1)
|
|
|
|
|
|
### Board gateware versions
|
|
|
|
|
|
This section lists what gateware is loaded by default to which boards.
|
|
|
|
|
|
To poll the gateware versions for the boards, see [Accessing the list of
|
|
|
modules in CCDB and
|
|
|
MTF](https://wikis.cern.ch/display/HT/Accessing+the+list+of+modules+in+CCDB+and+MTF).
|
|
|
|
|
|
More information about gateware releases can be found on the [Gateware
|
|
|
versions
|
|
|
page](https://www.ohwr.org/project/conv-ttl-blo-gw/wikis/Releases)
|
|
|
|
|
|
- [v0.1 + v2.2](https://www.ohwr.org/project/conv-ttl-blo/uploads/26fd9675df62c12d32b6ce9a632dc24a/gw-0.1-2.2.txt)
|
|
|
- [v0.2 + v3.0](https://www.ohwr.org/project/conv-ttl-blo/uploads/8685d96e6f0a663038e6ca958b7fe950/gw-0.2-3.0.txt)
|
|
|
|
|
|
-----
|
|
|
|
|
|
Theodor-Adrian Stana, Carlos Gil-Soriano, Erik van der Bij - Sept. 2013
|
|
|
Theodor-Adrian Stana, Carlos Gil-Soriano, Erik van der Bij - Oct. 2014
|
|
|
|