... | ... | @@ -59,8 +59,8 @@ fp-top-bot.png:/2136 |
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piggyback on RTM with connectors
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- [Getting started with CONV-TTL-BLO boards](getting-started)
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- [User guide](https://www.ohwr.org/project/conv-ttl-blo/wikis/Documents/CONV-TTL-BLO-User-Guide)
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- [Hardware guide](/hw-guide)
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- [HDL guide](/hdl-guide)
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- [Hardware guide](hw-guide)
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- [HDL guide](hdl-guide)
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- [CERN-specific information](cern-specific)
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- On ELMA crate:
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- I2C communication: [ELMA SysMon to
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... | ... | @@ -94,116 +94,12 @@ fp-top-bot.png:/2136 |
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<td>Start working on project.</td>
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</tr>
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<tr class="even">
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<td>20-07-2011</td>
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<td>[Review of architecture](Review200711).</td>
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</tr>
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<tr class="odd">
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<td>11-08-2011</td>
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<td>Blocking level output circuit simulated. Will be documented.</td>
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</tr>
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<tr class="even">
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<td>16-08-2011</td>
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<td><a href="https://www.ohwr.org/documents/94">Blocking Oscillator documentation</a>. Brief <a href="/BlockingOscillator">web version</a> available.</td>
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</tr>
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<tr class="odd">
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<td>23-08-2011</td>
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<td>Blocking Oscillator prototype made, problems integrating into CTDAH. Moving to a flyback solution.</td>
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</tr>
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<tr class="even">
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<td>29-08-2011</td>
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<td><a href="https://www.ohwr.org/documents/97">Blocking Oscillator Daisy-chain alternatives document</a>. Prototype board already made, waiting for LM2733</td>
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</tr>
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<tr class="odd">
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<td>12-09-2011</td>
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<td>[Functional Specifications Draft proposed](https://www.ohwr.org/project/conv-ttl-blo/wikis/Documents/Functional-Specifications)</td>
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</tr>
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<tr class="even">
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<td>16-09-2011</td>
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<td>The flyback module that outputs the blocking signal works fine.</td>
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</tr>
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<tr class="odd">
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<td>20-09-2011</td>
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<td>[A draft for a clear definition of the Standard Blocking Signal is defined](https://www.ohwr.org/project/conv-ttl-blo/wikis/Documents/Standard-Blocking-Output-Signal-Definition)</td>
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</tr>
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<tr class="even">
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<td>03-10-2011</td>
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<td>PF0552.104NL transformer samples were received. Pulse Converter Unit works nicely.</td>
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</tr>
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<tr class="odd">
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<td>04-10-2011</td>
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<td>Schematics draft done. See: http://svn.ohwr.org/conv-ttl-blo</td>
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</tr>
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<tr class="even">
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<td>11-10-2011</td>
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<td>CTDAH - White Rabbit capable version up in repo (CTDAHalt). Moving to HDL.</td>
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</tr>
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<tr class="odd">
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<td>20-10-2011</td>
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<td>Second Review of architecture. Modifications accomplished to CTDAHalt</td>
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</tr>
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<tr class="even">
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<td>24-10-2011</td>
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<td>Uploaded package containing files for [schematic revision](https://www.ohwr.org/846).</td>
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</tr>
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<tr class="odd">
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<td>03-11-2011</td>
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<td>Changes to the schematics upon Erik's advice. [Files for schematics revision](https://www.ohwr.org/852).</td>
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</tr>
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<tr class="even">
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<td>10-11-2011</td>
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<td>Schematics design review held. Needs major revision and prototyping of a simplified output stage.</td>
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</tr>
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<tr class="odd">
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<td>15-11-2011</td>
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<td>Output stage simplified. Update of the schematics addressing the [points discussed in the revision](Rev10112011Issues).</td>
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</tr>
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<tr class="even">
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<td>21-11-2011</td>
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<td>[Files for Schematics Revision C](https://www.ohwr.org/873).</td>
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</tr>
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<tr class="odd">
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<td>30-11-2011</td>
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<td>Schematics ready for layout. Contacting with Electronics Design Office.</td>
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</tr>
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<tr class="even">
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<td>12-12-2011</td>
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<td>Start of PCB layout.</td>
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</tr>
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<tr class="odd">
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<td>11-01-2012</td>
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<td>Received BOM from DEM. Contacted with Cristine for components.</td>
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</tr>
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<tr class="even">
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<td>12-01-2012</td>
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<td>Added <a href="https://www.ohwr.org/project/conv-ttl-blo/uploads/dbdc5af994a465c6f10f9fb7060600d7/RTMdiffConnectors.xlsx">diff table</a> for using only one RTM motherboard for both conv-ttl-blo and conv-ttl-rs485 projects.</td>
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</tr>
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<tr class="odd">
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<td>16-01-2012</td>
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<td>Added <a href="/RTM-board-detection">Rear Transition Module detection</a> feature.</td>
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</tr>
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<tr class="even">
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<td>19-01-2012</td>
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<td><a href="PCBR20012012">PCB Review Agenda 20-01-2012</a> added.</td>
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</tr>
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<tr class="odd">
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<td>20-01-2012</td>
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<td><a href="PCBN20012012">PCB Review Notes 20-01-2012</a> added. New wiki page: <a href="PulseTransformerRepl">on choosing replacements</a> for pulse transformers.</td>
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</tr>
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<tr class="even">
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<td>30-01-2012</td>
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<td>Waiting for OS-CON availability. Added <a href="https://www.ohwr.org/project/conv-ttl-blo/uploads/dbdc5af994a465c6f10f9fb7060600d7/RTMdiffConnectors.xlsx">RTM pinouts</a> and schematics for <a href="https://www.ohwr.org/project/conv-ttl-blo/tree/master/pcb/conv-ttl-rtm">RTM Motherboard</a> and [RTM Piggyback for Blocking](https://www.ohwr.org/project/conv-ttl-blo/tree/master/pcb/conv-ttl-rtm-blo).</td>
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</tr>
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<tr class="odd">
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<td>06-02-2012</td>
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<td>Schematics and PCB reviewed. [review06022012](review06022012)</td>
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</tr>
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<tr class="even">
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<td>13-02-2012</td>
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<td>Improving schematics and PCB based on review. [review06022012comments](review06022012comments)</td>
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</tr>
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<tr class="odd">
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<td>21-02-2012</td>
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<td>Added more cores (control, multiboot and first image) to the project. See <a href="HDLStatus.[PCB">HDL blocks status</a> Review Notes 20-02-2012](PCBN20022012-added)</td>
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<td><a href="https://www.ohwr.org/project/conv-ttl-blo/wikis/Documents/Standard-Blocking-Output-Signal-Definition">Blocking standard</a> defined.</td>
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</tr>
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<tr class="even">
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<td>24-02-2012</td>
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... | ... | @@ -214,54 +110,6 @@ fp-top-bot.png:/2136 |
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<td>Prototypes received. Testing HDL simple repetition code.</td>
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</tr>
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<tr class="even">
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<td>19-04-2012</td>
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<td>DEM has not already soldered the RTM modules. One week to get them in the lab.</td>
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</tr>
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<tr class="odd">
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<td>20-04-2012</td>
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<td>Basic repetition code works from SPI flash memory. Moving to PTS and ELMA interfacing.</td>
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</tr>
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<tr class="even">
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<td>08-05-2012</td>
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<td>WR core adapted to CONV-TTL-BLO. Bitstream has been generated. Pending the test of WR upon a set up of a WR link.</td>
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</tr>
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<tr class="odd">
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<td>11-05-2012</td>
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<td>RTMs (CONV-TTL-BLO-RTM) received from DEM. Some issues found with the lenght of the pins in 100 pin connector.</td>
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</tr>
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<tr class="even">
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<td>14-05-2012</td>
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<td>A list of tests for CONV-TTL-BLO with the <a href="/HDLStatus">Basic Functionality Bitstream</a> is [available](/Image0tests).</td>
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</tr>
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<tr class="odd">
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<td>19-06-2012</td>
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<td>Running some <a href="/Image1test">tests on image 1</a>. I2C HDL works and moving to SPI for m25p32 HDL core.</td>
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</tr>
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<tr class="even">
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<td>21-08-2012</td>
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<td><a href="https://www.ohwr.org/project/conv-ttl-blo/tree/master/hdl/wr_core_demo">White Rabbit test core</a> works!</td>
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</tr>
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<tr class="odd">
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<td>02-10-2012</td>
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<td>A lot of work put on <a href="https://www.ohwr.org/project/conv-ttl-blo/tree/master/hdl/spi_master_multifield">SPI module</a> for <a href="https://www.ohwr.org/project/conv-ttl-blo/tree/master/hdl/m25p32">Flash programming</a>. Reads and writes have been coarsed verified, still little details to give a final OK.</td>
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</tr>
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<tr class="even">
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<td>03-10-2012</td>
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<td>Speeding up for LS1. <a href="https://www.ohwr.org/project/conv-ttl-blo/repository/entry/pcb/doc/issues/conv-ttl-blo/02446_issues.pdf">Report of issues in CONV-TTL-BLO</a>. <a href="https://www.ohwr.org/project/conv-ttl-blo/tree/master/pcb/conv-ttl-blo-v2">Project files</a>, <a href="https://www.ohwr.org/project/conv-ttl-blo/repository/entry/pcb/conv-ttl-blo-v2/conv-ttl-blo-v2.pdf">schematics pdf</a> and <a href="https://www.ohwr.org/project/conv-ttl-blo/repository/entry/pcb/conv-ttl-blo-v2/Project%20Outputs%20for%20conv-ttl-blo-v2/conv-ttl-blo-v2.pdf">BOM</a> of V2.</td>
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</tr>
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<tr class="odd">
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<td>10-10-2012</td>
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<td>Schematics design review of V2 held.</td>
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</tr>
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<tr class="even">
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<td>22-10-2012</td>
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<td>V2 ready. <a href="https://www.ohwr.org/project/conv-ttl-blo/blob/master/pcb/doc/report/10oct.txt">Report of the design review</a> added. <a href="https://www.ohwr.org/project/conv-ttl-blo/blob/master/pcb/conv-ttl-blo-v2/conv-ttl-blo-v2.pdf">Schematics</a> , <a href="https://www.ohwr.org/project/conv-ttl-blo/tree/master/pcb/conv-ttl-blo-v2/Project%20Outputs%20for%20conv-ttl-blo-v2">BOM</a> and <a href="https://www.ohwr.org/project/conv-ttl-blo/tree/master/pcb/conv-ttl-blo-v2/Schematics">project files</a> up in repo.</td>
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</tr>
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<tr class="odd">
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<td>14-11-2012</td>
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<td><a href="https://edms.cern.ch/nav/P:EDA-02446:V0/I:EDA-02446-V2-0:V0/TAB4">Blocking V2</a> ready for review.</td>
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</tr>
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<tr class="even">
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<td>21-11-2012</td>
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<td>Deployed a Blocking V1 in PS facilities. Source and bitstream available [here](https://www.ohwr.org/project/conv-ttl-blo/uploads/b2aff0ce4516e0dd3a078bdb8a2ae567/basic_trigger.zip)</td>
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</tr>
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... | ... | @@ -274,30 +122,28 @@ fp-top-bot.png:/2136 |
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<td>Received 4 V2 boards. Some assembly problems on two.</td>
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</tr>
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<tr class="odd">
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<td>11-01-2013</td>
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<td>Starting <a href="https://www.ohwr.org/project/conv-ttl-blo/tree/master/doc/TransferKnowledge?rev=basic_trigger_addingGenerics">transfer knowledge</a> of the project to Thedi (Stana).</td>
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</tr>
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<tr class="even">
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<td>22-01-2013</td>
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<td><a href="https://www.ohwr.org/project/conv-ttl-blo/tree/master/doc/TransferKnowledge?rev=basic_trigger_addingGenerics">Transfer knowledge</a> document released.</td>
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</tr>
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<tr class="odd">
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<td>18-02-2013</td>
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<td>Order placed for 25 <a href="http://edms.cern.ch/nav/EDA-02452">RTM</a> and 27 <a href="http://edms.cern.ch/nav/EDA-02453">BLO-RTMP</a> boards.</td>
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</tr>
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<tr class="even">
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<td>27-03-2013</td>
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<td>Modifications needed for all three boards. Not expected before end April.</td>
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<td>15-03-2013</td>
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<td>25x RTMs and 27x BLO-RTMPs received</td>
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</tr>
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<tr class="odd">
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<td>05-06-2013</td>
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<td>25 boards produced.</td>
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<td>25 CONV-TTL-BLO boards and front panels produced.</td>
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</tr>
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<tr class="even">
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<td>19-06-2013</td>
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<td>10 rear panels produced.</td>
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</tr>
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</tbody>
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</table>
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[Complete status](complete-status)
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-----
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Carlos Gil Soriano, Theodor-Adrian Stana, Erik van der Bij - 05 June
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Carlos Gil Soriano, Theodor-Adrian Stana, Erik van der Bij - 21 June
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2013
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