... | ... | @@ -8,15 +8,15 @@ and targeted for connectivity. By dividing the functionality of each |
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board in this way, an improvement can be achieved in terms of ease of
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maintenance.
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A block diagram with the main functionalities carried out by the pulse
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converter system is shown
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below.
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[![](/uploads/e1ee42fca69ff9a6683c7b8d67cc6361/convTTLblo_front_small.jpg)](/uploads/a66c7768842968e12a324a5e8eaceb0c/convTTLblo_front.jpg)
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[![](/uploads/ba6714d0bde37544fcd74e4514a43c77/convTTLblo_top_small.jpg)](/uploads/a896326313ea75fea7db0930a8e11677/convTTLblo_top.jpg)
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BLOschema.png
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## How does it work?
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![](/uploads/ba6714d0bde37544fcd74e4514a43c77/convTTLblo_top_small.jpg)
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A block diagram with the main functionalities carried out by the pulse
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converter system is shown below.
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## How does it work?
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BLOschema.png
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When a pulse is received either in the front panel (TTL level) or the
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rear one (Blocking level), the event is time-tagged in the FPGA and a
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