... | ... | @@ -101,170 +101,48 @@ Useful user documentation can be found at these locations: |
|
|
|
|
|
## Status
|
|
|
|
|
|
<table>
|
|
|
<tbody>
|
|
|
<tr class="odd">
|
|
|
<td><b> <strong>Date</strong> </b></td>
|
|
|
<td><b> <strong>Event</strong> </b></td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>02-03-2011</td>
|
|
|
<td>Stock manager worries about low stock of <a href="http://wikis/display/HT/LA-TTL-BLO+-+Level+adapter+TTL+to+BLO">LA-TTL-BLO</a> modules.</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>01-07-2011</td>
|
|
|
<td>Start working on project.</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>12-09-2011</td>
|
|
|
<td>[Functional Specifications Draft proposed](https://www.ohwr.org/project/conv-ttl-blo/wikis/Documents/Functional-Specifications)</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>20-09-2011</td>
|
|
|
<td><a href="https://www.ohwr.org/project/conv-ttl-blo/wikis/Documents/Standard-Blocking-Output-Signal-Definition">Blocking standard</a> defined.</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>24-02-2012</td>
|
|
|
<td>3 prototypes ordered for 30-03-2012.</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>05-04-2012</td>
|
|
|
<td>Prototypes received. Testing HDL simple repetition code.</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>21-11-2012</td>
|
|
|
<td>Deployed a Blocking V1 in PS facilities. Source and bitstream available [here](https://www.ohwr.org/project/conv-ttl-blo/uploads/b2aff0ce4516e0dd3a078bdb8a2ae567/basic_trigger.zip)</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>10-12-2012</td>
|
|
|
<td>Will build 4 V2's before building another 20 and after that 100. Ordered 25 RTM modules.</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>08-01-2013</td>
|
|
|
<td>Received 4 V2 boards. Some assembly problems on two.</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>18-02-2013</td>
|
|
|
<td>Order placed for 25 <a href="http://edms.cern.ch/nav/EDA-02452">RTM</a> and 27 <a href="http://edms.cern.ch/nav/EDA-02453">BLO-RTMP</a> boards.</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>15-03-2013</td>
|
|
|
<td>25x RTMs and 27x BLO-RTMPs received</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>05-06-2013</td>
|
|
|
<td>25 CONV-TTL-BLO boards and front panels produced.</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>19-06-2013</td>
|
|
|
<td>10 rear panels produced.</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>10-09-2013</td>
|
|
|
<td>Received 15 more rear panels.</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>11-09-2013</td>
|
|
|
<td>Test system set up in LINAC 4 facility (see <a href="testing" class="uri">testing</a> page for more information).</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>09-10-2013</td>
|
|
|
<td>Ordering 100 sets.</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>15-11-2013</td>
|
|
|
<td>Design review held (see [design-review-2013 branch](https://www.ohwr.org/project/conv-ttl-blo/tree/design-review-2013/))</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>20-12-2013</td>
|
|
|
<td>Received 100 front module boards.</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>09-01-2014</td>
|
|
|
<td>Added 100 front modules to stock.</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>12-02-2014</td>
|
|
|
<td>Received 100 produced and assembled RTMs.</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>10-03-2014</td>
|
|
|
<td>CONV-TTL-BLO now with diagnostics support.</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>09-04-2014</td>
|
|
|
<td><a href="https://www.ohwr.org/project/conv-ttl-blo-gw/wikis/Release-2-1">Gateware v2.1</a> released</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>15-04-2014</td>
|
|
|
<td><a href="https://www.ohwr.org/project/conv-ttl-blo-gw/wikis/Release-2-2">Gateware v2.2</a> released</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>26-09-2014</td>
|
|
|
<td><a href="https://www.ohwr.org/project/conv-ttl-blo-gw/wikis/Release-3-0">Gateware v3.0</a> released</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>08-02-2016</td>
|
|
|
<td>Reviving the test system and studying [Issue 1104](https://www.ohwr.org/work_packages/1104)</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>01-07-2016</td>
|
|
|
<td>Schematics, layout and front panel modification requests sent to DEM for V3</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>05-08-2016</td>
|
|
|
<td>EDA-02446-V3-0 Ready for release. Order placed for 3 prototypes. Components ready</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>26-10-2016</td>
|
|
|
<td>EDA-02446-V3-0 Three boards received. Outputs give unexpected overshoot. Will need a V4</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>03-02-2017</td>
|
|
|
<td>EDA-02446-V4-0 <a href="https://www.ohwr.org/project/conv-ttl-blo-hw/wikis/review2017">Review</a> held</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>14-02-2017</td>
|
|
|
<td>Updated <a href="https://www.ohwr.org/project/conv-ttl-blo/wikis/Documents/CONV-TTL-BLO-User-Guide">user manual</a> and hardware <a href="https://www.ohwr.org/wikis/documents/397">design guide</a> for v4 boards</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>8-03-2017</td>
|
|
|
<td>v4 schematics, PCB layout, mechanical parts and manufacturing information available in [EDMS](https://edms.cern.ch/ui/#!master/navigator/item?p:1041794658:1546515533:subdocs)</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>10-03-2017</td>
|
|
|
<td><a href="https://www.ohwr.org/project/conv-ttl-blo-gw/wikis/Release-4-0">Gateware v4.0</a> released</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>20-03-2017</td>
|
|
|
<td>5 prototypes ordered of v4.0 boards, expected from 15-05-2017</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>12-06-2017</td>
|
|
|
<td>5 v4 prototypes have been received, small error on silkscreen leads to issue #1611</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>13-09-2017</td>
|
|
|
<td>Schematics v4-1 released on <a href="https://edms.cern.ch/item/EDA-02446-V4-1/0">EDMS</a> to resolve issue #1611</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>16-10-2017</td>
|
|
|
<td>Prototypes with new firmware successfully running on installations. Error-free since July 20th. Launch of large scale production. 460 motherboards and 405 RTM modules</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>23-01-2018</td>
|
|
|
<td><a href="https://www.ohwr.org/project/conv-ttl-blo-gw/wikis/Release-4-1">Gateware v4.1</a> released</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>20-07-2018</td>
|
|
|
<td>pre-series of 25 v4.1 boards have been delivered to CERN</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>15-08-2018</td>
|
|
|
<td>405 boards of CONV-TTL-RTM-BLO, EDA-02453 v3.2 delivered at CERN</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
|** **Date** **|** **Event** **|
|
|
|
|----|----|
|
|
|
|02-03-2011|Stock manager worries about low stock of [LA-TTL-BLO](http://wikis/display/HT/LA-TTL-BLO+-+Level+adapter+TTL+to+BLO) modules.|
|
|
|
|01-07-2011|Start working on project.|
|
|
|
|12-09-2011|[Functional Specifications Draft proposed](https://www.ohwr.org/project/conv-ttl-blo/wikis/Documents/Functional-Specifications)|
|
|
|
|20-09-2011|[Blocking standard](https://www.ohwr.org/project/conv-ttl-blo/wikis/Documents/Standard-Blocking-Output-Signal-Definition) defined.|
|
|
|
|24-02-2012|3 prototypes ordered for 30-03-2012.|
|
|
|
|05-04-2012|Prototypes received. Testing HDL simple repetition code.|
|
|
|
|21-11-2012|Deployed a Blocking V1 in PS facilities. Source and bitstream available [here](https://www.ohwr.org/project/conv-ttl-blo/uploads/b2aff0ce4516e0dd3a078bdb8a2ae567/basic_trigger.zip)|
|
|
|
|10-12-2012|Will build 4 V2's before building another 20 and after that 100. Ordered 25 RTM modules.|
|
|
|
|08-01-2013|Received 4 V2 boards. Some assembly problems on two.|
|
|
|
|18-02-2013|Order placed for 25 [RTM](http://edms.cern.ch/nav/EDA-02452) and 27 [BLO-RTMP](http://edms.cern.ch/nav/EDA-02453) boards.|
|
|
|
|15-03-2013|25x RTMs and 27x BLO-RTMPs received|
|
|
|
|05-06-2013|25 CONV-TTL-BLO boards and front panels produced.|
|
|
|
|19-06-2013|10 rear panels produced.|
|
|
|
|10-09-2013|Received 15 more rear panels.|
|
|
|
|11-09-2013|Test system set up in LINAC 4 facility (see [testing](testing) page for more information).|
|
|
|
|09-10-2013|Ordering 100 sets.|
|
|
|
|15-11-2013|Design review held (see [design-review-2013 branch](https://www.ohwr.org/project/conv-ttl-blo/tree/design-review-2013/))|
|
|
|
|20-12-2013|Received 100 front module boards.|
|
|
|
|09-01-2014|Added 100 front modules to stock.|
|
|
|
|12-02-2014|Received 100 produced and assembled RTMs.|
|
|
|
|10-03-2014|CONV-TTL-BLO now with diagnostics support.|
|
|
|
|09-04-2014|[Gateware v2.1](https://www.ohwr.org/project/conv-ttl-blo-gw/wikis/Release-2-1) released|
|
|
|
|15-04-2014|[Gateware v2.2](https://www.ohwr.org/project/conv-ttl-blo-gw/wikis/Release-2-2) released|
|
|
|
|26-09-2014|[Gateware v3.0](https://www.ohwr.org/project/conv-ttl-blo-gw/wikis/Release-3-0) released|
|
|
|
|08-02-2016|Reviving the test system and studying [Issue 1104](https://www.ohwr.org/work_packages/1104)|
|
|
|
|01-07-2016|Schematics, layout and front panel modification requests sent to DEM for V3|
|
|
|
|05-08-2016|EDA-02446-V3-0 Ready for release. Order placed for 3 prototypes. Components ready|
|
|
|
|26-10-2016|EDA-02446-V3-0 Three boards received. Outputs give unexpected overshoot. Will need a V4|
|
|
|
|03-02-2017|EDA-02446-V4-0 [Review](https://www.ohwr.org/project/conv-ttl-blo-hw/wikis/review2017) held|
|
|
|
|14-02-2017|Updated [user manual](https://www.ohwr.org/project/conv-ttl-blo/wikis/Documents/CONV-TTL-BLO-User-Guide) and hardware [design guide](https://www.ohwr.org/wikis/documents/397) for v4 boards|
|
|
|
|8-03-2017|v4 schematics, PCB layout, mechanical parts and manufacturing information available in [EDMS](https://edms.cern.ch/ui/#!master/navigator/item?p:1041794658:1546515533:subdocs)|
|
|
|
|10-03-2017|[Gateware v4.0](https://www.ohwr.org/project/conv-ttl-blo-gw/wikis/Release-4-0) released|
|
|
|
|20-03-2017|5 prototypes ordered of v4.0 boards, expected from 15-05-2017|
|
|
|
|12-06-2017|5 v4 prototypes have been received, small error on silkscreen leads to issue #1611|
|
|
|
|13-09-2017|Schematics v4-1 released on [EDMS](https://edms.cern.ch/item/EDA-02446-V4-1/0) to resolve issue #1611|
|
|
|
|16-10-2017|Prototypes with new firmware successfully running on installations. Error-free since July 20th. Launch of large scale production. 460 motherboards and 405 RTM modules|
|
|
|
|23-01-2018|[Gateware v4.1](https://www.ohwr.org/project/conv-ttl-blo-gw/wikis/Release-4-1) released|
|
|
|
|20-07-2018|pre-series of 25 v4.1 boards have been delivered to CERN|
|
|
|
|15-08-2018|405 boards of CONV-TTL-RTM-BLO, EDA-02453 v3.2 delivered at CERN|
|
|
|
|
|
|
|
|
|
[Complete status](complete-status)
|
|
|
|
... | ... | @@ -273,3 +151,4 @@ Useful user documentation can be found at these locations: |
|
|
Theodor-Adrian Stana, Carlos Gil-Soriano, Erik van der Bij, Denia
|
|
|
Bouhired-Ferrag - August 23rd, 2018
|
|
|
|
|
|
|