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Conv TTL Blocking - Testing
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fm-doc: Added clock counter registers to memory map

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fm/doc/hdlg/clk_info.tex 0 → 100644
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\subsection{Clock counter registers}
\label{app:clk-info}
Base address (125-MHz counter): 0x100 \\
Base address (20-MHz counter): 0x120
{
\rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.5\textwidth}}
\hline
\textbf{Offset} & \textbf{Reset} & \textbf{Name}
& \textbf{Description} \\
\hline
\endfirsthead
\hline
\hline
\endhead
\hline
\endfoot
0x00 & 0x00000000 & CNTFULLR & Counter full register \\
0x04 & & & \textit{Reserved} \\
0x08 & & & \textit{Reserved} \\
0x0c & 0x00000000 & CNTMAXR & Counter max value register \\
0x10 & 0x00000000 & CNTVALR & Counter current value register \\
0x14 & 0x00000000 & CNTRSTR & Counter reset register \\
0x18 & 0x00000000 & CNTENR & Counter enable register \\
0x1c & 0xc000ffee & CNTCHKR & Module check register \\
\end{longtable}
}
\subsubsection{CNTFULLR}
\label{app:clk-info-cntfullr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}FULL}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
FULL
} [\emph{read-only}]: Full status bit
\\
1 -- Counter has reached value in MAX register \\ 0 -- Counter not full
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{CNTMAXR -- Counter maximum value}
\label{app:clk-info-cntmaxr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTMAX[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTMAX[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTMAX[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTMAX[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CNTMAX
} [\emph{read-write}]: Maximum value for the counter to count to. \\
When this value is reached, the counter will stop and needs to be reset via the CNTRSTR register.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{CNTVALR -- Counter current value register}
\label{app:clk-info-cntvalr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTVAL[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTVAL[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTVAL[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTVAL[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CNTVAL
} [\emph{read-only}]: Current value of the counter
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{CNTRSTR}
\label{app:clk-info-cntrstr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}CNTRST}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CNTRST
} [\emph{read-write}]: Counter reset bit
\\
1 -- Reset counter \\ 0 -- No effect
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{CNTENR}
\label{app:clk-info-cntenr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}CNTEN}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CNTEN
} [\emph{read-write}]: Counter enable bit
\\
1 -- Enable counter \\ 0 -- No effect
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\subsubsection{CNTCHKR -- Module check register}
\label{app:clk-info-cntchckr}
\vspace{11pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTCHK[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTCHK[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTCHK[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CNTCHK[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CNTCHK
} [\emph{read-only}]: Module check bits
\\
Reset value: 0xc000ffee
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
fm/doc/hdlg/hdlg-pts-conv-ttl-blo.tex
View file @ d40c52d1
......@@ -100,8 +100,8 @@ work, see \\
\pagebreak
\section{Introduction}
\label{sec:intro}
Production Test Suite (PTS) is the environment designed for the functionality tests of
boards at the manufacturing site, right after production. It assures that boards comply
Production Test Suite (PTS) is the environment designed for running functionality tests
on boards at the manufacturing site right after production. It assures that boards comply
with a minimum set of quality rules in terms of soldering, mounting and PCB fabrication
process.
......@@ -192,8 +192,8 @@ The way this test runs can be summarized as follows:
CONV-TTL-BLO
\item the DACs control the tuning inputs of the on-board oscillators, which are input to
the FPGA
\item two counters are driven by these clocks; the values of these counters can be read by the
PTS software
\item two counters are driven by these clocks; the values of these counters (Appendix~\ref{app:clk-info})
can be read by the PTS software
\item the change in frequency of the oscillators can be observed on the rate of change
of the two counters
\item this rate of change is monitored by the PTS software
......@@ -348,6 +348,8 @@ is organized into code sections as shown in Figure~\ref{fig:body}.
\include{pts_regs}
\include{clk_info}
\end{appendices}
%======================================================================================
......
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