Maximum pulse repetition frequency for blocking channels
The thermal properties of the BSH103 power MOSFET and their limiting values, are directly responsible for the achievable repetition frequency on the CONV-TTL-BLO. This has been discussed in depth as part of the blocking output circuit protection work.
In V3 boards and above, current limitation and pulse width-liming trigger circuit (maximum 8us) have been implemented to provide more adequate hardware protection.
However, the FPGA gateware will still be responsible for implementing ceilings on frequency repetition and fixed pulse width values.
For this ceilings to be chosen a direct experimental approach will be taken, informed by:
- MOSFET datasheet parameters.
- Methods and calculations described in an application note from the manufacturer.
- Measurements of the new V3 board prototypes (note 1) performance.
Note 1: As a minor bug has been identified in V3 boards, which has been described in issue #1404. The V3 prototypes used in these stress tests will have the missing resistor manually added, before being permanently added in V4 boards.