Hot-swapping the CONV-TTL-BLO
This page tackles issue #1104 and offers a solution to protect the conv-ttl-blo board components when plugged on a powered chassis, i.e. when it is hot-plugged.
The Hot swap problem affects the 24V blocking output stage circuitry. The working assumption is that the MOSFET is irreversibly damaged due to continuous high currents at the drain.
A key aspect is to note that the hotswap problem occurs in a time frame where the FPGA is not yet configured and therefore is a hardware problem that requires a purely hardware solution.*
Fig.1: Re-constructed schematics of the circuitry controlling the
blocking output pulse*
The reconstructed schematics in fig.1 show the three processes that, controlled by the FPGA, result in the blocking pulse output for one channel.
- Process A: 12V to 24V voltage connversion, active almost directly after power-up. If the boost controller (IC32) is to be disabled (by signal A3) a reset signal (A1) has to be generated by the FPGA and sent through a voltage supervisor (IC29) and an inverter (IC11).
- Process B: Enabling the blocking pulse output. The output is enabled by NANDing (IC10) two signals from the FPGA (B1 and B2), one enables output in general and the other enabling blocking output in particular.
- Process C: Generating the blocking pulse shape. The pulse shape from the FPGA (signal C1) is buffered in IC4 (enabled by B3, from process B) and is used to switch the power MOSFET ON and OFF.
Proposed solutions:
Though a number of approaches can be taken to resolve this problem, a conscious decision was made not to alter the actual output circuitry (the flyback transformer and snubber circuit), as this could lead to other consequences on the already well characterized output pulse. Rather, the choice was made to focus on the circuits controlling the output stage. This page will focus on the two that were actually tested on the board in the lab.
Disabling the 24V blocking supply:
The simplest suggested solution is to ensure that the 24V power supply
is inactive at startup.
The boost converter circuit responsible for 12V to 24V conversion can be
disabled via the DIS pin. This pin is driven via a fully 3.3V-powered IC
chain:
- The RESET_n (A2) output of IC29 is low when supply voltage is low or when the FPGA starts up and drives the MR_n (A1 master reset) signal low. It is otherwise high.
- The RESET_n output is inverted (IC11) and fed to the DIS/EN_n (A3) pin of the Boost converter.
The startup sequence therefore is shown below in fig.2 (a) (Note that
for a very short time, the disable pin to the boost converter is high,
this is because a high MR_n results in RESET_n driven high after a
20ms delay).
The 24V power supply can be disabled by pulling MR_n to GND at startup
(currently left floating by the FPGA and pulled high to 3.3V by IC29),
resulting in fig.2 (b). When the FPGA is fully setup, it activates the
master reset (MR_n) and therefore enables the blocking output (after
20ms delay) as in fig.2
Fig.2: Signal states at (a) power up in current design, (b) Power up
with proposed modification (MR_n is pulled low via 4k7 Ohm resistors),
Their are however some aspects to this solution that are worth pointing out:
- Disabling the 24V blocking supply does not mean suppressing it completely, rather it remains at 12V, which is still a relatively high voltage, potentially capable of causing damage to the board during a hot swap.
- The datasheet of the voltage supervisory chip (IC29) specifies that by connecting the CT pin to the right value capcitor, the RESET_n output delay is programmable between 1 and 10s. Currently it is disconnected so the output is 20ms. By choosing the right capacitor value the delay can be increased to, say 1 second, which will keep the DIS/EN_n pin on the boost controller high and essentially have the same effect as the MR_n pulled low. The two solutions are equivalent as far as disabling the 24V power supply at startup and both will involve the addition of one new component. Note however that the CT capacitor pad is already included in the pcb layout (capacitor C230 in the bottoms layer) and would not require any modification (except in the schematics where the "do not mount" comment should be removed).
- This modification assumes that the 3.3V ICs (IC29 and IC11) are properly powered up at startup. If 3.3V power supply is not immediately available during the hot swap (eg: problem of connectivity) this solution is no longer valid, as the DIS/EN_n pin is low (pulled low internally in IC32) and the 24V supply is active.
Circuit analysis in the absence of the 3.3V power supply
When, through a VME extender board, the 3.3V rail is turned off, lab
tests have shown that the VME crate shuts off the 12V supply. This
indicates a high current demand on the 12V power supply.
What happens to all of the circuits shown in fig.1, in the 3.3V off
scenario, has been analysed and the combined results are shown in
table.1 below. The table records the signal states for each of processes
A, B and C, in normal power on and normal FPGA ON conditions and also
when 3.3V power supply is absent. Note that the table and the complete
associated notes can be found in this
file.
Table 1: Signal states for each process and for the three different
scenarios: normal power on before and after FPGA configuration and power
on without the 3.3V power supply.
Normal power up behaviour is shown in green, while that with 3.3V rail absent is shown in red. Signals with faulty or unwanted transitions, caused by the absence of 3.3V power, are further highlighted, to be compared against the expected state. The chain of events causing failure is numbered 1 to 5:
- Event 1: Signal B3, normally pulled high to 3.3V, is no longer driven and is down to a low state.
- Event 2: Signal C2, output of C1, is high. Because the buffer is enabled as a result of event 1, the high impedance input C1 is interpreted as high in the output.
- Event 3: The Gate pin of the power MOSFET is high and the transistor is turned ON (switch closed).
- Event 4: The MOSFET is conducting, therefore the drain voltage is 0V.
- Event 5: The event chain described is for one blocking output. On the board these events occur on all 18 blocking output circuits (3 output ports for each of the 6 channels). Since all 18 transistors start conducting at the same time, the 12V power supply cannot supply sufficient current and it is turned off. (note that the VME crate's SysMon utility confirms this current overload).
By making sure that signal C1 is not in a high impedance state at power
up, the MOSFET will be prevented from being turned ON, even with the
buffer of IC4 is accidentally enabled (as in event 1).
Therefore the proposed solution is to add 4k7 Ohms pull-down resistors
at the FPGA blocking pulse outputs for each of the 6 channels.
Implementing this in the lab results in the oscilloscope plots of fig.2 below. Compare the output for 3.3V on and off, and also before and after adding pull-down resistors on all 6 FPGA_TRIG_BLO signals.
Fig.3: Oscilloscope output plots for operation with and without 3.3V of
signals in process C. The bottom plots show operation after the addition
of pulled down resistors at the FPGA ouput.
Conclusion and Recommendations:
A clear malfunction has been observed in the blocking output stage
circuitry when, for any reason, the 3.3V rail is not immediately
available at start up. This certainly seems consistent with what would
occur during a hot plug of the CONV-TTL-BLO board.
The proposed solution, which requires the addition of six pull-down
resistors, is light weight and will not add any complexity or alter the
core functionality of the board.
Some observations however are worth making before closing issue #1104:
- Switching off the 5V rail does not cause the same malfunction. Indeed, the 5V level is only used to power the output buffer (IC4). With 5V rail off, the default low pulse value (signal C2 pulled low) will still hold, and the MOSFET will not conduct.
- Similar output enabling buffers exist in the TTL output stage (schematics page 13, IC2,3), with FPGA outputs left similarly floating. By enabling the buffers accidentally a similar malfunction would occur, without resulting in similar damages. It is however good practice to tie low any floating signals, until the FPGA has finished its configuration.
- Though pulling down the MR_n signal has limited benefits as discussed above, it would still be good practice to tie it to ground level until it can be driven by the configured FPGA.