Maximum pulse repetition frequency for blocking channels
The thermal properties of the BSH103 power MOSFET and their limiting values, are directly responsible for the achievable repetition frequency on the CONV-TTL-BLO. This has been discussed in depth as part of the blocking output circuit protection work.
In V3 boards and above, current limitation and pulse width-liming trigger circuit (maximum 8us) have been implemented to provide more adequate hardware protection.
However, the FPGA gateware will still be responsible for implementing ceilings on frequency repetition and fixed pulse width values.
For this ceilings to be chosen a direct experimental approach will be taken, informed by:
- MOSFET datasheet parameters.
- Methods and calculations described in an application note from the manufacturer.
- Measurements of the new V3 board prototypes (note 1) performance.
Aim of stress tests
The goal of tests will be to:
- Continuous mode: Identify maximum pulse frequency supported by the blocking output stage for continuous operation.
- *Fast mode": The CONV-TTL-BLO board can support higher frequencies that the ,aximum defined in the continuous mode, but for a limited amount of time. This mode of operation is also known as burst mode. This time limited
The outcome of these tests can take a number of forms:
- The amount of time the board can sustain maximum rate of repetition, without being damaged.
- The number of pulses that can be repeated at a given rate without causing damage to the board.
- A target average frequency over a time period.
- A relationship between repetition frequency and the time for which the board can sustain it safely.
Minimal pulse definition in the fast repetion mode:
- Pulse width: It shall be reduced from 1.2us to 250ns, in order to be long enough to match exisisting CERN pulse repeaters (Fast versions), and short enough to cause as little temperature rise in the power MOSFET as possible.
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Maximum allowable frequency: This is equivalent to the maximum
duty cycle allowed for 250ns pulses. An initial maximum 12.5% duty
cycle will be assumed. This corresponds to maximum 500kHz pulses.
> This Duty cycle might be increased during further tests to 50% corresponding to 2MHz frequency to see how much it impacts on transistor life.
Test procedure and requirements
Hardware
- CONV-TTL-BLO V3 board plugged on VME64x ELMA crate and reachable via telnet.
- Oscilloscope to check for pulse shape one channel at a time.
Gateware & Software
Based on Pulsetest gateware:* A special gateware release for testing. It gives the possibility to set, in software via I2C, pulse repetition parameters, including:
- Pulse width, repetition frequency and delay.
- Read Input counters.
- Read Output counters.
Procedure:
- In hardware:
In the Elma crate, plug in one CONV-TTL-BLO Front module board and one RTM module.
There are six available channels on the board with equal performance. Two channels will be used
* In software:
- Set pulse width to 250ns.
- Each test will run a chosen repetition frequency, from list: 1kHz, 5kHz, 10kHz,
Note 1: As a minor bug has been identified in V3 boards, which has been described in issue #1404. The V3 prototypes used in these stress tests will have the missing resistor manually added, before being permanently added in V4 boards.