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Conv TTL Blocking - Gateware
Commit f44e8000 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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added test_pulse_regs fw

parent 10c69bc1
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hdl/test_pulse_regs/rtl/Manifest.py 0 → 100644
View file @ f44e8000
files = [
"pulse_cnt_regs.vhd",
"pgen_ctrl_regs.vhd"
]
hdl/test_pulse_regs/rtl/pgen_ctrl_regs.vhd 0 → 100644
View file @ f44e8000
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Pulse generation control registers
---------------------------------------------------------------------------------------
-- File : pgen_ctrl_regs.vhd
-- Author : auto-generated by wbgen2 from pgen_ctrl_regs.wb
-- Created : Fri Aug 16 11:22:20 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pgen_ctrl_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pgen_ctrl_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'channel enable' in reg: 'Enable register'
pgen_ctrl_regs_en_ch_o : out std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 delay register'
pgen_ctrl_regs_ch1_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 delay register'
pgen_ctrl_regs_ch2_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 delay register'
pgen_ctrl_regs_ch3_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 delay register'
pgen_ctrl_regs_ch4_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 delay register'
pgen_ctrl_regs_ch5_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 delay register'
pgen_ctrl_regs_ch6_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 pulse width register'
pgen_ctrl_regs_ch1_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 pulse width register'
pgen_ctrl_regs_ch2_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 pulse width register'
pgen_ctrl_regs_ch3_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 pulse width register'
pgen_ctrl_regs_ch4_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 pulse width register'
pgen_ctrl_regs_ch5_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 pulse width register'
pgen_ctrl_regs_ch6_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 frequency register'
pgen_ctrl_regs_ch1_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 frequency register'
pgen_ctrl_regs_ch2_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 frequency register'
pgen_ctrl_regs_ch3_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 frequency register'
pgen_ctrl_regs_ch4_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 frequency register'
pgen_ctrl_regs_ch5_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 frequency register'
pgen_ctrl_regs_ch6_freq_bits_o : out std_logic_vector(31 downto 0)
);
end pgen_ctrl_regs;
architecture syn of pgen_ctrl_regs is
signal pgen_ctrl_regs_en_ch_int : std_logic_vector(5 downto 0);
signal pgen_ctrl_regs_ch1_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch2_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch3_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch4_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch5_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch6_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch1_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch2_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch3_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch4_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch5_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch6_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch1_freq_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch2_freq_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch3_freq_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch4_freq_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch5_freq_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch6_freq_bits_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
pgen_ctrl_regs_en_ch_int <= "000000";
pgen_ctrl_regs_ch1_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch2_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch3_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch4_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch5_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch6_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch1_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch2_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch3_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch4_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch5_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch6_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch1_freq_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch2_freq_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch3_freq_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch4_freq_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch5_freq_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch6_freq_bits_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(4 downto 0) is
when "00000" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_en_ch_int <= wrdata_reg(5 downto 0);
end if;
rddata_reg(5 downto 0) <= pgen_ctrl_regs_en_ch_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch1_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch1_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch2_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch2_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch3_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch3_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch4_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch4_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch5_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch5_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch6_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch6_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch1_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch1_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch2_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch2_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch3_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch3_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch4_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch4_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch5_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch5_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch6_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch6_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch1_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch1_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch2_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch2_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch3_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch3_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch4_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch4_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch5_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch5_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch6_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch6_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- channel enable
pgen_ctrl_regs_en_ch_o <= pgen_ctrl_regs_en_ch_int;
-- bits
pgen_ctrl_regs_ch1_delay_bits_o <= pgen_ctrl_regs_ch1_delay_bits_int;
-- bits
pgen_ctrl_regs_ch2_delay_bits_o <= pgen_ctrl_regs_ch2_delay_bits_int;
-- bits
pgen_ctrl_regs_ch3_delay_bits_o <= pgen_ctrl_regs_ch3_delay_bits_int;
-- bits
pgen_ctrl_regs_ch4_delay_bits_o <= pgen_ctrl_regs_ch4_delay_bits_int;
-- bits
pgen_ctrl_regs_ch5_delay_bits_o <= pgen_ctrl_regs_ch5_delay_bits_int;
-- bits
pgen_ctrl_regs_ch6_delay_bits_o <= pgen_ctrl_regs_ch6_delay_bits_int;
-- bits
pgen_ctrl_regs_ch1_pwidth_bits_o <= pgen_ctrl_regs_ch1_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch2_pwidth_bits_o <= pgen_ctrl_regs_ch2_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch3_pwidth_bits_o <= pgen_ctrl_regs_ch3_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch4_pwidth_bits_o <= pgen_ctrl_regs_ch4_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch5_pwidth_bits_o <= pgen_ctrl_regs_ch5_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch6_pwidth_bits_o <= pgen_ctrl_regs_ch6_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch1_freq_bits_o <= pgen_ctrl_regs_ch1_freq_bits_int;
-- bits
pgen_ctrl_regs_ch2_freq_bits_o <= pgen_ctrl_regs_ch2_freq_bits_int;
-- bits
pgen_ctrl_regs_ch3_freq_bits_o <= pgen_ctrl_regs_ch3_freq_bits_int;
-- bits
pgen_ctrl_regs_ch4_freq_bits_o <= pgen_ctrl_regs_ch4_freq_bits_int;
-- bits
pgen_ctrl_regs_ch5_freq_bits_o <= pgen_ctrl_regs_ch5_freq_bits_int;
-- bits
pgen_ctrl_regs_ch6_freq_bits_o <= pgen_ctrl_regs_ch6_freq_bits_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/test_pulse_regs/rtl/pgen_ctrl_regs.wb 0 → 100644
View file @ f44e8000
peripheral {
name = "Pulse generation control registers";
description = "Registers containing control signals for the general-purpose pulse generator blocks";
hdl_entity = "pgen_ctrl_regs";
prefix = "pgen_ctrl_regs";
reg {
name = "Enable register";
prefix = "en";
field {
name = "channel enable";
prefix = "ch";
type = SLV;
size = 6;
};
};
reg {
name = "CH1 delay register";
prefix = "ch1_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH2 delay register";
prefix = "ch2_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH3 delay register";
prefix = "ch3_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH4 delay register";
prefix = "ch4_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH5 delay register";
prefix = "ch5_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH6 delay register";
prefix = "ch6_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH1 pulse width register";
prefix = "ch1_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH2 pulse width register";
prefix = "ch2_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH3 pulse width register";
prefix = "ch3_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH4 pulse width register";
prefix = "ch4_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH5 pulse width register";
prefix = "ch5_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH6 pulse width register";
prefix = "ch6_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH1 frequency register";
prefix = "ch1_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH2 frequency register";
prefix = "ch2_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH3 frequency register";
prefix = "ch3_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH4 frequency register";
prefix = "ch4_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH5 frequency register";
prefix = "ch5_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH6 frequency register";
prefix = "ch6_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
};
hdl/test_pulse_regs/rtl/pulse_cnt_regs.vhd 0 → 100644
View file @ f44e8000
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Pulse counter registers
---------------------------------------------------------------------------------------
-- File : pulse_cnt_regs.vhd
-- Author : auto-generated by wbgen2 from pulse_cnt_regs.wb
-- Created : Fri Aug 16 10:41:12 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pulse_cnt_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_cnt_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH1 input'
pulse_cnt_ch1i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH1 output'
pulse_cnt_ch1o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH2 input'
pulse_cnt_ch2i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH2 output'
pulse_cnt_ch2o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH3 input'
pulse_cnt_ch3i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH3 output'
pulse_cnt_ch3o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH4 input'
pulse_cnt_ch4i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH4 output'
pulse_cnt_ch4o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH5 input'
pulse_cnt_ch5i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH5 output'
pulse_cnt_ch5o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 input'
pulse_cnt_ch6i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 output'
pulse_cnt_ch6o_val_i : in std_logic_vector(31 downto 0)
);
end pulse_cnt_regs;
architecture syn of pulse_cnt_regs is
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch1i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch1o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch2i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch2o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch3i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch3o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch4i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch4o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch5i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch5o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch6i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch6o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/test_pulse_regs/rtl/pulse_cnt_regs.wb 0 → 100644
View file @ f44e8000
peripheral {
name = "Pulse counter registers";
description = "Registers containing the values for input and output generated pulses";
hdl_entity = "pulse_cnt_regs";
prefix = "pulse_cnt";
reg {
name = "CH1 input";
prefix = "ch1i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH1 output";
prefix = "ch1o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH2 input";
prefix = "ch2i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH2 output";
prefix = "ch2o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH3 input";
prefix = "ch3i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH3 output";
prefix = "ch3o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH4 input";
prefix = "ch4i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH4 output";
prefix = "ch4o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH5 input";
prefix = "ch5i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH5 output";
prefix = "ch5o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH6 input";
prefix = "ch6i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH6 output";
prefix = "ch6o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
hdl/test_pulse_regs/syn/Makefile 0 → 100644
View file @ f44e8000
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := conv_ttl_blo.xise
ISE_CRAP := *.b conv_ttl_blo_summary.html *.tcl conv_ttl_blo.bld conv_ttl_blo.cmd_log *.drc conv_ttl_blo.lso *.ncd conv_ttl_blo.ngc conv_ttl_blo.ngd conv_ttl_blo.ngr conv_ttl_blo.pad conv_ttl_blo.par conv_ttl_blo.pcf conv_ttl_blo.prj conv_ttl_blo.ptwx conv_ttl_blo.stx conv_ttl_blo.syr conv_ttl_blo.twr conv_ttl_blo.twx conv_ttl_blo.gise conv_ttl_blo.unroutes conv_ttl_blo.ut conv_ttl_blo.xpi conv_ttl_blo.xst conv_ttl_blo_bitgen.xwbt conv_ttl_blo_envsettings.html conv_ttl_blo_guide.ncd conv_ttl_blo_map.map conv_ttl_blo_map.mrp conv_ttl_blo_map.ncd conv_ttl_blo_map.ngm conv_ttl_blo_map.xrpt conv_ttl_blo_ngdbuild.xrpt conv_ttl_blo_pad.csv conv_ttl_blo_pad.txt conv_ttl_blo_par.xrpt conv_ttl_blo_summary.xml conv_ttl_blo_usage.xml conv_ttl_blo_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
USER:=$(HDLMAKE_USER)#take the value from the environment
SERVER:=$(HDLMAKE_SERVER)#take the value from the environment
R_NAME:=conv_ttl_blo
__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
endif
ifeq (x$(SERVER),x)
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
endif
CWD := $(shell pwd)
FILES := ../top/conv_ttl_blo.ucf \
../top/conv_ttl_blo.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../rtl/pulse_cnt_regs.vhd \
../rtl/pgen_ctrl_regs.vhd \
../../reset_gen/rtl/reset_gen.vhd \
../../vbcp_wb/rtl/i2c_slave_pkg.vhd \
../../vbcp_wb/rtl/i2c_slave.vhd \
../../vbcp_wb/rtl/vbcp_wb.vhd \
../../glitch_filt/rtl/glitch_filt.vhd \
../../pulse_gen_gp/rtl/pulse_gen_gp.vhd \
../../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_wfifo.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../../../../../ip_cores/general-cores/modules/common/gc_clk_div.vhd \
../../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
../../../../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd \
../../../../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../../../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../../../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v \
../../../../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
run.tcl \
conv_ttl_blo.xise
#target for running simulation in the remote location
remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
__send_back:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
hdl/test_pulse_regs/syn/Manifest.py 0 → 100644
View file @ f44e8000
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "conv_ttl_blo"
syn_project = "conv_ttl_blo.xise"
modules = {
"local" : [
"../top"
]
}
hdl/test_pulse_regs/syn/conv_ttl_blo.gise 0 → 100644
View file @ f44e8000
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="conv_ttl_blo.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
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hdl/test_pulse_regs/syn/conv_ttl_blo.mcs 0 → 100644
View file @ f44e8000
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/test_pulse_regs/syn/conv_ttl_blo.prm 0 → 100644
View file @ f44e8000
PROMGEN: Xilinx Prom Generator P.28xd
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
promgen -spi -w -u 0 conv_ttl_blo.bit
PROM conv_ttl_blo.prm map: Tue Aug 13 16:17:11 2013
Format Mcs86 (32-bit)
Size 2048K
PROM start 0000:0000
PROM end 001f:ffff
Addr1 Addr2 Date File(s)
0000:0000 0016:a673 Aug 13 16:15:17 2013 conv_ttl_blo.bit
hdl/test_pulse_regs/syn/conv_ttl_blo.xise 0 → 100644
View file @ f44e8000
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<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
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<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|conv_ttl_blo" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/conv_ttl_blo" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="conv_ttl_blo" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="conv_ttl_blo_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="conv_ttl_blo_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="conv_ttl_blo_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="conv_ttl_blo_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
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<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
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<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
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<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
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</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
</file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
</project>
hdl/test_pulse_regs/syn/regtest.ppr 0 → 100644
View file @ f44e8000
<?xml version="1.0"?>
<Project Version="4" Minor="36">
<FileSet Dir="sources_1" File="fileset.xml"/>
<FileSet Dir="constrs_1" File="fileset.xml"/>
<FileSet Dir="sim_1" File="fileset.xml"/>
<RunSet Dir="runs" File="runs.xml"/>
<DefaultLaunch Dir="$PRUNDIR"/>
<DefaultPromote Dir="$PROMOTEDIR"/>
<Config>
<Option Name="Id" Val="e86760636aa04032b3f8aebe5c67672c"/>
<Option Name="Part" Val="xc6slx45tfgg484-3"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compxlib"/>
<Option Name="TargetLanguage" Val="VHDL"/>
<Option Name="TargetSimulator" Val="ISim"/>
<Option Name="Board" Val=""/>
<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
<Option Name="ActiveSimSet" Val=""/>
<Option Name="CxlOverwriteLibs" Val="1"/>
<Option Name="CxlFuncsim" Val="1"/>
<Option Name="CxlTimesim" Val="1"/>
<Option Name="CxlCore" Val="1"/>
<Option Name="CxlEdk" Val="0"/>
<Option Name="CxlExcludeCores" Val="1"/>
<Option Name="CxlExcludeSubLibs" Val="0"/>
</Config>
</Project>
hdl/test_pulse_regs/syn/run.tcl 0 → 100644
View file @ f44e8000
project open conv_ttl_blo.xise
process run {Generate Programming File} -force rerun_all
hdl/test_pulse_regs/top/Manifest.py 0 → 100644
View file @ f44e8000
files = [
"conv_ttl_blo.ucf",
"conv_ttl_blo.vhd"
]
modules = {
"local" : [
"../../reset_gen",
"../../bicolor_led_ctrl",
"../../vbcp_wb",
"../../pulse_gen_gp",
"../rtl"
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git"
]
}
fetchto = "../../../../../ip_cores"
hdl/test_pulse_regs/top/conv_ttl_blo.ucf 0 → 100644
View file @ f44e8000
##--==============================================================================
##-- CERN (BE-CO-HT)
##-- Glitch filter with selectable length
##--==============================================================================
##--
##-- author: Theodor Stana (t.stana@cern.ch)
##-- Carlos-Gil Soriano
##--
##-- date of creation: 2013-04-26
##--
##-- version: 1.0
##--
##-- description:
##-- This file contains the pin definitions for the CONV-TTL-BLO FPGA. The pin
##-- names reflect those of net names at the schematic level. To keep to CERN
##-- coding standards (http://www.ohwr.org/documents/24) and make the code more
##-- readable, the pin names have been lowercased and the pin type is indicated
##-- by its suffix. The suffix "_i" indicates an input pin, "_o" an output pin
##-- and "_b" a bidirectional pin.
##--
##-- An example of net name change is given below:
##-- LED_WR_OWNADDR_I2C -> led_wr_ownaddr_i2c_o
##--
##-- Apart from this, some pins have been renamed completely and do not resemble
##-- the schematics. These pins are:
##-- TTL/INV_TTL_N -> ttl_switch_n_i
##--
##-- dependencies:
##--
##-- references:
##--
##--==============================================================================
##-- GNU LESSER GENERAL PUBLIC LICENSE
##--==============================================================================
##-- This source file is free software; you can redistribute it and/or modify it
##-- under the terms of the GNU Lesser General Public License as published by the
##-- Free Software Foundation; either version 2.1 of the License, or (at your
##-- option) any later version. This source is distributed in the hope that it
##-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
##-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
##-- See the GNU Lesser General Public License for more details. You should have
##-- received a copy of the GNU Lesser General Public License along with this
##-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##--==============================================================================
##-- last changes:
##-- 2013-04-26 Theodor Stana t.stana@cern.ch File modified
##--==============================================================================
##-- TODO: -
##--==============================================================================
##-----------------------------------------------------------------------------
##-- Default attributes
##--
##-- IOSTANDARD = "LVCMOS25"
##-- SLEW = "SLOW"
##-- DRIVE = "12"
##-----------------------------------------------------------------------------
#NET "rst_i" LOC = N20;
#NET "rst_i" IOSTANDARD = "LVCMOS33";
#NET "fpga_sysreset_n_i" LOC = L20;
NET "mr_n_o" LOC = T22;
NET "mr_n_o" IOSTANDARD = LVCMOS33;
# NET "clk20_vcxo_i" LOC = E16;
# NET "clk20_vcxo_i" TNM_NET=clk20_vcxo_i;
# TIMESPEC TSCLK20 = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %;
NET "fpga_clk_p_i" LOC = H12;
NET "fpga_clk_n_i" LOC = G11;
##=============================================================================
##-- FRONT PANEL TTLs
##=============================================================================
##-----------------------------------------------------------------------------
##-- Status LEDs
##-----------------------------------------------------------------------------
NET "led_ctrl0_o" LOC = M18;
NET "led_ctrl0_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl0_oen_o" LOC = T20;
NET "led_ctrl0_oen_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_o" LOC = M17;
NET "led_ctrl1_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_oen_o" LOC = U19;
NET "led_ctrl1_oen_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_2_0_o" LOC = P16;
NET "led_multicast_2_0_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_3_1_o" LOC = P17;
NET "led_multicast_3_1_o" IOSTANDARD = LVCMOS33;
NET "led_wr_gmt_ttl_ttln_o" LOC = N16;
NET "led_wr_gmt_ttl_ttln_o" IOSTANDARD = LVCMOS33;
NET "led_wr_link_syserror_o" LOC = R15;
NET "led_wr_link_syserror_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ok_syspw_o" LOC = R16;
NET "led_wr_ok_syspw_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ownaddr_i2c_o" LOC = N15;
NET "led_wr_ownaddr_i2c_o" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Front channel LEDs
##-----------------------------------------------------------------------------
# NET "pulse_front_led_n_o[1]" LOC = H5;
# NET "pulse_front_led_n_o[1]" IOSTANDARD = LVCMOS33;
# NET "pulse_front_led_n_o[1]" DRIVE = 4;
# NET "pulse_front_led_n_o[1]" SLEW = QUIETIO;
# NET "pulse_front_led_n_o[2]" LOC = J6;
# NET "pulse_front_led_n_o[2]" IOSTANDARD = LVCMOS33;
# NET "pulse_front_led_n_o[2]" DRIVE = 4;
# NET "pulse_front_led_n_o[2]" SLEW = QUIETIO;
# NET "pulse_front_led_n_o[3]" LOC = K6;
# NET "pulse_front_led_n_o[3]" IOSTANDARD = LVCMOS33;
# NET "pulse_front_led_n_o[3]" DRIVE = 4;
# NET "pulse_front_led_n_o[3]" SLEW = QUIETIO;
# NET "pulse_front_led_n_o[4]" LOC = K5;
# NET "pulse_front_led_n_o[4]" IOSTANDARD = LVCMOS33;
# NET "pulse_front_led_n_o[4]" DRIVE = 4;
# NET "pulse_front_led_n_o[4]" SLEW = QUIETIO;
# NET "pulse_front_led_n_o[5]" LOC = M7;
# NET "pulse_front_led_n_o[5]" IOSTANDARD = LVCMOS33;
# NET "pulse_front_led_n_o[5]" DRIVE = 4;
# NET "pulse_front_led_n_o[5]" SLEW = QUIETIO;
# NET "pulse_front_led_n_o[6]" LOC = M6;
# NET "pulse_front_led_n_o[6]" IOSTANDARD = LVCMOS33;
# NET "pulse_front_led_n_o[6]" DRIVE = 4;
# NET "pulse_front_led_n_o[6]" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- Rear LEDs
##-----------------------------------------------------------------------------
# NET "pulse_rear_led_n_o[1]" LOC = AB17;
# NET "pulse_rear_led_n_o[1]" IOSTANDARD = LVCMOS33;
# NET "pulse_rear_led_n_o[1]" DRIVE = 4;
# NET "pulse_rear_led_n_o[1]" SLEW = QUIETIO;
# NET "pulse_rear_led_n_o[2]" LOC = AB19;
# NET "pulse_rear_led_n_o[2]" IOSTANDARD = LVCMOS33;
# NET "pulse_rear_led_n_o[2]" DRIVE = 4;
# NET "pulse_rear_led_n_o[2]" SLEW = QUIETIO;
# NET "pulse_rear_led_n_o[3]" LOC = AA16;
# NET "pulse_rear_led_n_o[3]" IOSTANDARD = LVCMOS33;
# NET "pulse_rear_led_n_o[3]" DRIVE = 4;
# NET "pulse_rear_led_n_o[3]" SLEW = QUIETIO;
# NET "pulse_rear_led_n_o[4]" LOC = AA18;
# NET "pulse_rear_led_n_o[4]" IOSTANDARD = LVCMOS33;
# NET "pulse_rear_led_n_o[4]" DRIVE = 4;
# NET "pulse_rear_led_n_o[4]" SLEW = QUIETIO;
# NET "pulse_rear_led_n_o[5]" LOC = AB16;
# NET "pulse_rear_led_n_o[5]" IOSTANDARD = LVCMOS33;
# NET "pulse_rear_led_n_o[5]" DRIVE = 4;
# NET "pulse_rear_led_n_o[5]" SLEW = QUIETIO;
# NET "pulse_rear_led_n_o[6]" LOC = AB18;
# NET "pulse_rear_led_n_o[6]" IOSTANDARD = LVCMOS33;
# NET "pulse_rear_led_n_o[6]" DRIVE = 4;
# NET "pulse_rear_led_n_o[6]" SLEW = QUIETIO;
#
##-----------------------------------------------------------------------------
##-- TTL trigger I/O
##-----------------------------------------------------------------------------
# NET "fpga_input_ttl_n_i[1]" LOC = T2;
# NET "fpga_input_ttl_n_i[1]" IOSTANDARD = LVCMOS33;
# NET "fpga_input_ttl_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "fpga_input_ttl_n_i[2]" LOC = U3;
# NET "fpga_input_ttl_n_i[2]" IOSTANDARD = LVCMOS33;
# NET "fpga_input_ttl_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "fpga_input_ttl_n_i[3]" LOC = V5;
# NET "fpga_input_ttl_n_i[3]" IOSTANDARD = LVCMOS33;
# NET "fpga_input_ttl_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "fpga_input_ttl_n_i[4]" LOC = W4;
# NET "fpga_input_ttl_n_i[4]" IOSTANDARD = LVCMOS33;
# NET "fpga_input_ttl_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "fpga_input_ttl_n_i[5]" LOC = T6;
# NET "fpga_input_ttl_n_i[5]" IOSTANDARD = LVCMOS33;
# NET "fpga_input_ttl_n_i[5]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "fpga_input_ttl_n_i[6]" LOC = T3;
# NET "fpga_input_ttl_n_i[6]" IOSTANDARD = LVCMOS33;
# NET "fpga_input_ttl_n_i[6]" CLOCK_DEDICATED_ROUTE = FALSE;
#
# NET "fpga_out_ttl_o[1]" LOC = C1;
# NET "fpga_out_ttl_o[1]" IOSTANDARD = LVCMOS33;
# NET "fpga_out_ttl_o[2]" LOC = F2;
# NET "fpga_out_ttl_o[2]" IOSTANDARD = LVCMOS33;
# NET "fpga_out_ttl_o[3]" LOC = F5;
# NET "fpga_out_ttl_o[3]" IOSTANDARD = LVCMOS33;
# NET "fpga_out_ttl_o[4]" LOC = H4;
# NET "fpga_out_ttl_o[4]" IOSTANDARD = LVCMOS33;
# NET "fpga_out_ttl_o[5]" LOC = J4;
# NET "fpga_out_ttl_o[5]" IOSTANDARD = LVCMOS33;
# NET "fpga_out_ttl_o[6]" LOC = H2;
# NET "fpga_out_ttl_o[6]" IOSTANDARD = LVCMOS33;
#
##-----------------------------------------------------------------------------
##-- Inverted TTL I/O
##-----------------------------------------------------------------------------
# NET "inv_in_n_i[1]" LOC = V2;
# NET "inv_in_n_i[1]" IOSTANDARD = LVCMOS33;
# NET "inv_in_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "inv_in_n_i[2]" LOC = W3;
# NET "inv_in_n_i[2]" IOSTANDARD = LVCMOS33;
# NET "inv_in_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "inv_in_n_i[3]" LOC = Y2;
# NET "inv_in_n_i[3]" IOSTANDARD = LVCMOS33;
# NET "inv_in_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "inv_in_n_i[4]" LOC = AA2;
# NET "inv_in_n_i[4]" IOSTANDARD = LVCMOS33;
# NET "inv_in_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "inv_out_o[1]" LOC = J3;
# NET "inv_out_o[1]" IOSTANDARD = LVCMOS33;
# NET "inv_out_o[2]" LOC = L3;
# NET "inv_out_o[2]" IOSTANDARD = LVCMOS33;
# NET "inv_out_o[3]" LOC = M3;
# NET "inv_out_o[3]" IOSTANDARD = LVCMOS33;
# NET "inv_out_o[4]" LOC = P2;
# NET "inv_out_o[4]" IOSTANDARD = LVCMOS33;
##=============================================================================
##-- RTM signals
##=============================================================================
##-----------------------------------------------------------------------------
##-- Blocking I/O
##-----------------------------------------------------------------------------
# NET "fpga_blo_in_i[1]" LOC = Y9;
# NET "fpga_blo_in_i[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_blo_in_i[2]" LOC = AA10;
# NET "fpga_blo_in_i[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_blo_in_i[3]" LOC = W12;
# NET "fpga_blo_in_i[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_blo_in_i[4]" LOC = AA6;
# NET "fpga_blo_in_i[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_blo_in_i[5]" LOC = Y7;
# NET "fpga_blo_in_i[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_blo_in_i[6]" LOC = AA8;
# NET "fpga_blo_in_i[6]" IOSTANDARD = "LVCMOS33";
#
# NET "fpga_trig_blo_o[1]" LOC = W9;
# NET "fpga_trig_blo_o[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_trig_blo_o[2]" LOC = T10;
# NET "fpga_trig_blo_o[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_trig_blo_o[3]" LOC = V7;
# NET "fpga_trig_blo_o[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_trig_blo_o[4]" LOC = U9;
# NET "fpga_trig_blo_o[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_trig_blo_o[5]" LOC = T8;
# NET "fpga_trig_blo_o[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_trig_blo_o[6]" LOC = R9;
# NET "fpga_trig_blo_o[6]" IOSTANDARD = "LVCMOS33";
##=============================================================================
##-- VME CONNECTOR SIGNALS
##=============================================================================
##-----------------------------------------------------------------------------
##-- I2C lines
##-----------------------------------------------------------------------------
NET "scl_i" LOC = F19;
NET "scl_i" IOSTANDARD = LVCMOS33;
NET "scl_o" LOC = E20;
NET "scl_o" IOSTANDARD = LVCMOS33;
NET "scl_o" DRIVE = 4;
NET "scl_oe_o" LOC = H18;
NET "scl_oe_o" IOSTANDARD = LVCMOS33;
NET "scl_oe_o" DRIVE = 4;
# NET "scl_oe_o" PULLDOWN;
NET "sda_i" LOC = G20;
NET "sda_i" IOSTANDARD = LVCMOS33;
NET "sda_o" LOC = F20;
NET "sda_o" IOSTANDARD = LVCMOS33;
NET "sda_o" SLEW = FAST;
NET "sda_o" DRIVE = 4;
# NET "sda_o" PULLUP;
NET "sda_oe_o" LOC = J19;
NET "sda_oe_o" IOSTANDARD = LVCMOS33;
NET "sda_oe_o" SLEW = FAST;
NET "sda_oe_o" DRIVE = 4;
# NET "sda_oe_o" PULLDOWN;
##-----------------------------------------------------------------------------
##-- Geographical Address
##-----------------------------------------------------------------------------
NET "fpga_ga_i[0]" LOC = H20;
NET "fpga_ga_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[1]" LOC = J20;
NET "fpga_ga_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[2]" LOC = K19;
NET "fpga_ga_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[3]" LOC = K20;
NET "fpga_ga_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[4]" LOC = L19;
NET "fpga_ga_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_gap_i" LOC = H19;
NET "fpga_gap_i" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- ROM memory
###-----------------------------------------------------------------------------
#NET "fpga_prom_cclk_o" LOC = Y20;
#NET "fpga_prom_cclk_o" IOSTANDARD = "LVCMOS33";
#NET "fpga_prom_cso_b_n_o" LOC = AA3;
#NET "fpga_prom_cso_b_n_o" IOSTANDARD = "LVCMOS33";
#NET "fpga_prom_miso_i" LOC = AA20;
#NET "fpga_prom_miso_i" IOSTANDARD = "LVCMOS33";
#NET "fpga_prom_mosi_o" LOC = AB20;
#NET "fpga_prom_mosi_o" IOSTANDARD = "LVCMOS33";
#
#
###=============================================================================
###-- WHITE RABBIT
###=============================================================================
###-----------------------------------------------------------------------------
###-- Thermo for UID
###-----------------------------------------------------------------------------
#NET "thermometer_b" LOC = B1;
#NET "thermometer_b" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- DAC control
###-----------------------------------------------------------------------------
#NET "fpga_plldac1_din_o" LOC = AB14;
#NET "fpga_plldac1_din_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac1_sclk_o" LOC = AA14;
#NET "fpga_plldac1_sclk_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac1_sync_n_o" LOC = AB15;
#NET "fpga_plldac1_sync_n_o" IOSTANDARD = LVCMOS33;
#
#NET "fpga_plldac2_din_o" LOC = W14;
#NET "fpga_plldac2_din_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac2_sclk_o" LOC = Y14;
#NET "fpga_plldac2_sclk_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac2_sync_n_o" LOC = W13;
#NET "fpga_plldac2_sync_n_o" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- SFP connection
###-----------------------------------------------------------------------------
##NET "fpga_sfp_los_i" LOC = G3;
## NET "fpga_sfp_los_i" IOSTANDARD = "LVCMOS33";
##NET "fpga_sfp_mod_def0_i" LOC = K8;
## NET "fpga_sfp_mod_def0_i" IOSTANDARD = "LVCMOS33";
##NET "fpga_sfp_rate_select_o" LOC = C4;
## NET "fpga_sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
#NET "fpga_sfp_mod_def1_b" LOC = G4;
#NET "fpga_sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
#
#NET "fpga_sfp_mod_def2_b" LOC = F3;
#NET "fpga_sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
##NET "fpga_sfp_tx_disable_o" LOC = E4;
## NET "fpga_sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
##NET "fpga_sfp_tx_fault_i" LOC = D2;
## NET "fpga_sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
###-----------------------------------------------------------------------------
###-- FPGA MGT lines
###-----------------------------------------------------------------------------
#NET "fpga_mgt_clk0_p_i" LOC = A10;
#NET "fpga_mgt_clk0_n_i" LOC = B10;
#
#NET "mgt_sfp_rx0_p_i" LOC = D7;
#NET "mgt_sfp_rx0_n_i" LOC = C7;
#
#NET "mgt_sfp_tx0_p_o" LOC = B6;
#NET "mgt_sfp_tx0_n_o" LOC = A6;
###=============================================================================
###-- ADDITIONAL PINS
###=============================================================================
# NET "fpga_oe_o" LOC = R3;
# NET "fpga_oe_o" IOSTANDARD = LVCMOS33;
# NET "fpga_oe_o" DRIVE = 4;
# NET "fpga_oe_o" SLEW = QUIETIO;
#
# NET "fpga_blo_oe_o" LOC = P5;
# NET "fpga_blo_oe_o" IOSTANDARD = LVCMOS33;
# NET "fpga_blo_oe_o" DRIVE = 4;
# NET "fpga_blo_oe_o" SLEW = QUIETIO;
# NET "fpga_trig_ttl_oe_o" LOC = N3;
# NET "fpga_trig_ttl_oe_o" IOSTANDARD = LVCMOS33;
# NET "fpga_trig_ttl_oe_o" DRIVE = 4;
# NET "fpga_trig_ttl_oe_o" SLEW = QUIETIO;
#
# NET "fpga_inv_oe_o" LOC = P6;
# NET "fpga_inv_oe_o" IOSTANDARD = LVCMOS33;
# NET "fpga_inv_oe_o" DRIVE = 4;
# NET "fpga_inv_oe_o" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- Configuration Switches
##-----------------------------------------------------------------------------
# NET "extra_switch_n_i[1]" LOC = F22;
# NET "extra_switch_n_i[1]" IOSTANDARD = "LVCMOS33";
# NET "extra_switch_n_i[2]" LOC = G22;
# NET "extra_switch_n_i[2]" IOSTANDARD = "LVCMOS33";
# NET "extra_switch_n_i[3]" LOC = H21;
# NET "extra_switch_n_i[3]" IOSTANDARD = "LVCMOS33";
# NET "extra_switch_n_i[4]" LOC = H22;
# NET "extra_switch_n_i[4]" IOSTANDARD = "LVCMOS33";
# NET "extra_switch_n_i[5]" LOC = J22;
# NET "extra_switch_n_i[5]" IOSTANDARD = "LVCMOS33";
# NET "extra_switch_n_i[6]" LOC = K21;
# NET "extra_switch_n_i[6]" IOSTANDARD = "LVCMOS33";
# NET "extra_switch_n_i[7]" LOC = K22;
# NET "extra_switch_n_i[7]" IOSTANDARD = "LVCMOS33";
# NET "ttl_switch_n_i" LOC = L22;
# NET "ttl_switch_n_i" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Motherboard and piggyback IDs
##-----------------------------------------------------------------------------
# NET "fpga_rtmm_n_i[0]" LOC = V21;
# NET "fpga_rtmm_n_i[0]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmm_n_i[1]" LOC = V22;
# NET "fpga_rtmm_n_i[1]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmm_n_i[2]" LOC = U22;
# NET "fpga_rtmm_n_i[2]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmp_n_i[0]" LOC = W22;
# NET "fpga_rtmp_n_i[0]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmp_n_i[1]" LOC = Y22;
# NET "fpga_rtmp_n_i[1]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmp_n_i[2]" LOC = Y21;
# NET "fpga_rtmp_n_i[2]" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- General purpose
###-----------------------------------------------------------------------------
# NET "fpga_header_out_n_o[1]" LOC = F15;
# NET "fpga_header_out_n_o[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[2]" LOC = F16;
# NET "fpga_header_out_n_o[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[3]" LOC = F17;
# NET "fpga_header_out_n_o[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[4]" LOC = F14;
# NET "fpga_header_out_n_o[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[5]" LOC = H14;
# NET "fpga_header_out_n_o[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[6]" LOC = H13;
# NET "fpga_header_out_n_o[6]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[1]" LOC = A17;
# NET "fpga_header_in_n_i[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[2]" LOC = A18;
# NET "fpga_header_in_n_i[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[3]" LOC = B18;
# NET "fpga_header_in_n_i[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[4]" LOC = A19;
# NET "fpga_header_in_n_i[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[5]" LOC = A20;
# NET "fpga_header_in_n_i[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[6]" LOC = B20;
# NET "fpga_header_in_n_i[6]" IOSTANDARD = "LVCMOS33";
# NET "cmp_i2c_bridge/i2c_addr_i[6]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/i2c_addr_i[5]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/i2c_addr_i[4]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/i2c_addr_i[3]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/i2c_addr_i[2]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/i2c_addr_i[1]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/i2c_addr_i[0]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[7]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[6]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[5]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[4]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[3]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[2]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[1]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[0]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[11]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[10]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[9]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[8]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[7]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[6]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[5]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[4]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[3]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[2]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[1]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[0]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/i2c_done_o" KEEP = "TRUE";
# NET "ram_we" KEEP = "TRUE";
# NET "xbar_master_out[0]_cyc" KEEP = "TRUE";
# NET "xbar_master_out[0]_stb" KEEP = "TRUE";
# NET "xbar_master_out[0]_we" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[11]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[10]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[9]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[8]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[7]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[6]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[5]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[4]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[3]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[2]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[1]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[0]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[31]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[30]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[29]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[28]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[27]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[26]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[25]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[24]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[23]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[22]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[21]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[20]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[19]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[18]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[17]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[16]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[15]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[14]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[13]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[12]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[11]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[10]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[9]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[8]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[7]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[6]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[5]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[4]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[3]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[2]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[1]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[0]" KEEP = "TRUE";
# NET "ram_ack" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[31]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[30]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[29]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[28]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[27]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[26]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[25]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[24]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[23]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[22]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[21]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[20]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[19]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[18]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[17]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[16]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[15]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[14]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[13]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[12]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[11]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[10]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[9]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[8]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[7]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[6]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[5]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[4]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[3]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[2]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[1]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[0]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[31]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[30]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[29]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[28]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[27]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[26]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[25]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[24]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[23]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[22]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[21]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[20]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[19]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[18]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[17]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[16]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[15]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[14]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[13]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[12]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[11]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[10]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[9]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[8]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[7]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[6]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[5]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[4]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[3]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[2]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[1]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[0]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[31]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[30]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[29]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[28]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[27]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[26]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[25]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[24]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[23]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[22]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[21]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[20]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[19]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[18]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[17]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[16]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[15]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[14]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[13]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[12]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[11]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[10]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[9]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[8]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[7]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[6]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[5]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[4]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[3]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[2]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[1]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[0]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[31]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[30]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[29]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[28]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[27]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[26]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[25]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[24]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[23]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[22]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[21]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[20]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[19]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[18]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[17]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[16]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[15]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[14]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[13]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[12]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[11]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[10]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[9]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[8]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[7]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[6]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[5]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[4]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[3]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[2]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[1]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[0]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_ack" KEEP = "TRUE";
# NET "xbar_slave_in[0]_cyc" KEEP = "TRUE";
# NET "xbar_slave_in[0]_we" KEEP = "TRUE";
# NET "xbar_slave_in[0]_stb" KEEP = "TRUE";
# NET "xbar_slave_out[0]_err" KEEP = "TRUE";
hdl/test_pulse_regs/top/conv_ttl_blo.vhd 0 → 100644
View file @ f44e8000
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO
-- http://www.ohwr.org/projects/conv-ttl-blo
--------------------------------------------------------------------------------
--
-- unit name: conv_ttl_blo.vhd
--
-- author: Theodor-Adrian Stana (t.stana@cern.ch)
--
-- version: 1.0
--
-- description: Top entity of CONV-TTL-BLO
--
-- dependencies:
--
-- references:
-- [1] ELMA, Access to board data using SNMP and I2C
-- http://www.ohwr.org/documents/227
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use unisim.vcomponents.all;
use work.bicolor_led_ctrl_pkg.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
entity conv_ttl_blo is
generic
(
g_nr_ttl_chan : natural := 6;
g_nr_inv_chan : natural := 4
);
port
(
-- Clock lines
fpga_clk_p_i : in std_logic; --Using the 125MHz clock
fpga_clk_n_i : in std_logic;
-- LEDs
led_ctrl0_o : out std_logic;
led_ctrl0_oen_o : out std_logic;
led_ctrl1_o : out std_logic;
led_ctrl1_oen_o : out std_logic;
led_multicast_2_0_o : out std_logic;
led_multicast_3_1_o : out std_logic;
led_wr_gmt_ttl_ttln_o : out std_logic;
led_wr_link_syserror_o : out std_logic;
led_wr_ok_syspw_o : out std_logic;
led_wr_ownaddr_i2c_o : out std_logic;
-- I/Os for pulses
pulse_front_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
pulse_rear_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_input_ttl_n_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_out_ttl_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_blo_in_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_trig_blo_o : out std_logic_vector(g_nr_ttl_chan downto 1);
inv_in_n_i : in std_logic_vector(g_nr_inv_chan downto 1);
inv_out_o : out std_logic_vector(g_nr_inv_chan downto 1);
-- Output enable lines
fpga_oe_o : out std_logic;
fpga_blo_oe_o : out std_logic;
fpga_trig_ttl_oe_o : out std_logic;
fpga_inv_oe_o : out std_logic;
--TTL/INV_TTL_N
ttl_switch_n_i : in std_logic;
extra_switch_n_i : in std_logic_vector(7 downto 1);
-- Lines for the i2c_slave
scl_i : in std_logic;
scl_o : out std_logic;
scl_oe_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_oe_o : out std_logic;
fpga_ga_i : in std_logic_vector(4 downto 0);
fpga_gap_i : in std_logic;
-- It allows power sequencing of the 24V rail after a security delay
mr_n_o : out std_logic
);
end conv_ttl_blo;
architecture behav of conv_ttl_blo is
--============================================================================
-- Type declarations
--============================================================================
type t_pulse_counter is array(1 to g_nr_ttl_chan) of unsigned(31 downto 0);
type t_pulse_led_counter is array (1 to g_nr_ttl_chan) of unsigned(22 downto 0);
type t_pgen_ctrl_reg is array (1 to 6) of std_logic_vector(31 downto 0);
--============================================================================
-- Constant declarations
--============================================================================
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 3;
-----------------------------------------
-- Memory map
-- * all registers are word-addressable
-- * all registers are word-aligned
-----------------------------------------
-- MEM [000-FFF]
-----------------------------------------
-- slave order definitions
constant c_slv_pgen_ctrl : natural := 0;
constant c_slv_pulse_cnt : natural := 1;
constant c_slv_mem : natural := 2;
-- base address definitions
constant c_addr_pgen_ctrl : t_wishbone_address := x"00000000";
constant c_addr_pulse_cnt : t_wishbone_address := x"00000080";
constant c_addr_mem : t_wishbone_address := x"00000100";
-- address mask definitions
constant c_mask_pgen_ctrl : t_wishbone_address := x"00000FF0";
constant c_mask_pulse_cnt : t_wishbone_address := x"00000F80";
constant c_mask_mem : t_wishbone_address := x"00000F00";
-- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_pgen_ctrl => c_addr_pgen_ctrl,
c_slv_pulse_cnt => c_addr_pulse_cnt,
c_slv_mem => c_addr_mem
);
-- masks constant for Wishbone crossbar
constant c_masks : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_pgen_ctrl => c_mask_pgen_ctrl,
c_slv_pulse_cnt => c_mask_pulse_cnt,
c_slv_mem => c_mask_mem
);
--============================================================================
-- Component declarations
--============================================================================
-- Reset generator component
-- (use: global reset generation, output reset generation)
component reset_gen is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time : positive := 5_000_000
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
rst_n_o : out std_logic
);
end component reset_gen;
-- I2C bridge
-- (use: convert I2C transfers into WB transfers on memmapped registers)
component vbcp_wb is
port
(
-- Clock, reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C lines
sda_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
-- I2C address and status
i2c_addr_i : in std_logic_vector(6 downto 0);
i2c_done_o : out std_logic;
i2c_err_o : out std_logic;
-- Wishbone master signals
wbm_stb_o : out std_logic;
wbm_cyc_o : out std_logic;
wbm_sel_o : out std_logic_vector(3 downto 0);
wbm_we_o : out std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_adr_o : out std_logic_vector(31 downto 0);
wbm_ack_i : in std_logic;
wbm_rty_i : in std_logic;
wbm_err_i : in std_logic
);
end component vbcp_wb;
-- General-purpose pulse generator component
-- (usage: generate pulses on each channel output)
component pulse_gen_gp is
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic;
delay_i : in std_logic_vector(31 downto 0);
pwidth_i : in std_logic_vector(31 downto 0);
freq_i : in std_logic_vector(31 downto 0);
pulse_o : out std_logic
);
end component pulse_gen_gp;
-- Pulse generator control registers component
-- (usage: contains bits and values to control the pulse_gen_gp component)
component pgen_ctrl_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'channel enable' in reg: 'Enable register'
pgen_ctrl_regs_en_ch_o : out std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 delay register'
pgen_ctrl_regs_ch1_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 delay register'
pgen_ctrl_regs_ch2_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 delay register'
pgen_ctrl_regs_ch3_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 delay register'
pgen_ctrl_regs_ch4_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 delay register'
pgen_ctrl_regs_ch5_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 delay register'
pgen_ctrl_regs_ch6_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 pulse width register'
pgen_ctrl_regs_ch1_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 pulse width register'
pgen_ctrl_regs_ch2_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 pulse width register'
pgen_ctrl_regs_ch3_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 pulse width register'
pgen_ctrl_regs_ch4_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 pulse width register'
pgen_ctrl_regs_ch5_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 pulse width register'
pgen_ctrl_regs_ch6_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 frequency register'
pgen_ctrl_regs_ch1_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 frequency register'
pgen_ctrl_regs_ch2_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 frequency register'
pgen_ctrl_regs_ch3_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 frequency register'
pgen_ctrl_regs_ch4_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 frequency register'
pgen_ctrl_regs_ch5_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 frequency register'
pgen_ctrl_regs_ch6_freq_bits_o : out std_logic_vector(31 downto 0)
);
end component pgen_ctrl_regs;
-- Pulse counter registers component
-- (usage: store values of pulse counters)
component pulse_cnt_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH1 input'
pulse_cnt_ch1i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH1 output'
pulse_cnt_ch1o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH2 input'
pulse_cnt_ch2i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH2 output'
pulse_cnt_ch2o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH3 input'
pulse_cnt_ch3i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH3 output'
pulse_cnt_ch3o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH4 input'
pulse_cnt_ch4i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH4 output'
pulse_cnt_ch4o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH5 input'
pulse_cnt_ch5i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH5 output'
pulse_cnt_ch5o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 input'
pulse_cnt_ch6i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 output'
pulse_cnt_ch6o_val_i : in std_logic_vector(31 downto 0)
);
end component pulse_cnt_regs;
--============================================================================
-- Signal declarations
--============================================================================
-- Clock signals
signal clk125 : std_logic;
-- Reset signals
signal rst_n, rst : std_logic;
-- Wishbone crossbar signals
signal xbar_slave_in : t_wishbone_slave_in_array (c_nr_masters - 1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_nr_masters - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_nr_slaves - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array(c_nr_slaves - 1 downto 0);
-- RAM signals
signal ram_we : std_logic;
signal ram_ack : std_logic;
-- Signal for controlling the bicolor LED matrix
signal bicolor_led_state : std_logic_vector(23 downto 0);
-- VBCP bridge signals
signal i2c_done : std_logic;
signal i2c_err : std_logic;
signal i2c_err_led : std_logic;
signal i2c_up : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0);
signal led_i2c : std_logic;
signal led_i2c_clkdiv : unsigned(22 downto 0);
signal led_i2c_cnt : unsigned( 2 downto 0);
signal blink_state : std_logic;
-- Pulse enable signals
signal oe, ttl_oe : std_logic;
signal blo_oe, inv_oe : std_logic;
signal ch_en : std_logic_vector(g_nr_ttl_chan downto 1);
-- Pulse generation signals
signal trig_ttl_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_blo_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_synced : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_synced_edge: std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse, pulse_d0 : std_logic_vector(g_nr_ttl_chan downto 1);
-- Pulse LED signals
signal pulse_leds : std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse_led_cnt : t_pulse_led_counter;
-- Pulse generator and counter register signals
signal cnt_in, cnt_out : t_pulse_counter;
signal delay_reg : t_pgen_ctrl_reg;
signal pwidth_reg : t_pgen_ctrl_reg;
signal freq_reg : t_pgen_ctrl_reg;
begin
--============================================================================
-- Generate 125 MHz global signal from differential lines
--============================================================================
cmp_125_diff_buf : IBUFGDS
generic map
(
DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE
)
port map
(
I => fpga_clk_p_i,
IB => fpga_clk_n_i,
O => clk125
);
--============================================================================
-- Internal and external reset generation
--============================================================================
-- Configure reset generator for 96ms power-on reset
cmp_reset_gen : reset_gen
generic map
(
-- Reset time: 12 * 8ns * (10**6) = 96 ms
g_reset_time => 12*(10**6)
)
port map
(
clk_i => clk125,
rst_i => '0',
rst_n_o => rst_n
);
-- rst <= not rst_n;
mr_n_o <= rst_n;
--============================================================================
-- I2C bridge logic
--============================================================================
-- Set the I2C address signal according to ELMA protocol [1]
i2c_addr <= "10" & fpga_ga_i;
-- Instantiate VBCP bridge component
cmp_i2c_bridge : vbcp_wb
port map
(
-- Clock, reset
clk_i => clk125,
rst_n_i => rst_n,
-- I2C lines
sda_en_o => sda_oe_o,
sda_i => sda_i,
sda_o => sda_o,
scl_en_o => scl_oe_o,
scl_i => scl_i,
scl_o => scl_o,
-- I2C address and status
i2c_addr_i => i2c_addr,
i2c_done_o => i2c_done,
i2c_err_o => i2c_err,
-- Wishbone master signals
wbm_stb_o => xbar_slave_in(0).stb,
wbm_cyc_o => xbar_slave_in(0).cyc,
wbm_sel_o => xbar_slave_in(0).sel,
wbm_we_o => xbar_slave_in(0).we,
wbm_dat_i => xbar_slave_out(0).dat,
wbm_dat_o => xbar_slave_in(0).dat,
wbm_adr_o => xbar_slave_in(0).adr,
wbm_ack_i => xbar_slave_out(0).ack,
wbm_rty_i => xbar_slave_out(0).rty,
wbm_err_i => xbar_slave_out(0).err
);
-- Process to blink the LED for a finite amount of time when the i2c_done
-- signal is set.
p_i2c_blink : process(clk125)
begin
if rising_edge(clk125) then
if (rst_n = '0') then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= (others => '0');
led_i2c <= '0';
blink_state <= '0';
else
case blink_state is
when '0' =>
led_i2c <= '0';
if (i2c_done = '1') then
blink_state <= '1';
end if;
when '1' =>
led_i2c_clkdiv <= led_i2c_clkdiv + 1;
if (led_i2c_clkdiv = 2499999) then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= led_i2c_cnt + 1;
led_i2c <= not led_i2c;
if (led_i2c_cnt = 7) then
led_i2c_cnt <= (others => '0');
blink_state <= '0';
end if;
end if;
when others =>
blink_state <= '0';
end case;
end if;
end if;
end process p_i2c_blink;
-- Process to set the I2C error LED signal for display on the front panel
-- of the front module. The I2C error signal is permanently set once an
-- error is detected from the bridge module.
p_i2c_err_led : process (clk125) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
i2c_err_led <= '0';
elsif (i2c_err = '1') then
i2c_err_led <= '1';
end if;
end if;
end process p_i2c_err_led;
--============================================================================
-- Instantiation and connection of the main Wishbone crossbar
--============================================================================
xbar_master_in(0).int <= '0';
xbar_master_in(0).err <= '0';
cmp_wb_crossbar : xwb_crossbar
generic map
(
g_num_masters => c_nr_masters,
g_num_slaves => c_nr_slaves,
g_registered => false,
g_address => c_addresses,
g_mask => c_masks
)
port map
(
clk_sys_i => clk125,
rst_n_i => rst_n,
slave_i => xbar_slave_in,
slave_o => xbar_slave_out,
master_i => xbar_master_in,
master_o => xbar_master_out
);
--============================================================================
-- Instantiate single-port RAM
--============================================================================
cmp_memory: generic_spram
generic map (
g_data_width => 32,
g_size => 2**12
)
port map (
rst_n_i => rst_n,
clk_i => clk125,
bwe_i => (others => '0'),
we_i => ram_we,
a_i => xbar_master_out(c_slv_mem).adr(11 downto 0),
d_i => xbar_master_out(c_slv_mem).dat,
q_o => xbar_master_in(c_slv_mem).dat
);
ram_we <= xbar_master_out(c_slv_mem).we and xbar_master_out(c_slv_mem).stb and
xbar_master_out(c_slv_mem).cyc;
xbar_master_in(c_slv_mem).ack <= ram_ack;
xbar_master_in(c_slv_mem).err <= '0';
p_ram_ack : process (clk125) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
ram_ack <= '0';
else
ram_ack <= '0';
if (xbar_master_out(c_slv_mem).stb = '1') and
(xbar_master_out(c_slv_mem).cyc = '1') then
ram_ack <= '1';
end if;
end if;
end if;
end process p_ram_ack;
--============================================================================
-- Pulse generation control registers instantiation
--============================================================================
cmp_pulse_gen_ctrl_regs : pgen_ctrl_regs
port map
(
rst_n_i => rst_n,
clk_sys_i => clk125,
wb_adr_i => xbar_master_out(c_slv_pgen_ctrl).adr(6 downto 2),
wb_dat_i => xbar_master_out(c_slv_pgen_ctrl).dat,
wb_dat_o => xbar_master_in(c_slv_pgen_ctrl).dat,
wb_cyc_i => xbar_master_out(c_slv_pgen_ctrl).cyc,
wb_sel_i => xbar_master_out(c_slv_pgen_ctrl).sel,
wb_stb_i => xbar_master_out(c_slv_pgen_ctrl).stb,
wb_we_i => xbar_master_out(c_slv_pgen_ctrl).we,
wb_ack_o => xbar_master_in(c_slv_pgen_ctrl).ack,
wb_stall_o => xbar_master_in(c_slv_pgen_ctrl).stall,
pgen_ctrl_regs_en_ch_o => ch_en,
pgen_ctrl_regs_ch1_delay_bits_o => delay_reg(1),
pgen_ctrl_regs_ch2_delay_bits_o => delay_reg(2),
pgen_ctrl_regs_ch3_delay_bits_o => delay_reg(3),
pgen_ctrl_regs_ch4_delay_bits_o => delay_reg(4),
pgen_ctrl_regs_ch5_delay_bits_o => delay_reg(5),
pgen_ctrl_regs_ch6_delay_bits_o => delay_reg(6),
pgen_ctrl_regs_ch1_pwidth_bits_o => pwidth_reg(1),
pgen_ctrl_regs_ch2_pwidth_bits_o => pwidth_reg(2),
pgen_ctrl_regs_ch3_pwidth_bits_o => pwidth_reg(3),
pgen_ctrl_regs_ch4_pwidth_bits_o => pwidth_reg(4),
pgen_ctrl_regs_ch5_pwidth_bits_o => pwidth_reg(5),
pgen_ctrl_regs_ch6_pwidth_bits_o => pwidth_reg(6),
pgen_ctrl_regs_ch1_freq_bits_o => freq_reg(1),
pgen_ctrl_regs_ch2_freq_bits_o => freq_reg(2),
pgen_ctrl_regs_ch3_freq_bits_o => freq_reg(3),
pgen_ctrl_regs_ch4_freq_bits_o => freq_reg(4),
pgen_ctrl_regs_ch5_freq_bits_o => freq_reg(5),
pgen_ctrl_regs_ch6_freq_bits_o => freq_reg(6)
);
--============================================================================
-- Output enable logic
--============================================================================
-- The general output enable is set first and the blocking, TTL
-- and INV output enable signals are set one clock cycle later.
p_oe : process(clk125)
begin
if rising_edge(clk125) then
if (rst_n = '0') then
oe <= '0';
blo_oe <= '0';
ttl_oe <= '0';
inv_oe <= '0';
else
oe <= '1';
if (oe = '1') then
blo_oe <= '1';
ttl_oe <= '1';
inv_oe <= '1';
end if;
end if;
end if;
end process p_oe;
fpga_oe_o <= oe;
fpga_blo_oe_o <= '0';
fpga_trig_ttl_oe_o <= ttl_oe;
fpga_inv_oe_o <= inv_oe;
--============================================================================
-- Pulse generation logic
--============================================================================
-- First, the TTL trigger mux, selected via the TTL switch; ttlbar_nosig_n is
-- controlled in the process below
trig_ttl_a <= not fpga_input_ttl_n_i when (ttl_switch_n_i = '0') else
fpga_input_ttl_n_i;
-- Then, the blocking trigger
trig_blo_a <= fpga_blo_in_i;
-- And now the OR gate at the inputs of the pulse generator blocks
trig_a <= trig_ttl_a or trig_blo_a;
-- Generate logic for each channel
gen_chan_logic : for i in 1 to g_nr_ttl_chan generate
-- First, resync the trigger signal into clk125 domain
cmp_sync_ffs: gc_sync_ffs
port map
(
clk_i => clk125,
rst_n_i => rst_n,
data_i => trig_a(i),
synced_o => trig_synced(i),
ppulse_o => trig_synced_edge(i)
);
-- Instantiate output pulse generators
cmp_pulse_gen : pulse_gen_gp
port map
(
clk_i => clk125,
rst_n_i => rst_n,
en_i => ch_en(i),
delay_i => delay_reg(i),
pwidth_i => pwidth_reg(i),
freq_i => freq_reg(i),
pulse_o => pulse(i)
);
-- Delay reg for output pulses
p_delay_pulse : process (clk125) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
pulse_d0(i) <= '0';
else
pulse_d0(i) <= pulse(i);
end if;
end if;
end process p_delay_pulse;
-- Pulse counting logic
p_cnt_pulses : process(clk125) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
cnt_in(i) <= (others => '0');
cnt_out(i) <= (others => '0');
else
if (pulse(i) = '1') and (pulse_d0(i) = '0') then
cnt_out(i) <= cnt_out(i) + 1;
end if;
if (trig_synced_edge(i) = '1') then
cnt_in(i) <= cnt_in(i) + 1;
end if;
end if;
end if;
end process p_cnt_pulses;
-- Finally, a process to flash pulse LED on pulse transmission
p_pulse_led : process (clk125, rst_n) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
pulse_led_cnt(i) <= (others => '0');
pulse_leds(i) <= '0';
else
case pulse_leds(i) is
when '0' =>
if (pulse(i) = '1') and (pulse_d0(i) = '0') then
pulse_leds(i) <= '1';
end if;
when '1' =>
pulse_led_cnt(i) <= pulse_led_cnt(i) + 1;
if (pulse_led_cnt(i) = (pulse_led_cnt(i)'range => '1')) then
pulse_leds(i) <= '0';
end if;
when others =>
pulse_leds(i) <= '0';
end case;
end if;
end if;
end process p_pulse_led;
end generate gen_chan_logic;
-- Pulse outputs assignment
fpga_out_ttl_o <= pulse when (ttl_switch_n_i = '0') else
not pulse;
fpga_trig_blo_o <= (others => '0');
-- Pulse status LED output assignments
pulse_front_led_n_o <= (not pulse_leds) when (ttl_oe = '1') else
(others => '1');
pulse_rear_led_n_o <= (others => '1');
--============================================================================
-- Pulse counter registers instantiation
--============================================================================
cmp_pulse_cnt_regs : pulse_cnt_regs
port map
(
rst_n_i => rst_n,
clk_sys_i => clk125,
wb_adr_i => xbar_master_out(c_slv_pulse_cnt).adr(5 downto 2),
wb_dat_i => xbar_master_out(c_slv_pulse_cnt).dat,
wb_dat_o => xbar_master_in(c_slv_pulse_cnt).dat,
wb_cyc_i => xbar_master_out(c_slv_pulse_cnt).cyc,
wb_sel_i => xbar_master_out(c_slv_pulse_cnt).sel,
wb_stb_i => xbar_master_out(c_slv_pulse_cnt).stb,
wb_we_i => xbar_master_out(c_slv_pulse_cnt).we,
wb_ack_o => xbar_master_in(c_slv_pulse_cnt).ack,
wb_stall_o => xbar_master_in(c_slv_pulse_cnt).stall,
pulse_cnt_ch1i_val_i => std_logic_vector(cnt_in(1)),
pulse_cnt_ch1o_val_i => std_logic_vector(cnt_out(1)),
pulse_cnt_ch2i_val_i => std_logic_vector(cnt_in(2)),
pulse_cnt_ch2o_val_i => std_logic_vector(cnt_out(2)),
pulse_cnt_ch3i_val_i => std_logic_vector(cnt_in(3)),
pulse_cnt_ch3o_val_i => std_logic_vector(cnt_out(3)),
pulse_cnt_ch4i_val_i => std_logic_vector(cnt_in(4)),
pulse_cnt_ch4o_val_i => std_logic_vector(cnt_out(4)),
pulse_cnt_ch5i_val_i => std_logic_vector(cnt_in(5)),
pulse_cnt_ch5o_val_i => std_logic_vector(cnt_out(5)),
pulse_cnt_ch6i_val_i => std_logic_vector(cnt_in(6)),
pulse_cnt_ch6o_val_i => std_logic_vector(cnt_out(6))
);
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
-- Bicolor LED controls, corresponding to the column orders on the
-- bicolor_led_ctrl unit.
-- WR address
bicolor_led_state( 1 downto 0) <= c_LED_OFF;
-- WR GMT
bicolor_led_state( 3 downto 2) <= c_LED_OFF;
-- WR link
bicolor_led_state( 5 downto 4) <= c_LED_OFF;
-- WR OK
bicolor_led_state( 7 downto 6) <= c_LED_OFF;
-- MULTICAST 0
bicolor_led_state( 9 downto 8) <= c_LED_OFF;
-- MULTICAST 1
bicolor_led_state(11 downto 10) <= c_LED_OFF;
-- I2C
bicolor_led_state(13 downto 12) <= c_LED_GREEN when (led_i2c = '1') else
c_LED_RED when (i2c_err_led = '1') else
c_LED_OFF;
-- State of TTL/TTL_N switch
bicolor_led_state(15 downto 14) <= c_LED_OFF;
-- System error
bicolor_led_state(17 downto 16) <= c_LED_OFF;
-- System power
bicolor_led_state(19 downto 18) <= c_LED_GREEN;
-- MULTICAST 2
bicolor_led_state(21 downto 20) <= c_LED_OFF;
-- MULTICAST 3
bicolor_led_state(23 downto 22) <= c_LED_OFF;
cmp_bicolor_led_ctrl : bicolor_led_ctrl
generic map
(
g_NB_COLUMN => 6,
g_NB_LINE => 2,
g_clk_freq => 125000000,
g_refresh_rate => 250
)
port map
(
clk_i => clk125,
rst_n_i => rst_n,
led_intensity_i => "1111111",
led_state_i => bicolor_led_state,
column_o(0) => led_wr_ownaddr_i2c_o,
column_o(1) => led_wr_gmt_ttl_ttln_o,
column_o(2) => led_wr_link_syserror_o,
column_o(3) => led_wr_ok_syspw_o,
column_o(4) => led_multicast_2_0_o,
column_o(5) => led_multicast_3_1_o,
line_o(0) => led_ctrl0_o,
line_o(1) => led_ctrl1_o,
line_oen_o(0) => led_ctrl0_oen_o,
line_oen_o(1) => led_ctrl1_oen_o
);
end behav;
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