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C
Conv TTL Blocking - Gateware
Commit effeaabc authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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work on multiboot

parent 201bc482
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Showing with 594 additions and 75 deletions
hdl/multiboot/rtl/multiboot_fsm.vhd
View file @ effeaabc
This diff is collapsed.
hdl/multiboot/rtl/multiboot_regs.vhd
View file @ effeaabc
......@@ -109,6 +109,10 @@ begin
ack_sreg(0) <= ack_sreg(1);
ack_sreg(1) <= '0';
if (ack_in_progress = '1') then
multiboot_cr_rdbootsts_int <= '0';
multiboot_cr_wmb_int <= '0';
multiboot_cr_wgb_int <= '0';
multiboot_cr_iprog_int <= '0';
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
......
hdl/multiboot/sim/run.do
View file @ effeaabc
......@@ -15,4 +15,4 @@ log -r /*
# add wave *
do wave.do
run 4 us
run 5 us
hdl/multiboot/sim/testbench.vhd
View file @ effeaabc
......@@ -129,15 +129,6 @@ architecture behav of testbench is
signal adr : std_logic_vector(31 downto 0);
signal dat : std_logic_vector(31 downto 0);
signal rdbootsts : std_logic;
signal wmb, wgb : std_logic;
signal iprog : std_logic;
signal bootsts_img : std_logic_vector(15 downto 0);
signal valid : std_logic;
signal mbbar, gbbar : std_logic_vector(31 downto 0);
signal str : string(1 to 8);
--==============================================================================
......@@ -198,9 +189,9 @@ begin
wait for 1500ns;
-- Write to CR
-- Send IPROG
wait for 200 ns;
str <= "wr-cr ";
str <= "wr-iprog";
adr <= x"00000000";
dat <= x"00000008";
write <= '1';
......@@ -208,6 +199,25 @@ begin
wait for c_clk_per;
transfer <= '0';
-- Send RDBOOTSTS
wait for 200 ns;
str <= "wr-bsts ";
adr <= x"00000000";
dat <= x"00000001";
write <= '1';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
-- Read from SR
wait for 500 ns;
str <= "rd-sr ";
adr <= x"00000004";
write <= '0';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
---- Read from CR
--wait for 30 ns;
--str <= "rd-cr ";
......
hdl/multiboot/sim/transcript
View file @ effeaabc
This diff is collapsed.
hdl/multiboot/sim/wave.do
View file @ effeaabc
......@@ -15,14 +15,6 @@ add wave -noupdate /testbench/transfer
add wave -noupdate /testbench/write
add wave -noupdate -radix hexadecimal /testbench/adr
add wave -noupdate -radix hexadecimal /testbench/dat
add wave -noupdate /testbench/rdbootsts
add wave -noupdate /testbench/wmb
add wave -noupdate /testbench/wgb
add wave -noupdate /testbench/iprog
add wave -noupdate -radix hexadecimal /testbench/bootsts_img
add wave -noupdate -radix hexadecimal /testbench/valid
add wave -noupdate -radix hexadecimal /testbench/mbbar
add wave -noupdate -radix hexadecimal /testbench/gbbar
add wave -noupdate /testbench/str
add wave -noupdate -divider FSM
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/gbbar_i
......@@ -39,8 +31,11 @@ add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_icap/I
add wave -noupdate /testbench/UUT/cmp_icap/prog_b
add wave -noupdate /testbench/UUT/cmp_icap/init_b
add wave -noupdate /testbench/UUT/cmp_icap/done_o
add wave -noupdate /testbench/UUT/cmp_fsm/fsm_cmd
add wave -noupdate /testbench/UUT/cmp_fsm/fsm_cmd_reg
add wave -noupdate /testbench/UUT/cmp_icap/BUSY
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2075 ns} 0}
WaveRestoreCursors {{Cursor 1} {1918 ns} 0}
configure wave -namecolwidth 276
configure wave -valuecolwidth 99
configure wave -justifyvalue left
......@@ -55,4 +50,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ns} {7720 ns}
WaveRestoreZoom {0 ns} {5250 ns}
hdl/multiboot/syn/conv_ttl_blo.gise
View file @ effeaabc
......@@ -72,35 +72,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1376993298" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1376993298">
<transform xil_pn:end_ts="1377019849" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1377019849">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376993298" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1376993298">
<transform xil_pn:end_ts="1377019849" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1377019849">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376993298" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1376993298">
<transform xil_pn:end_ts="1377019849" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1377019849">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376993298" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1376993298">
<transform xil_pn:end_ts="1377019849" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1377019849">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376993298" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1376993298">
<transform xil_pn:end_ts="1377019849" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1377019849">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376993298" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1376993298">
<transform xil_pn:end_ts="1377019849" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1377019849">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376993298" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1376993298">
<transform xil_pn:end_ts="1377019849" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1377019849">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376993313" xil_pn:in_ck="6680273903363502638" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1376993298">
<transform xil_pn:end_ts="1377019866" xil_pn:in_ck="6680273903363502638" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1377019849">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -118,11 +118,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1376993313" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1376993313">
<transform xil_pn:end_ts="1377019866" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1377019866">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1376993324" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1376993313">
<transform xil_pn:end_ts="1377019874" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1377019866">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -131,7 +131,7 @@
<outfile xil_pn:name="conv_ttl_blo.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1376993375" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1376993324">
<transform xil_pn:end_ts="1377019923" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1377019874">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -144,7 +144,7 @@
<outfile xil_pn:name="conv_ttl_blo_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1376993430" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1376993375">
<transform xil_pn:end_ts="1377019976" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1377019923">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -158,7 +158,7 @@
<outfile xil_pn:name="conv_ttl_blo_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1376993465" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1376993430">
<transform xil_pn:end_ts="1377020011" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1377019976">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
......@@ -169,7 +169,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1376993430" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1376993419">
<transform xil_pn:end_ts="1377019976" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1377019965">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/multiboot/top/conv_ttl_blo.vhd
View file @ effeaabc
......@@ -124,7 +124,7 @@ architecture behav of conv_ttl_blo is
-- Constant declarations
--============================================================================
-- Firmware version
constant c_fwvers : std_logic_vector(15 downto 0) := x"0200";
constant c_fwvers : std_logic_vector(15 downto 0) := x"0201";
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
......
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