Skip to content

C
Conv TTL Blocking - Gateware
Commit e8cf3df3 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
Browse files
Options

Working on hwguide

parent ecc561f0
Hide whitespace changes
Inline Side-by-side
Showing with 3288 additions and 323 deletions
doc/hwguide/fig/blo-inp.svg 0 → 100644
View file @ e8cf3df3
This source diff could not be displayed because it is too large. You can view the blob instead.
doc/hwguide/fig/conv-ttl-blo-bd.svg 0 → 100644
View file @ e8cf3df3
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!-- Created with Inkscape (http://www.inkscape.org/) -->
<svg
xmlns:dc="http://purl.org/dc/elements/1.1/"
xmlns:cc="http://creativecommons.org/ns#"
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
width="206.51183"
height="165.23076"
id="svg2"
version="1.1"
inkscape:version="0.48.3.1 r9886"
sodipodi:docname="conv-ttl-blo-bd.pdf">
<defs
id="defs4">
<marker
inkscape:stockid="TriangleOutM"
orient="auto"
refY="0"
refX="0"
id="TriangleOutM"
style="overflow:visible">
<path
id="path4047"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(0.4,0.4)"
inkscape:connector-curvature="0" />
</marker>
<marker
inkscape:stockid="TriangleInM"
orient="auto"
refY="0"
refX="0"
id="TriangleInM"
style="overflow:visible">
<path
id="path4038"
d="m 5.77,0 -8.65,5 0,-10 8.65,5 z"
style="fill-rule:evenodd;stroke:#000000;stroke-width:1pt"
transform="scale(-0.4,-0.4)"
inkscape:connector-curvature="0" />
</marker>
</defs>
<sodipodi:namedview
id="base"
pagecolor="#ffffff"
bordercolor="#666666"
borderopacity="1.0"
inkscape:pageopacity="0.0"
inkscape:pageshadow="2"
inkscape:zoom="2.8"
inkscape:cx="98.170304"
inkscape:cy="48.083202"
inkscape:document-units="px"
inkscape:current-layer="layer1"
showgrid="true"
inkscape:window-width="1855"
inkscape:window-height="1176"
inkscape:window-x="65"
inkscape:window-y="24"
inkscape:window-maximized="1"
inkscape:snap-bbox="false"
inkscape:snap-bbox-midpoints="false"
inkscape:snap-smooth-nodes="false"
inkscape:object-nodes="true"
fit-margin-top="0"
fit-margin-left="0"
fit-margin-right="0"
fit-margin-bottom="0"
showguides="true"
inkscape:guide-bbox="true" />
<metadata
id="metadata7">
<rdf:RDF>
<cc:Work
rdf:about="">
<dc:format>image/svg+xml</dc:format>
<dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
<dc:title></dc:title>
</cc:Work>
</rdf:RDF>
</metadata>
<g
inkscape:label="Layer 1"
inkscape:groupmode="layer"
id="layer1"
transform="translate(-243.98819,-139.99363)">
<rect
style="fill:#d9d9d9;fill-opacity:1;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:round;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="rect2989"
width="53.149609"
height="53.149605"
x="318.89764"
y="184.25195" />
<rect
style="fill:#d9d9d9;fill-opacity:1;stroke:#000000;stroke-width:1;stroke-linejoin:round;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="rect3823"
width="53.149609"
height="31.889763"
x="311.811"
y="272.83463" />
<rect
y="272.83463"
x="248.03149"
height="31.889763"
width="53.149609"
id="rect3833"
style="fill:#d9d9d9;fill-opacity:1;stroke:#000000;stroke-width:1;stroke-linejoin:round;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<rect
y="279.92123"
x="375.59055"
height="17.716534"
width="31.889759"
id="rect3851"
style="fill:#d9d9d9;fill-opacity:1;stroke:#000000;stroke-width:1;stroke-linejoin:round;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<rect
style="fill:#d9d9d9;fill-opacity:1;stroke:#000000;stroke-width:1;stroke-linejoin:round;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="rect3861"
width="31.889759"
height="17.716534"
x="418.11023"
y="279.92123" />
<rect
y="155.76178"
x="244.48819"
height="10.62992"
width="205.51181"
id="rect3890"
style="fill:#d9d9d9;fill-opacity:1;stroke:#000000;stroke-width:1;stroke-linejoin:round;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<text
xml:space="preserve"
style="font-size:23.95430756px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="341.85156"
y="217.09576"
id="text3759"
sodipodi:linespacing="125%"
transform="scale(1.0093636,0.99072327)"><tspan
sodipodi:role="line"
id="tspan3761"
x="341.85156"
y="217.09576"
style="font-size:12px;font-weight:bold;text-align:center;text-anchor:middle">FPGA</tspan></text>
<g
id="g3903"
transform="translate(0,3.4169006)">
<rect
y="180.33505"
x="246.70586"
height="24.484011"
width="53.149609"
id="rect3901"
style="fill:#d9d9d9;fill-opacity:1;stroke:#000000;stroke-width:1;stroke-linejoin:round;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<text
xml:space="preserve"
style="font-size:11px;font-style:normal;font-weight:normal;line-height:100%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="273.25381"
y="190.04849"
id="text3768"
sodipodi:linespacing="100%"><tspan
sodipodi:role="line"
id="tspan3770"
x="273.25381"
y="190.04849"
style="text-align:center;line-height:100%;text-anchor:middle">Power</tspan><tspan
sodipodi:role="line"
x="273.25381"
y="201.04849"
id="tspan3772"
style="text-align:center;line-height:100%;text-anchor:middle">supplies</tspan></text>
</g>
<g
transform="matrix(0.60446516,0,0,0.59330226,107.57679,199.8999)"
id="g3807" />
<text
xml:space="preserve"
style="font-size:11px;font-style:normal;font-weight:normal;line-height:100%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="338.4288"
y="286.1235"
id="text3817"
sodipodi:linespacing="100%"><tspan
sodipodi:role="line"
x="338.4288"
y="286.1235"
id="tspan3821"
style="text-align:center;line-height:100%;text-anchor:middle">TTL</tspan><tspan
sodipodi:role="line"
x="338.4288"
y="297.1235"
style="text-align:center;line-height:100%;text-anchor:middle"
id="tspan3837">interface</tspan></text>
<text
sodipodi:linespacing="100%"
id="text3827"
y="286.1235"
x="274.64926"
style="font-size:11px;font-style:normal;font-weight:normal;line-height:100%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="text-align:center;line-height:100%;text-anchor:middle"
id="tspan3831"
y="286.1235"
x="274.64926"
sodipodi:role="line">Blocking</tspan><tspan
style="text-align:center;line-height:100%;text-anchor:middle"
y="297.1235"
x="274.64926"
sodipodi:role="line"
id="tspan3841">interface</tspan></text>
<text
sodipodi:linespacing="100%"
id="text3845"
y="293.21008"
x="391.5784"
style="font-size:11px;font-style:normal;font-weight:normal;line-height:100%;letter-spacing:0px;word-spacing:0px;fill:#000037;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
id="tspan3849"
style="text-align:center;line-height:100%;text-anchor:middle;fill:#000037;fill-opacity:1"
y="293.21008"
x="391.5784"
sodipodi:role="line">SFP</tspan></text>
<text
xml:space="preserve"
style="font-size:11px;font-style:normal;font-weight:normal;line-height:100%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="434.09811"
y="293.21008"
id="text3857"
sodipodi:linespacing="100%"><tspan
sodipodi:role="line"
x="434.09811"
y="293.21008"
style="text-align:center;line-height:100%;text-anchor:middle"
id="tspan3859">LEDs</tspan></text>
<text
sodipodi:linespacing="125%"
id="text3892"
y="164.9493"
x="354.33072"
style="font-size:11px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="text-align:center;text-anchor:middle"
y="164.9493"
x="354.33072"
id="tspan3894"
sodipodi:role="line">VME connector</tspan></text>
<path
inkscape:connector-curvature="0"
id="path4894"
d="m 343.70079,180.70864 0,-35.43307"
style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:2.99999999, 2.99999999;stroke-dashoffset:0;marker-start:url(#TriangleInM);marker-end:url(#TriangleOutM)" />
<text
sodipodi:linespacing="125%"
id="text5266"
y="148.81888"
x="322.44095"
style="font-size:11px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:10px;font-style:italic"
y="148.81888"
x="322.44095"
id="tspan5268"
sodipodi:role="line">I<tspan
id="tspan5270"
style="font-size:6.50139284px;baseline-shift:super">2</tspan>C</tspan></text>
<path
inkscape:connector-curvature="0"
id="path5832"
d="m 336.61417,240.94486 0,10.62992 0,17.71654"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:url(#TriangleInM);marker-end:url(#TriangleOutM)" />
<path
inkscape:connector-curvature="0"
id="path5834"
d="m 347.24409,240.94486 0,14.17323 42.51969,0 0,21.25984"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:url(#TriangleInM);marker-end:url(#TriangleOutM)" />
<path
inkscape:connector-curvature="0"
id="path5836"
d="m 357.87402,240.94486 0,7.08661 74.40944,0 0,28.34646"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:url(#TriangleInM);marker-end:url(#TriangleOutM)" />
<path
inkscape:connector-curvature="0"
id="path5838"
d="m 325.98425,240.94486 0,7.08661 -49.6063,0 0,21.25985"
style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;marker-start:url(#TriangleInM);marker-end:url(#TriangleOutM)" />
<g
id="g3955"
transform="translate(-1.4285642,2.0326138)">
<rect
y="214.6091"
x="398.27896"
height="21.259844"
width="53.149609"
id="rect3795"
style="fill:#d9d9d9;fill-opacity:1;stroke:#000000;stroke-width:1;stroke-linejoin:round;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<text
sodipodi:linespacing="100%"
id="text3789"
y="229.17871"
x="424.89673"
style="font-size:11px;font-style:normal;font-weight:normal;line-height:100%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="text-align:center;line-height:100%;text-anchor:middle"
id="tspan3793"
y="229.17871"
x="424.89673"
sodipodi:role="line">Flash</tspan></text>
<path
inkscape:connector-curvature="0"
id="path7312"
d="m 377.01912,225.23901 17.71654,0"
style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-start:url(#TriangleInM);marker-end:url(#TriangleOutM)" />
</g>
<g
id="g3949"
transform="translate(0,-2.032608)">
<rect
style="fill:#d9d9d9;fill-opacity:1;stroke:#000000;stroke-width:1;stroke-linejoin:round;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none"
id="rect3805"
width="53.149609"
height="21.259844"
x="396.8504"
y="185.78456" />
<text
xml:space="preserve"
style="font-size:11px;font-style:normal;font-weight:normal;line-height:100%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="423.46817"
y="200.35417"
id="text3801"
sodipodi:linespacing="100%"><tspan
sodipodi:role="line"
x="423.46817"
y="200.35417"
id="tspan3803"
style="text-align:center;line-height:100%;text-anchor:middle">Clocks</tspan></text>
<path
style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-start:url(#TriangleInM);marker-end:url(#TriangleOutM)"
d="m 375.59055,196.41449 17.71654,0"
id="path7314"
inkscape:connector-curvature="0" />
</g>
<rect
y="216.64171"
x="246.70586"
height="21.259844"
width="53.149609"
id="rect3824"
style="fill:#d9d9d9;fill-opacity:1;stroke:#000000;stroke-width:1;stroke-linejoin:round;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none" />
<text
sodipodi:linespacing="100%"
id="text3826"
y="231.21135"
x="273.32361"
style="font-size:11px;font-style:normal;font-weight:normal;line-height:100%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="text-align:center;line-height:100%;text-anchor:middle"
id="tspan3828"
y="231.21135"
x="273.32361"
sodipodi:role="line">Thermo</tspan></text>
<path
style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;marker-start:url(#TriangleInM);marker-end:url(#TriangleOutM)"
d="m 303.44769,226.77163 11.46654,0"
id="path3909"
inkscape:connector-curvature="0"
sodipodi:nodetypes="cc" />
</g>
</svg>
doc/hwguide/hwguide-conv-ttl-blo.bib
View file @ e8cf3df3
@misc{onewire,
author = {Iztok Jeras},
title = {{sockit\_owm, 1-wire (onewire) master}},
year = 2011,
note = {\url{http://opencores.org/websvn,filedetails?repname=sockit_owm&path=%2Fsockit_owm%2Ftrunk%2Fdoc%2Fsockit_owr.pdf}}
}
@misc{spi,
author = {Simon Srot},
title = {{SPI Master Core Specification}},
year = 2004,
note = {\url{http://opencores.org/websvn,filedetails?repname=spi&path=%2Fspi%2Ftrunk%2Fdoc%2Fspi.pdf}}
}
@misc{i2c-master,
author = {Richard Herveille},
title = {{I$2$C Master Core Specification}},
year = 2003,
note = {\url{http://opencores.org/websvn,filedetails?repname=i2c&path=%2Fi2c%2Ftrunk%2Fdoc%2Fi2c_specs.pdf}}
}
@misc{coding-guidelines,
author = "Patrick Loschmidt and Nata{\v s}a Simani\'c and C\'esar Prados and Pablo Alvarez and Javier Serrano",
title = {{Guidelines for VHDL Coding}},
month = 04,
year = 2011,
note = {\url{http://www.ohwr.org/documents/24}}
}
@misc{ctb-ug,
author = "Theodor-Adrian Stana",
title = {{CONV-TTL-BLO User Guide}},
......@@ -46,3 +17,14 @@
title = {{White Rabbit}},
howpublished = {\url{http://www.ohwr.org/projects/white-rabbit}}
}
@misc{conv-ttl-blo-sch,
title = {{CONV-TTL-BLO Schematics}},
howpublished = {\url{https://edms.cern.ch/file/1278535/1/EDA-02446-V2-1_sch.pdf}}
}
@misc{blo-ps-datasheet,
author = {{Texas Instruments}},
title = {{TPS40210, TPS40211, 4.5~V to 52~V Input Current Mode Boost Controller}},
howpublished = {\url{http://www.ohwr.org/documents/227}}
}
\ No newline at end of file
doc/hwguide/hwguide-conv-ttl-blo.tex
View file @ e8cf3df3
......@@ -60,6 +60,8 @@
\section*{List of Abbreviations}
\begin{tabular}{l l}
RTM & Rear-Transition Module \\
IC & Integrated Circuit \\
PLL & Phase-Locked Loop \\
SFP & Small-Form-factor Pluggable (transceiver) \\
\end{tabular}
......@@ -117,12 +119,16 @@ connections to input blocking pulses to the CONV-TTL-BLO.
\section{Front module}
\label{sec:ctb}
A block diagram of the CONV-TTL-BLO board is shown in Figure!!!.
A block diagram of the CONV-TTL-BLO board is shown in Figure~\ref{fig:conv-ttl-blo-bd}.
The board contains all active circuitry needed within a converter system. The various
blocks in Figure~\ref{fig:conv-ttl-blo-bd} are presented in subsections that follow.
\begin{figure}
\centerline{\includegraphics[width=.75\textwidth]{fig/}}
The schematics of the CONV-TTL-BLO board can be found at \cite{conv-ttl-blo-sch}.
\begin{figure}[h]
\centerline{\includegraphics[width=.75\textwidth]{fig/conv-ttl-blo-bd}}
\caption{Block diagram of CONV-TTL-BLO board}
\label{fig:}
\label{fig:conv-ttl-blo-bd}
\end{figure}
%------------------------------------------------------------------------------
......@@ -131,15 +137,46 @@ A block diagram of the CONV-TTL-BLO board is shown in Figure!!!.
\subsection{Power supplies}
\label{sec:ctb-power}
\textcolor{red}{\textbf{FPGA PS from VME}}
\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: pages 2, 3 \\
\hline
\end{tabular}
\vspace*{11pt}
\textcolor{red}{\textbf{FPGA logic from VME, voltage regulator}}
Various power levels are needed on the CONV-TTL-BLO board. They are listed in
Table~\ref{tbl:voltage-levels}. All power supplies on the board are derived
in some way from the 3.3~V, 5~V and 12~V VME power supplies.
\begin{table}
\caption{Voltage levels on CONV-TTL-BLO}
\label{tbl:voltage-levels}
\centerline{
\begin{tabular}{l p{.5\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Level}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
1.2~V & Low-voltage power supply for the FPGA logic \\
3.3~V & V$_{CC}$ for most of the devices on the board \\
5~V & Power supply for some circuits on-board (blocking input optocouplers, blocking
output buffers, etc.) \\
24~V & Blocking-level power supply \\
\hline
\end{tabular}
}
\end{table}
\textcolor{red}{\textbf{FPGA logic from VME, voltage adapted}}
First, the 5~V and 3.3~V VME supplies arriving on the VME connectors are filtered using
two PI filters (schematic page 2). These filters assure noise immunity in the 50~MHz to
150~MHz band. The filtered power supplies are used throughout the logic.
\textcolor{red}{\textbf{PS filtering}}
The 1.2~V logic power supply is generated by a Texas Instruments TPS54312PWP Buck converter.
This circuit can be found in page 2 of the schematics.
\textcolor{red}{\textbf{Blocking PS}}
Finally, the 24~V blocking power supply (schematics page 3) uses a Texas Instruments
TPS40210DGQR. It was calculated using the first design example in the device's
datasheet~\cite{blo-ps-datasheet}.
%------------------------------------------------------------------------------
% SUBSEC: Clocks
......@@ -147,7 +184,75 @@ A block diagram of the CONV-TTL-BLO board is shown in Figure!!!.
\subsection{Clock circuits}
\label{sec:clocks}
\textcolor{red}{\textbf{Describe clock circuits}}
\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 5 \\
\hline
\end{tabular}
\vspace*{11pt}
There are multiple clock signals on the CONV-TTL-BLO (Table~\ref{tbl:clocks}).
A 20~MHz clock for the FPGA is generated directly from a tunable VCXO (OSC3). The
second FPGA clock is a 125~MHz signal generated from a 25~MHz VCXO by means of a Texas
Instruments CDCM61004RHBT PLL IC. Two of the other PLL's output channels are used
to output dedicated 125~MHz dedicated clocks to the SFP and FPGA transceiver.
Both VCXOs can be tuned by means of two Analog Devices AD5662BRMZ-1 DACs (IC17
and IC18). The DACs can be controlled via a 3-wire SPI interface from the FPGA.
\begin{table}
\caption{Clocks on CONV-TTL-BLO}
\label{tbl:clocks}
\centerline
{
\begin{tabular}{l c l}
\hline
\multicolumn{1}{c}{\textbf{Clock}} & \textbf{Frequency} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
CLK20\_VCXO & $ 20 MHz$ & FPGA clock (from VCXO) \\
FPGA\_CLK & $125 MHz$ & FPGA clock (from PLL IC) \\
SFP\_CLK & $125 MHz$ & Dedicated SFP clock \\
FPGA\_MGT\_CLK & $125 MHz$ & Dedicated clock for FPGA transceiver \\
\hline
\end{tabular}
}
\end{table}
The 3.3~V power supply used by ICs on the clock generation part is a cleaner version
of the board-wide 3.3~V supply. The cleaning is done by a four-pole LC filter.
%------------------------------------------------------------------------------
% SUBSEC: TTL pulse rep
%------------------------------------------------------------------------------
\subsection{FPGA}
\label{sec:fpga}
\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 4 \\
\hline
\end{tabular}
\vspace*{11pt}
A Xilinx XC6SLX45T Spartan-6 FPGA is present on the CONV-TTL-BLO board. It is the
core part of the blocking conversion system, since it is the device controlling
all the components on the board.
The intended functionality of the FPGA is:
\begin{itemize}
\item generating output pulses as response to input pulse
\item pulse logging
\item clock conditioning
\item remote reprogramming
\item controlling the various panel LEDs to inform the user either of pulse
arrival, or the status of the system.
\end{itemize}
For more details on the FPGA firmware and functionality, refer to the CONV-TTL-BLO
HDL Guide \textcolor{red}{\textbf{REFER}}.
%------------------------------------------------------------------------------
% SUBSEC: TTL pulse rep
......@@ -155,18 +260,59 @@ A block diagram of the CONV-TTL-BLO board is shown in Figure!!!.
\subsection{TTL pulse repetition}
\label{sec:ttl}
\textcolor{red}{\textbf{Describe TTL pulse rep}}
\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 13 \\
\hline
\end{tabular}
\vspace*{11pt}
TTL and TTL-BAR pulses may arrive on front panels of CONV-TTL-BLO boards. The two
signal types are described in Sections~4.1~and~4.2 of~\cite{ctb-ug}. Signals
arriving on an input channel go through an input stage consisting of Schmitt
trigger circuits; they are then input to the FPGA, where the pulse gets regenerated
and passed to the output stage.
%------------------------------------------------------------------------------
\subsubsection{Input stage}
\textcolor{red}{\textbf{Schmitt trigger isolates FPGA}}
The input stage on a TTL pulse channel is shown in Figure~\ref{fig:ttl-inp}.
Pulses go through a Texas Instruments SN74LVC14AD Schmitt trigger inverter which smooths
the edges of the input signal and helps isolate the FPGA from the channel
input. The inverter is 5~V tolerant at the input, so TTL signals may be up to 5~V
high. Anything above 5.6~V opens the BAS66 diode to the 5~V and protects
the Schmitt trigger.
The input stage is 50~$\Omega$ terminated (the three 150~$\Omega$ resistors). Note that
when no wire is plugged into the LEMO connector, the termination pulls the line low
which becomes a continuous high-level when it comes out of the Schmitt trigger.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/ttl-inp}}
\caption{TTL pulse input stage}
\label{fig:ttl-inp}
\end{figure}
This input stage is repeated on each of the six TTL pulse replication channels of
the CONV-TTL-BLO, as well as the four inverter channels.
%------------------------------------------------------------------------------
\subsubsection{Output stage}
\textcolor{red}{\textbf{details about output buffers}}
The output stage consists of Texas Instruments SN64BCT25244DW tri-state buffers
driven from the FPGA. The purpose of the buffers is two-fold. First, they isolate
the FPGA outputs from the actual channel outputs. Second, they assure the line can
drive a 50~$\Omega$ load.
The buffers' enable signals are controlled by two signals from the FPGA.
These signals are NANDed together (IC10 NAND gate) and connected to the output
enable active-low signals. When the FPGA does not drive the output enable line,
it is pulled high by a pull-up resistor, to safeguard against spurious signals on the
output of the channel.
Pull-down resistors at the output of the tri-state buffers assure a continuous
low level at the output when the buffers are not enabled.
%------------------------------------------------------------------------------
% SUBSEC: Blocking pulse rep
......@@ -174,14 +320,61 @@ A block diagram of the CONV-TTL-BLO board is shown in Figure!!!.
\subsection{Blocking pulse repetition}
\label{sec:blo}
\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: pages 9-12 \\
\hline
\end{tabular}
\vspace*{11pt}
Blocking pulses arrive through the LEMO connectors on the rear panel. Through the
RTM and the P2 connector, they arrive at the blocking input stage on the CONV-TTL-BLO,
where an optocoupler is used to isolate the input signal from the logic levels of
the FPGA. The input pulse then goes into the FPGA, where the pulse is regenerated
in the same manner as TTL pulses. The regenerated pulse signal goes through a flyback
converter output stage, where the logic levels of the FPGA are converted back into
blocking level.
The blocking input stage can be found on pages~9~and~10 of the schematics; the blocking
output stage can be found on pages~11~and~12.
%------------------------------------------------------------------------------
\subsubsection{Input stage}
\textcolor{red}{\textbf{Max. inp. PW computation}}
\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: pages 9, 10 \\
\hline
\end{tabular}
\vspace*{11pt}
The blocking input stage contains the 50~$\Omega$ termination, a transient voltage
suppressor diode to protect against high-voltage spikes, a high-pass RC filter which
prevents DC signals from passing to the Avago optocoupler. Finally, the optocoupler
isolates the blocking-level stage from the logic stage on the FPGA side. Since the
optocoupler is powered from 5~V, a Schmitt trigger (not shown in Figure~\ref{fig:blo-inp})
adapts the 5~V level to the 3.3~V level needed by the FPGA.
The minimum pulse level for this circuit is 3.8~$V$ (see Appendix~\ref{app:blo-min-level}).
The maximum pulse width that can be safely sustained by the input stage is 2~${\mu}s$
(see Appendix~\ref{app:blo-max-width}).
%------------------------------------------------------------------------------
\subsubsection{Output stage}
\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: pages 11, 12 \\
\hline
\end{tabular}
\vspace*{11pt}
\textcolor{red}{\textbf{details about output circuit}}
\textcolor{red}{\textbf{galvanic isolation}}
......@@ -196,15 +389,32 @@ A block diagram of the CONV-TTL-BLO board is shown in Figure!!!.
\subsection{SFP connector}
\label{sec:sfp}
\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 6 \\
\hline
\end{tabular}
\vspace*{11pt}
The small form-factor pluggable (SFP) connector on the CONV-TTL-BLO front panel
can be used to input an optic fiber cable that may be used for pulse tagging
using White Rabbit.
%------------------------------------------------------------------------------
% SEC: Thermo, flash
%------------------------------------------------------------------------------
\subsection{Thermometer and flash chip}
\label{sec:thermo-flash}
\textcolor{red}{\textbf{thermo in figure!!}}
\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 7 \\
\hline
\end{tabular}
\vspace*{11pt}
\textcolor{red}{\textbf{FLASH instead of EEPROM in figure!!}}
%==============================================================================
% SEC: RTM, RTMP
......@@ -223,6 +433,130 @@ A block diagram of the CONV-TTL-BLO board is shown in Figure!!!.
\subsection{RTM Piggyback}
%==============================================================================
% Appendices
%==============================================================================
\pagebreak
\begin{appendices}
%==============================================================================
% APP: Block inp stage calc
%==============================================================================
\section{Blocking input stage calculations}
\label{app:blo-inp}
Figure~\ref{fig:blo-inp} shows the blocking input stage, as a reference for the
calculations below.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/blo-inp}}
\caption{Blocking input stage}
\label{fig:blo-inp}
\end{figure}
%------------------------------------------------------------------------------
% SUBSEC: min pulse level
%------------------------------------------------------------------------------
\subsection{Minimum blocking pulse level}
\label{app:blo-min-level}
The optocoupler LED has a forward voltage of 1.5~V and therefore when the LED is on,
the voltage in point 2 of Figure~\ref{fig:blo-inp} is
\begin{equation}
V_2 = 1.5V
\end{equation}
This means that for the LED to turn on, only
\begin{equation}
V_2 = \frac{R_{152}}{R_{152} + R_{147}}{V_1}
\end{equation}
\begin{equation}
V_1 = \frac{R_{152} + R_{147}}{R_{152}}{V_2}
\end{equation}
\begin{equation}
V_1 = \frac{5k7}{4k7} \times 1.5 = 1.82 V
\end{equation}
\noindent are needed at the blocking input. However, the LED needs to reach a certain
intensity level before it triggers the output of the optocoupler. This translates into
a threshold current for the LED, which is given in the optocoupler datasheet to have a
typical value of
\begin{equation}
I_{TH} = 2mA
\end{equation}
Inputting this into the circuit calculation above, and knowing that when the LED is on
a 0.31~$mA$ current passes through $R_{152}$ (1.5~V / 4k7$\Omega$), this yields a
current of 2.31~$mA$ passing through $R_{147}$ ($I_{LED} + I_{R_{152}}$).
This results in a minimum pulse level of
\begin{equation}
V_1 - V_2 = 2.31mA \times 1k{\Omega}
\end{equation}
\begin{equation}
V_{1,min} = 3.8V
\end{equation}
This value has been verified in practice to be the minimum input pulse level for which
a pulse is generated at the output.
%------------------------------------------------------------------------------
% SUBSEC: max pulse width
%------------------------------------------------------------------------------
\subsection{Maximum blocking pulse width calculation}
\label{app:blo-max-width}
Considering $24V$ pulses at the blocking input (point 1 in Figure~\ref{fig:blo-inp})
and the fact that the forward voltage of the LED when conducting is $1.5V$ ($V_2 = 1.5V$),
this yields a $22.5mA$ current going through $R_{147}$
\begin{equation}
I_{R_{147}} = \frac{24-1.5}{1k} = 22.5mA
\end{equation}
Since this current is divided among $R_{152}$ and the optocoupler LED and the current
through $R_{152}$ is
\begin{equation}
I_{R_{152}} = \frac{V_2}{R_{152}} = \frac{1.5}{4k7} = 0.31mA
\end{equation}
the current through the LED is
\begin{equation}
I_{LED} = I_{R_{147}} - I_{R_{152}} \cong 22.2mA
\end{equation}
Now, by selecting a recommended input RMS current of $15mA$ from the optocoupler's datasheet,
and knowing that the RMS current for the pulse wave is
\begin{equation}
I_{LED,RMS} = I_{LED} \sqrt{\delta}
\end{equation}
this gives a maximum duty cycle of
\begin{equation}
\delta \cong 0.46
\end{equation}
With the $1.2{\mu}s$ pulse width at the output and the minimum $4.8{\mu}s$ pulse period,
this gives a maximum pulse width at the input of
\begin{equation}
t_{p,max} = 2.2 {\mu}s
\end{equation}
\end{appendices}
%==============================================================================
% Bibliography
%==============================================================================
......
doc/userguide/fig/vme64x-prot.svg deleted 100644 → 0
View file @ ecc561f0
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<!-- Created with Inkscape (http://www.inkscape.org/) -->
<svg
xmlns:dc="http://purl.org/dc/elements/1.1/"
xmlns:cc="http://creativecommons.org/ns#"
xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
xmlns:svg="http://www.w3.org/2000/svg"
xmlns="http://www.w3.org/2000/svg"
xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape"
width="497.06299"
height="27.837971"
id="svg2"
version="1.1"
inkscape:version="0.48.3.1 r9886"
sodipodi:docname="vme64x-prot.svg">
<defs
id="defs4" />
<sodipodi:namedview
id="base"
pagecolor="#ffffff"
bordercolor="#666666"
borderopacity="1.0"
inkscape:pageopacity="0.0"
inkscape:pageshadow="2"
inkscape:zoom="1.979899"
inkscape:cx="251.53438"
inkscape:cy="-80.377995"
inkscape:document-units="px"
inkscape:current-layer="layer1"
showgrid="true"
inkscape:window-width="1855"
inkscape:window-height="1176"
inkscape:window-x="65"
inkscape:window-y="24"
inkscape:window-maximized="1"
fit-margin-top="0"
fit-margin-left="0"
fit-margin-right="0"
fit-margin-bottom="0" />
<metadata
id="metadata7">
<rdf:RDF>
<cc:Work
rdf:about="">
<dc:format>image/svg+xml</dc:format>
<dc:type
rdf:resource="http://purl.org/dc/dcmitype/StillImage" />
<dc:title></dc:title>
</cc:Work>
</rdf:RDF>
</metadata>
<g
inkscape:label="Layer 1"
inkscape:groupmode="layer"
id="layer1"
transform="translate(-52.649605,-68.331299)">
<rect
style="fill:none;stroke:#000000;stroke-width:1;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
id="rect3757"
width="70.866142"
height="17.716534"
x="53.149605"
y="77.952736" />
<rect
y="77.952736"
x="124.01575"
height="17.716534"
width="70.866142"
id="rect3761"
style="fill:none;stroke:#000000;stroke-width:1;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0" />
<rect
y="77.952736"
x="194.88188"
height="17.716534"
width="70.866142"
id="rect3763"
style="fill:none;stroke:#000000;stroke-width:1;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0" />
<rect
style="fill:none;stroke:#000000;stroke-width:1;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
id="rect3765"
width="70.866142"
height="17.716534"
x="265.74802"
y="77.952736" />
<rect
style="fill:none;stroke:#000000;stroke-width:1;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
id="rect3767"
width="70.866142"
height="17.716534"
x="336.61417"
y="77.952736" />
<rect
y="77.952736"
x="407.48032"
height="17.716534"
width="70.866142"
id="rect3769"
style="fill:none;stroke:#000000;stroke-width:1;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0" />
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="67.726692"
y="91.152344"
id="text3771"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan3773"
x="67.726692"
y="91.152344">I<tspan
style="font-size:65.00091553%;baseline-shift:super"
id="tspan3775">2</tspan>C Addr</tspan></text>
<rect
style="fill:none;stroke:#000000;stroke-width:1;stroke-miterlimit:4;stroke-opacity:1;stroke-dasharray:none;stroke-dashoffset:0"
id="rect3777"
width="70.866142"
height="17.716534"
x="478.34647"
y="77.952736" />
<text
sodipodi:linespacing="125%"
id="text3779"
y="90.451141"
x="230.31496"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
y="90.451141"
x="230.31496"
id="tspan3781"
sodipodi:role="line"
style="text-align:center;text-anchor:middle">A0</tspan></text>
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="159.44882"
y="90.456024"
id="text3785"
sodipodi:linespacing="125%"><tspan
style="text-align:center;text-anchor:middle"
sodipodi:role="line"
id="tspan3787"
x="159.44882"
y="90.456024">A1</tspan></text>
<text
sodipodi:linespacing="125%"
id="text3789"
y="90.451141"
x="301.18109"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
y="90.451141"
x="301.18109"
id="tspan3791"
sodipodi:role="line"
style="text-align:center;text-anchor:middle">D0</tspan></text>
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="372.04724"
y="90.456024"
id="text3793"
sodipodi:linespacing="125%"><tspan
style="text-align:center;text-anchor:middle"
sodipodi:role="line"
id="tspan3795"
x="372.04724"
y="90.456024">D1</tspan></text>
<text
sodipodi:linespacing="125%"
id="text3797"
y="90.521942"
x="442.91339"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
y="90.521942"
x="442.91339"
id="tspan3799"
sodipodi:role="line"
style="text-align:center;text-anchor:middle">D2</tspan></text>
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="513.77954"
y="90.451141"
id="text3801"
sodipodi:linespacing="125%"><tspan
style="text-align:center;text-anchor:middle"
sodipodi:role="line"
id="tspan3803"
x="513.77954"
y="90.451141">D3</tspan></text>
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="88.58268"
y="74.409424"
id="text3824"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan3826"
x="88.58268"
y="74.409424"
style="font-size:8px;font-style:italic;text-align:center;text-anchor:middle">byte 0</tspan></text>
<text
sodipodi:linespacing="125%"
id="text3832"
y="74.409424"
x="159.44882"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:8px;font-style:italic;text-align:center;text-anchor:middle"
y="74.409424"
x="159.44882"
id="tspan3834"
sodipodi:role="line">byte 1</tspan></text>
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="230.31496"
y="74.409424"
id="text3836"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan3838"
x="230.31496"
y="74.409424"
style="font-size:8px;font-style:italic;text-align:center;text-anchor:middle">byte 2</tspan></text>
<text
sodipodi:linespacing="125%"
id="text3840"
y="74.409424"
x="301.18109"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:8px;font-style:italic;text-align:center;text-anchor:middle"
y="74.409424"
x="301.18109"
id="tspan3842"
sodipodi:role="line">byte 3</tspan></text>
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="372.04724"
y="74.409424"
id="text3844"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan3846"
x="372.04724"
y="74.409424"
style="font-size:8px;font-style:italic;text-align:center;text-anchor:middle">byte 4</tspan></text>
<text
sodipodi:linespacing="125%"
id="text3848"
y="74.409424"
x="442.91339"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
xml:space="preserve"><tspan
style="font-size:8px;font-style:italic;text-align:center;text-anchor:middle"
y="74.409424"
x="442.91339"
id="tspan3850"
sodipodi:role="line">byte 5</tspan></text>
<text
xml:space="preserve"
style="font-size:10px;font-style:normal;font-weight:normal;line-height:125%;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;font-family:Sans"
x="513.77954"
y="74.409424"
id="text3852"
sodipodi:linespacing="125%"><tspan
sodipodi:role="line"
id="tspan3854"
x="513.77954"
y="74.409424"
style="font-size:8px;font-style:italic;text-align:center;text-anchor:middle">byte 6</tspan></text>
</g>
</svg>
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment