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Conv TTL Blocking - Gateware
Commit def26966 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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New folder structure 

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 5cbef60e
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general-cores @ fec74c4d
Subproject commit fec74c4d983ee96a985a05d3384f467ec97376ce
modules/Manifest.py 0 → 100644
View file @ def26966
modules = {
"local" : [
# pulsetest module added from pulsetest syn folder
# Release module added from Release syn folder
"bicolor_led_ctrl",
"vbcp_wb",
"xil_multiboot"
]
}
files = [
"ctb_pulse_gen.vhd",
"glitch_filt.vhd",
"reset_gen.vhd",
"rtm_detector.vhd"
]
modules/Release/Manifest.py 0 → 100644
View file @ def26966
files = [
"conv_regs.vhd"
];
modules/Release/conv_regs.vhd 0 → 100644
View file @ def26966
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Converter board registers
---------------------------------------------------------------------------------------
-- File : conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created : Fri Aug 2 16:02:13 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID register'
conv_regs_id_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'fwvers' in reg: 'Status register'
conv_regs_sr_fwvers_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'switches' in reg: 'Status register'
conv_regs_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status register'
conv_regs_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Port for BIT field: 'Reset unlock bit' in reg: 'Control register'
conv_regs_cr_rst_unlock_o : out std_logic;
-- Port for BIT field: 'Reset bit' in reg: 'Control register'
conv_regs_cr_rst_o : out std_logic
);
end conv_regs;
architecture syn of conv_regs is
signal conv_regs_id_bits_int : std_logic_vector(31 downto 0);
signal conv_regs_cr_rst_unlock_int : std_logic ;
signal conv_regs_cr_rst_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
conv_regs_id_bits_int <= x"424c4f32";
conv_regs_cr_rst_unlock_int <= '0';
conv_regs_cr_rst_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
conv_regs_id_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= conv_regs_id_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= conv_regs_sr_fwvers_i;
rddata_reg(23 downto 16) <= conv_regs_sr_switches_i;
rddata_reg(29 downto 24) <= conv_regs_sr_rtm_i;
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
conv_regs_cr_rst_unlock_int <= wrdata_reg(0);
conv_regs_cr_rst_int <= wrdata_reg(1);
end if;
rddata_reg(0) <= conv_regs_cr_rst_unlock_int;
if (conv_regs_cr_rst_unlock_int = '1') then
rddata_reg(1) <= conv_regs_cr_rst_int;
end if;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- bits
conv_regs_id_bits_o <= conv_regs_id_bits_int;
-- fwvers
-- switches
-- RTM detection
-- Reset unlock bit
conv_regs_cr_rst_unlock_o <= conv_regs_cr_rst_unlock_int;
-- Reset bit
conv_regs_cr_rst_o <= conv_regs_cr_rst_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
modules/Release/conv_regs.wb 0 → 100644
View file @ def26966
peripheral {
name = "Converter board registers";
hdl_entity = "conv_regs";
prefix = "conv_regs";
reg {
name = "Board ID register";
description = "Bits of ID register, defaulting to ASCII string of BLO2";
prefix = "id";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "Status register";
description = "Contains fields for firmware version, switches, RTM detection lines";
prefix = "sr";
field {
name = "fwvers";
prefix = "fwvers";
type = SLV;
size = 16;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "switches";
prefix = "switches";
type = SLV;
size = 8;
align = 16;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "RTM detection";
prefix = "rtm";
type = SLV;
size = 6;
align = 24;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "Control register";
description = "Contains bits that control operation of the converter modules";
prefix = "cr";
-- field {
-- name = "blocking chan 1 enable";
-- prefix = "bch1_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 2 enable";
-- prefix = "bch2_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 3 enable";
-- prefix = "bch3_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 4 enable";
-- prefix = "bch4_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 5 enable";
-- prefix = "bch5_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 6 enable";
-- prefix = "bch6_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
field {
name = "Reset unlock bit";
prefix = "rst_unlock";
description = "1 - unlock reset bit\
0 - lock reset bit";
type = BIT;
align = 30;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reset bit";
prefix = "rst";
description = "1 - initiate logic reset\
0 - no reset";
type = BIT;
align = 31;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
modules/bicolor_led_ctrl/Manifest.py 0 → 100644
View file @ def26966
files = [
"bicolor_led_ctrl_pkg.vhd",
"bicolor_led_ctrl.vhd"
]
modules/bicolor_led_ctrl/README 0 → 100644
View file @ def26966
Taken from:
http://www.ohwr.org/projects/svec/repository/revisions/master/show/hdl/top/bicolor_led_test
Revision: 220c7837
modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd 0 → 100644
View file @ def26966
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Bi-color LED controller
-- http://www.ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: bicolor_led_ctrl
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 11-07-2012
--
-- version: 1.0
--
-- description: Bi-color LED controller. It controls a matrix of bi-color LED.
-- The FPGA ouputs for the columns (C) are connected to buffers
-- and serial resistances and then to the LEDs. The FPGA outputs
-- for lines (L) are connected to tri-state buffers and the to
-- the LEDs. The FPGA outputs for lines output enable (L_OEN) are
-- connected to the output enable of the tri-state buffers.
--
-- Example with three lines and two columns:
--
-- |<refresh period>|
--
-- L1/L2/L3 __|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__
--
-- L1_OEN -----|___________|-----|___________|-----|___________|-----|___________|--
--
-- L2_OEN _____|-----|___________|-----|___________|-----|___________|-----|________
--
-- L3_OEN ___________|-----|___________|-----|___________|-----|___________|-----|__
--
-- Cn __|--|__|--|__|--|_________________|-----------------|--|__|--|__|--|__|--
--
-- LED Ln/Cn OFF | color_1 | color_2 | both_colors |
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.bicolor_led_ctrl_pkg.all;
entity bicolor_led_ctrl is
generic(
g_NB_COLUMN : natural := 4;
g_NB_LINE : natural := 2;
g_CLK_FREQ : natural := 125000000; -- in Hz
g_REFRESH_RATE : natural := 250 -- in Hz
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
led_intensity_i : in std_logic_vector(6 downto 0);
led_state_i : in std_logic_vector((g_NB_LINE * g_NB_COLUMN * 2) - 1 downto 0);
column_o : out std_logic_vector(g_NB_COLUMN - 1 downto 0);
line_o : out std_logic_vector(g_NB_LINE - 1 downto 0);
line_oen_o : out std_logic_vector(g_NB_LINE - 1 downto 0)
);
end bicolor_led_ctrl;
architecture rtl of bicolor_led_ctrl is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_REFRESH_CNT_INIT : natural := natural(g_CLK_FREQ/(2 * g_NB_LINE * g_REFRESH_RATE)) - 1;
constant c_REFRESH_CNT_NB_BITS : natural := log2_ceil(c_REFRESH_CNT_INIT);
constant c_LINE_OEN_CNT_NB_BITS : natural := log2_ceil(g_NB_LINE);
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal refresh_rate_cnt : unsigned(c_REFRESH_CNT_NB_BITS - 1 downto 0);
signal refresh_rate : std_logic;
signal line_ctrl : std_logic;
signal intensity_ctrl_cnt : unsigned(c_REFRESH_CNT_NB_BITS - 1 downto 0);
signal intensity_ctrl : std_logic;
signal line_oen_cnt : unsigned(c_LINE_OEN_CNT_NB_BITS - 1 downto 0);
signal line_oen : std_logic_vector(2**c_LINE_OEN_CNT_NB_BITS - 1 downto 0);
signal led_state : std_logic_vector((g_NB_LINE * g_NB_COLUMN) -1 downto 0);
begin
------------------------------------------------------------------------------
-- Refresh rate counter
------------------------------------------------------------------------------
p_refresh_rate_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
refresh_rate_cnt <= (others => '0');
refresh_rate <= '0';
elsif refresh_rate_cnt = 0 then
refresh_rate_cnt <= to_unsigned(c_REFRESH_CNT_INIT, c_REFRESH_CNT_NB_BITS);
refresh_rate <= '1';
else
refresh_rate_cnt <= refresh_rate_cnt - 1;
refresh_rate <= '0';
end if;
end if;
end process p_refresh_rate_cnt;
------------------------------------------------------------------------------
-- Intensity control
------------------------------------------------------------------------------
p_intensity_ctrl_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
intensity_ctrl_cnt <= (others => '0');
elsif refresh_rate = '1' then
intensity_ctrl_cnt <= to_unsigned(natural(c_REFRESH_CNT_INIT/100) * to_integer(unsigned(led_intensity_i)), c_REFRESH_CNT_NB_BITS);
else
intensity_ctrl_cnt <= intensity_ctrl_cnt - 1;
end if;
end if;
end process p_intensity_ctrl_cnt;
p_intensity_ctrl : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
intensity_ctrl <= '0';
elsif refresh_rate = '1' then
intensity_ctrl <= '1';
elsif intensity_ctrl_cnt = 0 then
intensity_ctrl <= '0';
end if;
end if;
end process p_intensity_ctrl;
------------------------------------------------------------------------------
-- Lines ouput
------------------------------------------------------------------------------
p_line_ctrl : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
line_ctrl <= '0';
elsif refresh_rate = '1' then
line_ctrl <= not(line_ctrl);
end if;
end if;
end process p_line_ctrl;
f_line_o : for I in 0 to g_NB_LINE - 1 generate
line_o(I) <= line_ctrl and intensity_ctrl;
end generate f_line_o;
------------------------------------------------------------------------------
-- Lines output enable
------------------------------------------------------------------------------
p_line_oen_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
line_oen_cnt <= (others => '0');
elsif line_ctrl = '1' and refresh_rate = '1' then
if line_oen_cnt = 0 then
line_oen_cnt <= to_unsigned(g_NB_LINE - 1, c_LINE_OEN_CNT_NB_BITS);
else
line_oen_cnt <= line_oen_cnt - 1;
end if;
end if;
end if;
end process p_line_oen_cnt;
p_line_oen_decode : process(line_oen_cnt)
variable v_onehot : std_logic_vector((2**line_oen_cnt'length)-1 downto 0);
variable v_index : integer range 0 to (2**line_oen_cnt'length)-1;
begin
v_onehot := (others => '0');
v_index := 0;
for i in line_oen_cnt'range loop
if (line_oen_cnt(i) = '1') then
v_index := 2*v_index+1;
else
v_index := 2*v_index;
end if;
end loop;
v_onehot(v_index) := '1';
line_oen <= v_onehot;
end process p_line_oen_decode;
line_oen_o <= line_oen(line_oen_o'left downto 0);
------------------------------------------------------------------------------
-- Columns output
------------------------------------------------------------------------------
f_led_state : for I in 0 to (g_NB_COLUMN * g_NB_LINE) - 1 generate
led_state(I) <= '0' when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED else
'1' when led_state_i(2 * I + 1 downto 2 * I) = c_LED_GREEN else
not(line_ctrl and intensity_ctrl) when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED_GREEN else
(line_ctrl and intensity_ctrl);-- when led_state_i(2 * I + 1 downto 2 * I) = c_LED_OFF else
end generate f_led_state;
f_column_o : for C in 0 to g_NB_COLUMN - 1 generate
column_o(C) <= led_state(g_NB_COLUMN * to_integer(line_oen_cnt) + C);
end generate f_column_o;
end rtl;
modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd 0 → 100644
View file @ def26966
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Bi-color LED controller package
-- http://www.ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: bicolor_led_ctrl_pkg
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 11-07-2012
--
-- version: 1.0
--
-- description: Package for Bi-color LED controller.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package bicolor_led_ctrl_pkg is
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_LED_RED : std_logic_vector(1 downto 0) := "10";
constant c_LED_GREEN : std_logic_vector(1 downto 0) := "01";
constant c_LED_RED_GREEN : std_logic_vector(1 downto 0) := "11";
constant c_LED_OFF : std_logic_vector(1 downto 0) := "00";
------------------------------------------------------------------------------
-- Functions declaration
------------------------------------------------------------------------------
function log2_ceil(N : natural) return positive;
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component bicolor_led_ctrl
generic(
g_NB_COLUMN : natural := 4;
g_NB_LINE : natural := 2;
g_CLK_FREQ : natural := 125000000; -- in Hz
g_REFRESH_RATE : natural := 250 -- in Hz
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
led_intensity_i : in std_logic_vector(6 downto 0);
led_state_i : in std_logic_vector((g_NB_LINE * g_NB_COLUMN * 2) - 1 downto 0);
column_o : out std_logic_vector(g_NB_COLUMN - 1 downto 0);
line_o : out std_logic_vector(g_NB_LINE - 1 downto 0);
line_oen_o : out std_logic_vector(g_NB_LINE - 1 downto 0)
);
end component;
end bicolor_led_ctrl_pkg;
package body bicolor_led_ctrl_pkg is
------------------------------------------------------------------------------
-- Function : Returns log of 2 of a natural number
------------------------------------------------------------------------------
function log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end;
end bicolor_led_ctrl_pkg;
modules/ctb_pulse_gen.vhd 0 → 100644
View file @ def26966
--==============================================================================
-- CERN (BE-CO-HT)
-- Pulse generator with trigger
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-03-01
--
-- version: 1.0
--
-- description:
-- This module generates a variable-width pulse. The width is set using the
-- g_pwidth generic, given in number of clk_i cycles. With a clk_i
-- period of 8ns, the output pulse width is by default 8*16=128ns.
--
-- The module contains a variable length filter, with the length adjustable
-- in clock cycle units via the g_gf_len generic. The glitch filter can be used
-- to avoid a signal being generated as a result of a short glitch on the input.
--
-- Enabling the glitch filter will result in jitter on the leading edge of the
-- output pulse signal. This jitter can be avoided by bypassing the glitch
-- filter; this is done via the gf_en_n_i input.
--
-- Regardless of whether the glitch filter is enabled, the input trigger signal
-- is extended or cut to g_pwidth, if it is shorter or respectively longer than
-- g_pwidth. At the end of the pulse, a rejection phase is implemented in order
-- to avoid too many pulses arriving on the input. This is to safeguard the
-- isolation transformers on the CONV-TTL-BLO boards. The isolation phase
-- limits the input pulse at a 1/5 duty cycle.
--
-- dependencies:
-- none
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 01-03-2013 Theodor Stana t.stana@cern.ch File created
-- 02-08-2013 Theodor Stana t.stana@cern.ch Implemented rejection
-- phase
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ctb_pulse_gen is
generic
(
-- Pulse width, in number of clk_i cycles
g_pwidth : natural := 15;
-- Glitch filter length:
-- g_gf_len=1 => trigger width should be > 1 clk_i cycle
-- g_gf_len=2 => trigger width should be > 2 clk_i cycles
-- etc.
g_gf_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Glitch filter enable input
-- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
-- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
gf_en_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_i : in std_logic;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: g_gf_len+3 clk_i cycles
pulse_o : out std_logic
);
end entity ctb_pulse_gen;
architecture behav of ctb_pulse_gen is
--============================================================================
-- Type declarations
--============================================================================
type t_state is ( ST_IDLE, ST_GEN_GF_OFF, ST_REJ_GF_OFF,
ST_GEN_GF_ON, ST_REJ_GF_ON );
--============================================================================
-- Constant declarations
--============================================================================
-- Max value of pulse counter for pulse width and pulse rejection width; see
-- below for explanation for their values
constant c_pulse_width_gf_off : natural := g_pwidth-5;
constant c_pulse_rej_gf_off : natural := 5*g_pwidth-5;
constant c_pulse_width_gf_on : natural := g_pwidth-1;
constant c_pulse_rej_gf_on : natural := 5*g_pwidth-1;
--============================================================================
-- Function and procedure declarations
--============================================================================
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
--============================================================================
-- Component declarations
--============================================================================
component glitch_filt is
generic
(
-- Length of glitch filter:
-- g_len = 1 => data width should be > 1 clk_i cycle
-- g_len = 2 => data width should be > 2 clk_i cycle
-- etc.
g_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Data input
dat_i : in std_logic;
-- Data output
-- latency: g_len+1 clk_i cycles
dat_o : out std_logic
);
end component glitch_filt;
--============================================================================
-- Signal declarations
--============================================================================
-- Deglitched trigger
signal trig_degl : std_logic;
signal trig_degl_d0 : std_logic;
-- Pulse length counter
signal pulse_cnt : unsigned(f_log2_size(6*g_pwidth)-1 downto 0);
-- Pulse-specific signals
signal pulse_gf_off : std_logic;
signal pulse_gf_off_d0 : std_logic;
signal pulse_gf_off_d1 : std_logic;
signal pulse_gf_off_d2 : std_logic;
signal pulse_rst : std_logic;
signal pulse_gf_on : std_logic;
-- FSM signal
signal state : t_state;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Output logic
--============================================================================
pulse_o <= pulse_gf_off when (gf_en_n_i = '1') else
pulse_gf_on;
--============================================================================
-- Pulse generation logic
--============================================================================
-- Generate the pulse on rising edge of trig_i
p_pulse_gf_off: process(pulse_rst, trig_i)
begin
if (pulse_rst = '1') then
pulse_gf_off <= '0';
elsif rising_edge(trig_i) then
if (en_i = '1') then
pulse_gf_off <= '1';
end if;
end if;
end process p_pulse_gf_off;
-- and synchronize it in clk_i domain
p_sync_pulse_gf_off: process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
pulse_gf_off_d0 <= '0';
pulse_gf_off_d1 <= '0';
pulse_gf_off_d2 <= '0';
elsif (en_i = '1') then
pulse_gf_off_d0 <= pulse_gf_off;
pulse_gf_off_d1 <= pulse_gf_off_d0;
pulse_gf_off_d2 <= pulse_gf_off_d1;
end if;
end if;
end process p_sync_pulse_gf_off;
--============================================================================
-- Glitch filtration logic
--============================================================================
cmp_glitch_filt: glitch_filt
generic map
(
g_len => g_gf_len
)
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
dat_i => trig_i,
dat_o => trig_degl
);
--============================================================================
-- Pulse width adjustment logic
--============================================================================
p_pulse_width: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state <= ST_IDLE;
pulse_rst <= '1';
pulse_gf_on <= '0';
pulse_cnt <= (others => '0');
trig_degl_d0 <= '0';
elsif (en_i = '1') then
-- Deglitched trigger delay
trig_degl_d0 <= trig_degl;
-- State machine
case state is
---------------------------------------------------------------------
-- ST_IDLE
---------------------------------------------------------------------
-- Clear all values and go to pulse generation state when the
-- appropriate input arrives
---------------------------------------------------------------------
when ST_IDLE =>
pulse_cnt <= (others => '0');
pulse_rst <= '0';
if (gf_en_n_i = '1') then
if (pulse_gf_off_d1 = '1') and (pulse_gf_off_d2 = '0') then
state <= ST_GEN_GF_OFF;
end if;
else
if (trig_degl = '1') and (trig_degl_d0 = '0') then
state <= ST_GEN_GF_ON;
end if;
end if;
---------------------------------------------------------------------
-- ST_GEN_GF_OFF
---------------------------------------------------------------------
-- Increment pulse counter to pulse width value.
--
-- Max value: g_pwidth-5 due to:
-- 1. pulse_cnt starts from 0 => g_pwidth-1
-- 2. three cycle delay in clock sync FFs
-- 3. one cycle delay due to reset in next state
--
-- No clock cycle delay for switching from ST_IDLE to ST_GEN_GF_ON,
-- since pulse is already generated on rising edge of trig_i
---------------------------------------------------------------------
when ST_GEN_GF_OFF =>
pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_pulse_width_gf_off) then
state <= ST_REJ_GF_OFF;
end if;
---------------------------------------------------------------------
-- ST_REJ_GF_OFF
---------------------------------------------------------------------
-- Increment pulse counter to pulse rejection value, while keeping
-- the pulse_rst high. Max pulse rejection value is 5x that of
-- pulse width value, to enable 1/5 duty cycle.
---------------------------------------------------------------------
when ST_REJ_GF_OFF =>
pulse_rst <= '1';
pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_pulse_rej_gf_off) then
state <= ST_IDLE;
end if;
---------------------------------------------------------------------
-- ST_GEN_GF_ON
---------------------------------------------------------------------
-- Increment counter to pulse width value and generate glitch-filtered
-- pulse while incrementing.
--
-- Max value: g_pwidth-1, since pulse_cnt starts from 0
---------------------------------------------------------------------
when ST_GEN_GF_ON =>
pulse_cnt <= pulse_cnt + 1;
pulse_gf_on <= '1';
if (pulse_cnt = c_pulse_width_gf_on) then
state <= ST_REJ_GF_ON;
end if;
---------------------------------------------------------------------
-- ST_REJ_GF_ON
---------------------------------------------------------------------
-- Increment pulse counter to pulse rejection value, while keeping
-- the pulse_rst high. Max pulse rejection value is 5x that of
-- pulse width value, to enable 1/5 duty cycle.
---------------------------------------------------------------------
when ST_REJ_GF_ON =>
pulse_gf_on <= '0';
pulse_rst <= '1';
pulse_cnt <= pulse_cnt + 1;
if (pulse_cnt = c_pulse_rej_gf_on) then
state <= ST_IDLE;
end if;
when others =>
state <= ST_IDLE;
end case;
end if;
end if;
end process p_pulse_width;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
modules/glitch_filt.vhd 0 → 100644
View file @ def26966
--==============================================================================
-- CERN (BE-CO-HT)
-- Glitch filter with selectable length
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-03-12
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-03-12 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity glitch_filt is
generic
(
-- Length of glitch filter:
-- g_len = 1 => data width should be > 1 clk_i cycle
-- g_len = 2 => data width should be > 2 clk_i cycle
-- etc.
g_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Data input
dat_i : in std_logic;
-- Data output
-- latency: g_len+1 clk_i cycles
dat_o : out std_logic
);
end entity glitch_filt;
architecture behav of glitch_filt is
--============================================================================
-- Component declarations
--============================================================================
component gc_sync_ffs is
generic(
g_sync_edge : string := "positive"
);
port(
clk_i : in std_logic; -- clock from the destination clock domain
rst_n_i : in std_logic; -- reset
data_i : in std_logic; -- async input
synced_o : out std_logic; -- synchronized output
npulse_o : out std_logic; -- negative edge detect output (single-clock
-- pulse)
ppulse_o : out std_logic -- positive edge detect output (single-clock
-- pulse)
);
end component gc_sync_ffs;
--============================================================================
-- Signal declarations
--============================================================================
signal glitch_filt : std_logic_vector(g_len downto 0);
signal dat_synced : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Glitch filtration logic
--============================================================================
-- First, synchronize the data input in the clk_i domain
cmp_sync : gc_sync_ffs
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => dat_i,
synced_o => dat_synced,
npulse_o => open,
ppulse_o => open
);
-- Then, assign the current sample of the glitch filter
glitch_filt(0) <= dat_synced;
-- Generate glitch filter FFs when the filter length is > 0
gen_glitch_filt: if (g_len > 0) generate
p_glitch_filt: process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
glitch_filt(g_len downto 1) <= (others => '0');
else
glitch_filt(g_len downto 1) <= glitch_filt(g_len-1 downto 0);
end if;
end if;
end process p_glitch_filt;
end generate gen_glitch_filt;
-- and set the data output based on the state of the glitch filter
p_output: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
dat_o <= '0';
elsif (glitch_filt = (glitch_filt'range => '1')) then
dat_o <= '1';
elsif (glitch_filt = (glitch_filt'range => '0')) then
dat_o <= '0';
end if;
end if;
end process p_output;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
modules/pulsetest/Manifest.py 0 → 100644
View file @ def26966
files = [
"conv_regs.vhd",
"pulse_cnt_regs.vhd",
"pgen_ctrl_regs.vhd",
"pulse_gen_gp.vhd"
]
modules/pulsetest/conv_regs.vhd 0 → 100644
View file @ def26966
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Converter board registers
---------------------------------------------------------------------------------------
-- File : conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created : Fri Aug 2 16:02:13 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID register'
conv_regs_id_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'fwvers' in reg: 'Status register'
conv_regs_sr_fwvers_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'switches' in reg: 'Status register'
conv_regs_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status register'
conv_regs_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Port for BIT field: 'Reset unlock bit' in reg: 'Control register'
conv_regs_cr_rst_unlock_o : out std_logic;
-- Port for BIT field: 'Reset bit' in reg: 'Control register'
conv_regs_cr_rst_o : out std_logic
);
end conv_regs;
architecture syn of conv_regs is
signal conv_regs_id_bits_int : std_logic_vector(31 downto 0);
signal conv_regs_cr_rst_unlock_int : std_logic ;
signal conv_regs_cr_rst_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
conv_regs_id_bits_int <= x"424c4f32";
conv_regs_cr_rst_unlock_int <= '0';
conv_regs_cr_rst_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
conv_regs_id_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= conv_regs_id_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= conv_regs_sr_fwvers_i;
rddata_reg(23 downto 16) <= conv_regs_sr_switches_i;
rddata_reg(29 downto 24) <= conv_regs_sr_rtm_i;
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
conv_regs_cr_rst_unlock_int <= wrdata_reg(0);
conv_regs_cr_rst_int <= wrdata_reg(31);
end if;
rddata_reg(0) <= conv_regs_cr_rst_unlock_int;
rddata_reg(31) <= conv_regs_cr_rst_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- bits
conv_regs_id_bits_o <= conv_regs_id_bits_int;
-- fwvers
-- switches
-- RTM detection
-- Reset unlock bit
conv_regs_cr_rst_unlock_o <= conv_regs_cr_rst_unlock_int;
-- Reset bit
conv_regs_cr_rst_o <= conv_regs_cr_rst_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
modules/pulsetest/pgen_ctrl_regs.vhd 0 → 100644
View file @ def26966
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Pulse generation control registers
---------------------------------------------------------------------------------------
-- File : pgen_ctrl_regs.vhd
-- Author : auto-generated by wbgen2 from pgen_ctrl_regs.wb
-- Created : Fri Aug 16 11:22:20 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pgen_ctrl_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pgen_ctrl_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'channel enable' in reg: 'Enable register'
pgen_ctrl_regs_en_ch_o : out std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 delay register'
pgen_ctrl_regs_ch1_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 delay register'
pgen_ctrl_regs_ch2_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 delay register'
pgen_ctrl_regs_ch3_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 delay register'
pgen_ctrl_regs_ch4_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 delay register'
pgen_ctrl_regs_ch5_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 delay register'
pgen_ctrl_regs_ch6_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 pulse width register'
pgen_ctrl_regs_ch1_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 pulse width register'
pgen_ctrl_regs_ch2_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 pulse width register'
pgen_ctrl_regs_ch3_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 pulse width register'
pgen_ctrl_regs_ch4_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 pulse width register'
pgen_ctrl_regs_ch5_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 pulse width register'
pgen_ctrl_regs_ch6_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 frequency register'
pgen_ctrl_regs_ch1_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 frequency register'
pgen_ctrl_regs_ch2_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 frequency register'
pgen_ctrl_regs_ch3_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 frequency register'
pgen_ctrl_regs_ch4_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 frequency register'
pgen_ctrl_regs_ch5_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 frequency register'
pgen_ctrl_regs_ch6_freq_bits_o : out std_logic_vector(31 downto 0)
);
end pgen_ctrl_regs;
architecture syn of pgen_ctrl_regs is
signal pgen_ctrl_regs_en_ch_int : std_logic_vector(5 downto 0);
signal pgen_ctrl_regs_ch1_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch2_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch3_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch4_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch5_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch6_delay_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch1_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch2_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch3_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch4_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch5_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch6_pwidth_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch1_freq_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch2_freq_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch3_freq_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch4_freq_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch5_freq_bits_int : std_logic_vector(31 downto 0);
signal pgen_ctrl_regs_ch6_freq_bits_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(4 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
pgen_ctrl_regs_en_ch_int <= "000000";
pgen_ctrl_regs_ch1_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch2_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch3_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch4_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch5_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch6_delay_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch1_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch2_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch3_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch4_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch5_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch6_pwidth_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch1_freq_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch2_freq_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch3_freq_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch4_freq_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch5_freq_bits_int <= "00000000000000000000000000000000";
pgen_ctrl_regs_ch6_freq_bits_int <= "00000000000000000000000000000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(4 downto 0) is
when "00000" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_en_ch_int <= wrdata_reg(5 downto 0);
end if;
rddata_reg(5 downto 0) <= pgen_ctrl_regs_en_ch_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00001" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch1_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch1_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch2_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch2_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch3_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch3_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00100" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch4_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch4_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00101" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch5_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch5_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00110" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch6_delay_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch6_delay_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00111" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch1_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch1_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01000" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch2_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch2_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01001" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch3_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch3_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01010" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch4_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch4_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01011" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch5_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch5_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01100" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch6_pwidth_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch6_pwidth_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01101" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch1_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch1_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01110" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch2_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch2_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01111" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch3_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch3_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10000" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch4_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch4_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10001" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch5_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch5_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10010" =>
if (wb_we_i = '1') then
pgen_ctrl_regs_ch6_freq_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= pgen_ctrl_regs_ch6_freq_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- channel enable
pgen_ctrl_regs_en_ch_o <= pgen_ctrl_regs_en_ch_int;
-- bits
pgen_ctrl_regs_ch1_delay_bits_o <= pgen_ctrl_regs_ch1_delay_bits_int;
-- bits
pgen_ctrl_regs_ch2_delay_bits_o <= pgen_ctrl_regs_ch2_delay_bits_int;
-- bits
pgen_ctrl_regs_ch3_delay_bits_o <= pgen_ctrl_regs_ch3_delay_bits_int;
-- bits
pgen_ctrl_regs_ch4_delay_bits_o <= pgen_ctrl_regs_ch4_delay_bits_int;
-- bits
pgen_ctrl_regs_ch5_delay_bits_o <= pgen_ctrl_regs_ch5_delay_bits_int;
-- bits
pgen_ctrl_regs_ch6_delay_bits_o <= pgen_ctrl_regs_ch6_delay_bits_int;
-- bits
pgen_ctrl_regs_ch1_pwidth_bits_o <= pgen_ctrl_regs_ch1_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch2_pwidth_bits_o <= pgen_ctrl_regs_ch2_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch3_pwidth_bits_o <= pgen_ctrl_regs_ch3_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch4_pwidth_bits_o <= pgen_ctrl_regs_ch4_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch5_pwidth_bits_o <= pgen_ctrl_regs_ch5_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch6_pwidth_bits_o <= pgen_ctrl_regs_ch6_pwidth_bits_int;
-- bits
pgen_ctrl_regs_ch1_freq_bits_o <= pgen_ctrl_regs_ch1_freq_bits_int;
-- bits
pgen_ctrl_regs_ch2_freq_bits_o <= pgen_ctrl_regs_ch2_freq_bits_int;
-- bits
pgen_ctrl_regs_ch3_freq_bits_o <= pgen_ctrl_regs_ch3_freq_bits_int;
-- bits
pgen_ctrl_regs_ch4_freq_bits_o <= pgen_ctrl_regs_ch4_freq_bits_int;
-- bits
pgen_ctrl_regs_ch5_freq_bits_o <= pgen_ctrl_regs_ch5_freq_bits_int;
-- bits
pgen_ctrl_regs_ch6_freq_bits_o <= pgen_ctrl_regs_ch6_freq_bits_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
modules/pulsetest/pgen_ctrl_regs.wb 0 → 100644
View file @ def26966
peripheral {
name = "Pulse generation control registers";
description = "Registers containing control signals for the general-purpose pulse generator blocks";
hdl_entity = "pgen_ctrl_regs";
prefix = "pgen_ctrl_regs";
reg {
name = "Enable register";
prefix = "en";
field {
name = "channel enable";
prefix = "ch";
type = SLV;
size = 6;
};
};
reg {
name = "CH1 delay register";
prefix = "ch1_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH2 delay register";
prefix = "ch2_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH3 delay register";
prefix = "ch3_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH4 delay register";
prefix = "ch4_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH5 delay register";
prefix = "ch5_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH6 delay register";
prefix = "ch6_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH1 pulse width register";
prefix = "ch1_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH2 pulse width register";
prefix = "ch2_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH3 pulse width register";
prefix = "ch3_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH4 pulse width register";
prefix = "ch4_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH5 pulse width register";
prefix = "ch5_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH6 pulse width register";
prefix = "ch6_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH1 frequency register";
prefix = "ch1_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH2 frequency register";
prefix = "ch2_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH3 frequency register";
prefix = "ch3_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH4 frequency register";
prefix = "ch4_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH5 frequency register";
prefix = "ch5_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH6 frequency register";
prefix = "ch6_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
};
modules/pulsetest/pulse_cnt_regs.vhd 0 → 100644
View file @ def26966
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Pulse counter registers
---------------------------------------------------------------------------------------
-- File : pulse_cnt_regs.vhd
-- Author : auto-generated by wbgen2 from pulse_cnt_regs.wb
-- Created : Mon Sep 16 18:23:47 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pulse_cnt_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_cnt_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH1 input'
pulse_cnt_ch1i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH1 output'
pulse_cnt_ch1o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH2 input'
pulse_cnt_ch2i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH2 output'
pulse_cnt_ch2o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH3 input'
pulse_cnt_ch3i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH3 output'
pulse_cnt_ch3o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH4 input'
pulse_cnt_ch4i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH4 output'
pulse_cnt_ch4o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH5 input'
pulse_cnt_ch5i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH5 output'
pulse_cnt_ch5o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 input'
pulse_cnt_ch6i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 output'
pulse_cnt_ch6o_val_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: 'reset' in reg: 'Counter reset'
pulse_cnt_rst_bit_o : out std_logic
);
end pulse_cnt_regs;
architecture syn of pulse_cnt_regs is
signal pulse_cnt_rst_bit_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
pulse_cnt_rst_bit_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch1i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch1o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch2i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch2o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch3i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0101" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch3o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch4i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "0111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch4o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch5i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch5o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1010" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch6i_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= pulse_cnt_ch6o_val_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "1100" =>
if (wb_we_i = '1') then
pulse_cnt_rst_bit_int <= wrdata_reg(0);
end if;
rddata_reg(0) <= pulse_cnt_rst_bit_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- number of pulses
-- reset
pulse_cnt_rst_bit_o <= pulse_cnt_rst_bit_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
modules/pulsetest/pulse_cnt_regs.wb 0 → 100644
View file @ def26966
peripheral {
name = "Pulse counter registers";
description = "Registers containing the values for input and output generated pulses";
hdl_entity = "pulse_cnt_regs";
prefix = "pulse_cnt";
reg {
name = "CH1 input";
prefix = "ch1i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH1 output";
prefix = "ch1o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH2 input";
prefix = "ch2i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH2 output";
prefix = "ch2o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH3 input";
prefix = "ch3i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH3 output";
prefix = "ch3o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH4 input";
prefix = "ch4i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH4 output";
prefix = "ch4o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH5 input";
prefix = "ch5i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH5 output";
prefix = "ch5o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH6 input";
prefix = "ch6i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH6 output";
prefix = "ch6o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Counter reset";
prefix = "rst";
field {
name = "reset";
prefix = "bit";
type = BIT;
};
};
};
modules/pulsetest/pulse_gen_gp.vhd 0 → 100644
View file @ def26966
--==============================================================================
-- CERN (BE-CO-HT)
-- General-purpose pulse generator
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-02-28
--
-- version: 2.0
--
-- description:
--
-- This module generates pulses with configurable frequency, width and delay.
--
-- In order to generate pulses, the module must be enabled via the en_i port.
-- Once en_i is high, pulses are generated at the frequency specified via
-- freq_i, with the width specified via pwidth_i.
--
-- An optional delay can be added before the start of the pulse, via the delay_i
-- port.
--
-- Note that this delay can be set only before the module is enabled.
--
-- freq_i, pwidth_i and delay_i are given in clk_i cycles.
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-02-28 Theodor Stana t.stana@cern.ch File created
-- 2013 08-15 Theodor Stana t.stana@cern.ch v2.0, delay, pwidth, freq
-- now controllable via
-- inputs (regs, etc.)
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_gen_gp is
port
(
-- Input clock and active-low reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Active high enable signal
en_i : in std_logic;
-- Delay, pulse width and frequency inputs, in number of clk_i cycles
delay_i : in std_logic_vector(31 downto 0);
pwidth_i : in std_logic_vector(31 downto 0);
freq_i : in std_logic_vector(31 downto 0);
-- Output pulse signal
pulse_o : out std_logic
);
end entity pulse_gen_gp;
architecture behav of pulse_gen_gp is
--============================================================================
-- Function and procedure declarations
--============================================================================
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
--============================================================================
-- Signal declarations
--============================================================================
signal inp_delay : unsigned(31 downto 0);
signal inp_pwidth : unsigned(31 downto 0);
signal inp_freq : unsigned(31 downto 0);
signal freq_cnt : unsigned(31 downto 0);
signal delay_cnt : unsigned(31 downto 0);
signal delay_en : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Convert std_logic_vector inputs to unsigned
--============================================================================
inp_delay <= unsigned(delay_i);
inp_pwidth <= unsigned(pwidth_i);
inp_freq <= unsigned(freq_i);
--============================================================================
-- Delay logic
--============================================================================
p_delay: process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') or (en_i = '0') then
delay_en <= '1';
delay_cnt <= (others => '0');
else
if (inp_delay = (inp_delay'range => '0')) then
delay_en <= '0';
elsif (delay_en = '1') then
delay_cnt <= delay_cnt + 1;
if (delay_cnt = inp_delay) then
delay_en <= '0';
delay_cnt <= (others => '0');
end if;
end if;
end if;
end if;
end process p_delay;
--============================================================================
-- Pulse generation logic
--============================================================================
p_gen_pulse: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') or (en_i = '0') then
freq_cnt <= (others => '0');
pulse_o <= '0';
elsif (delay_en = '0') then
freq_cnt <= freq_cnt + 1;
pulse_o <= '0';
if (freq_cnt < inp_pwidth) then
pulse_o <= '1';
elsif (freq_cnt = inp_freq-1) then
freq_cnt <= (others => '0');
end if;
end if;
end if;
end process p_gen_pulse;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
modules/reset_gen.vhd 0 → 100644
View file @ def26966
--==============================================================================
-- CERN (BE-CO-HT)
-- Reset generator for CONV-TTL-* boards
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-03-05
--
-- version: 1.0
--
-- description:
-- This module generates a variable-width reset pulse. The width of the pulse
-- is set via the g_reset_time pulse; an internal counter counts up to this
-- value and de-asserts the active-low reset line when the value has been
-- reached. At the same time, the module is de-activated.
--
-- By default, a 125 MHz clock is assumed (8ns period), resulting in a 96ms
-- reset width.
--
-- dependencies:
-- none
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-03-05 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reset_gen is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time : positive := 12_000_000
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
rst_n_o : out std_logic
);
end entity reset_gen;
architecture behav of reset_gen is
--============================================================================
-- Function and procedure declarations
--============================================================================
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
--============================================================================
-- Signal declarations
--============================================================================
signal cnt : unsigned(f_log2_size(g_reset_time)-1 downto 0) := (others => '0');
signal cnt_en : std_logic := '1';
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Reset generation logic
--============================================================================
p_rst_gen: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
cnt_en <= '1';
cnt <= (others => '0');
elsif (cnt_en = '1') then
rst_n_o <= '0';
cnt <= cnt + 1;
if (cnt = g_reset_time) then
rst_n_o <= '1';
cnt_en <= '0';
end if;
end if;
end if;
end process p_rst_gen;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
modules/rtm_detector.vhd 0 → 100644
View file @ def26966
--==============================================================================
-- CERN (BE-CO-HT)
-- Rear transition module (RTM) detector
--==============================================================================
--
-- author: Carlos Gil Soriano
-- Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-01-09
--
-- version: 2.0
--
-- description:
--
-- This module detects the presence of rear transition module motherboards
-- (RTMMs) and piggybacks (RTMPs). Detection works by checking the RTMM and
-- RTMP input pins and these pins are pulled up on the front module. The
-- RTMM_OK and RTMP_OK ouputs are set if the corresponding inputs do not
-- yield errors. Different boards have the RTMM/P pins setup differently,
-- as outlined in the tables below:
--
-- Table 1. RTMM detection pins.
-- __________________________________________
-- | Board | RTMM[2] | RTMM[1] | RTMM[0] |
-- +-----------------------------------------+
-- | Error | '1' | '1' | '1' |
-- | RTMM_V1 | '1' | '1' | '0' |
-- | RTMM_V2 | '1' | '0' | '1' |
-- | Reserved | '1' | '0' | '0' |
-- | Reserved | '0' | '1' | '1' |
-- | Reserved | '0' | '1' | '0' |
-- | Reserved | '0' | '0' | '1' |
-- | Reserved | '0' | '0' | '0' |
-- +-----------+---------+---------+---------+
--
--
-- Table 2. RTMP detection pins.
-- _____________________________________________
-- | Board | RTMP[2] | RTMP[1] | RTMP[0] |
-- +-------------------------------------------+
-- | Error OR | '1' | '1' | '1' |
-- | Blocking_V1 | | | |
-- | RS485_V1 | '1' | '1' | '0' |
-- | -Reserved- | '1' | '0' | '1' |
-- | -Reserved- | '1' | '0' | '0' |
-- | -Reserved- | '0' | '1' | '1' |
-- | -Reserved- | '0' | '1' | '0' |
-- | -Reserved- | '0' | '0' | '1' |
-- | Error | '0' | '0' | '0' |
-- +-------------+---------+---------+---------+
--
--
-- dependencies:
-- none
--
-- references:
-- http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-01-09 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity rtm_detector is
port
(
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
rtmm_ok_o : out std_logic;
rtmp_ok_o : out std_logic
);
end entity rtm_detector;
architecture Behavioral of rtm_detector is
begin
rtmm_ok_o <= '0' when (rtmm_i = "111") else '1';
rtmp_ok_o <= '0' when (rtmp_i = "111") else '1';
end Behavioral;
modules/vbcp_wb/Manifest.py 0 → 100644
View file @ def26966
files = [
"i2c_slave_pkg.vhd",
"i2c_slave.vhd",
"vbcp_wb.vhd"
]
modules = {
"local" : ".."
}
modules/vbcp_wb/i2c_slave.vhd 0 → 100644
View file @ def26966
--==============================================================================
-- CERN (BE-CO-HT)
-- I2C slave core
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-03-13
--
-- version: 1.0
--
-- description:
--
-- Simple I2C slave interface, providing the basic low-level functionality
-- of the I2C protocol.
--
-- The i2c_slave module waits for a master to initiate a transfer via
-- a start condition. The address is sent next and if the address matches
-- the slave address set via the i2c_addr_i input, the done_p_o output
-- is set. Based on the eighth bit of the first I2C transfer byte, the module
-- then starts shifting in or out each byte in the transfer, setting the
-- done_p_o output after each received/sent byte.
--
-- For master write (slave read) transfers, the received byte can be read at
-- the rx_byte_o output when the done_p_o pin is high. For master read (slave
-- write) transfers, the slave sends the byte at the tx_byte_i input, which
-- should be set when the done_p_o output is high, either after I2C address
-- reception, or a successful send of a previous byte.
--
-- dependencies:
-- none.
--
-- references:
-- [1] The I2C bus specification, version 2.1, NXP Semiconductor, Jan. 2000
-- http://www.nxp.com/documents/other/39340011.pdf
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-03-13 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO:
-- - Stop condition
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.i2c_slave_pkg.all;
entity i2c_slave is
port
(
-- Clock, reset ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C lines
scl_i : in std_logic;
scl_o : out std_logic;
scl_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
-- Slave address
i2c_addr_i : in std_logic_vector(6 downto 0);
-- ACK input, should be set after done_p_o = '1'
-- (note that the bit is reversed wrt I2C ACK bit)
-- '1' - ACK
-- '0' - NACK
i2c_ack_i : in std_logic;
-- I2C bus operation, set after address detection
-- '0' - write
-- '1' - read
op_o : out std_logic;
-- Byte to send, should be loaded while done_p_o = '1'
tx_byte_i : in std_logic_vector(7 downto 0);
-- Received byte, valid after done_p_o = '1'
rx_byte_o : out std_logic_vector(7 downto 0);
-- Done pulse signal, valid when
-- * received address matches i2c_addr_i, signaling valid op_o;
-- * a byte was received, signaling valid rx_byte_o and an ACK/NACK should be
-- sent to master;
-- * sent a byte, should set tx_byte_i.
done_p_o : out std_logic;
-- I2C transfer state
-- "00" - Idle
-- "01" - Got address, matches i2c_addr_i
-- "10" - Read done, waiting ACK/NACK
-- "11" - Write done, waiting next byte
stat_o : out std_logic_vector(1 downto 0)
);
end entity i2c_slave;
architecture behav of i2c_slave is
--============================================================================
-- Type declarations
--============================================================================
type t_state is
(
IDLE, -- idle
STA, -- start condition received
ADDR, -- shift in I2C address bits
ADDR_ACK, -- ACK/NACK to I2C address
RD, -- shift in byte to read
RD_ACK, -- ACK/NACK to received byte
WR_LOAD_TXSR, -- load byte to send via I2C
WR, -- shift out byte
WR_ACK -- get ACK/NACK from master
);
--============================================================================
-- Component declarations
--============================================================================
component glitch_filt is
generic
(
-- Length of glitch filter:
-- g_len = 1 => data width should be > 1 clk_i cycle
-- g_len = 2 => data width should be > 2 clk_i cycle
-- etc.
g_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Data input
dat_i : in std_logic;
-- Data output
-- latency: g_len+1 clk_i cycles
dat_o : out std_logic
);
end component glitch_filt;
--============================================================================
-- Signal declarations
--============================================================================
-- Deglitched signals and delays for SCL and SDA lines
signal scl_deglitched : std_logic;
signal scl_deglitched_d0 : std_logic;
signal sda_deglitched : std_logic;
signal sda_deglitched_d0 : std_logic;
signal scl_r_edge_p : std_logic;
signal scl_f_edge_p : std_logic;
signal sda_f_edge_p : std_logic;
signal sda_r_edge_p : std_logic;
-- FSM
signal state : t_state;
-- FSM tick
signal tick_p : std_logic;
signal tick_cnt : std_logic_vector(5 downto 0);
-- RX and TX shift registers
signal txsr : std_logic_vector(7 downto 0);
signal rxsr : std_logic_vector(7 downto 0);
-- Bit counter on RX & TX
signal bit_cnt : unsigned(2 downto 0);
-- Watchdog counter signals
signal watchdog_cnt : unsigned(26 downto 0);
signal watchdog_rst : std_logic;
signal rst_fr_watchdog : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- I/O logic
--============================================================================
-- No clock stretching implemented, always disable SCL line
scl_o <= '0';
scl_en_o <= '0';
-- SDA line driven low; SDA_EN line controls when the tristate buffer is enabled
sda_o <= '0';
-- Assign RX byte output
rx_byte_o <= rxsr;
--============================================================================
-- Deglitching logic
--============================================================================
-- Generate deglitched SCL signal with 54-ns max. glitch width
cmp_scl_deglitch : glitch_filt
generic map
(
g_len => 7
)
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
dat_i => scl_i,
dat_o => scl_deglitched
);
-- and create a delayed version of this signal, together with one-tick-long
-- falling-edge detection signal
p_scl_degl_d0 : process(clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
scl_deglitched_d0 <= '0';
scl_f_edge_p <= '0';
scl_r_edge_p <= '0';
else
scl_deglitched_d0 <= scl_deglitched;
scl_f_edge_p <= (not scl_deglitched) and scl_deglitched_d0;
scl_r_edge_p <= scl_deglitched and (not scl_deglitched_d0);
end if;
end if;
end process p_scl_degl_d0;
-- Generate deglitched SDA signal with 54-ns max. glitch width
cmp_sda_deglitch : glitch_filt
generic map
(
g_len => 7
)
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
dat_i => sda_i,
dat_o => sda_deglitched
);
-- and create a delayed version of this signal, together with one-tick-long
-- falling- and rising-edge detection signals
p_sda_deglitched_d0 : process(clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
sda_deglitched_d0 <= '0';
sda_f_edge_p <= '0';
sda_r_edge_p <= '0';
else
sda_deglitched_d0 <= sda_deglitched;
sda_f_edge_p <= (not sda_deglitched) and sda_deglitched_d0;
sda_r_edge_p <= sda_deglitched and (not sda_deglitched_d0);
end if;
end if;
end process p_sda_deglitched_d0;
--============================================================================
-- Tick generation
--============================================================================
-- p_tick : process (clk_i) is
-- begin
-- if rising_edge(clk_i) then
-- if (rst_n_i = '0') then
-- tick_cnt <= '0';
-- tick_p <= '0';
-- elsif (scl_f_edge_p = '1') then
-- tick_en <= '1';
-- else
-- if (tick_en = '1') then
-- tick_cnt <= tick_cnt + 1;
-- tick_p <= '0';
-- if (tick_cnt = (tick_cnt'range => '1')) then
-- tick_p <= '1';
-- tick_en <= '0';
-- end if;
-- else
-- tick_p <= '0';
-- end if;
-- end if;
-- end if;
-- end process p_tick;
--============================================================================
-- FSM logic
--============================================================================
p_fsm: process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') or (rst_fr_watchdog = '1') then
state <= IDLE;
watchdog_rst <= '1';
bit_cnt <= (others => '0');
rxsr <= (others => '0');
txsr <= (others => '0');
sda_en_o <= '0';
done_p_o <= '0';
op_o <= '0';
stat_o <= c_i2cs_idle;
-- I2C start condition
elsif (sda_f_edge_p = '1') and (scl_deglitched = '1') then
state <= ADDR;
bit_cnt <= (others => '0');
watchdog_rst <= '0';
-- I2C stop condition
elsif (sda_r_edge_p = '1') and (scl_deglitched = '1') then
state <= IDLE;
done_p_o <= '1';
stat_o <= c_i2cs_idle;
-- state machine logic
else
case state is
---------------------------------------------------------------------
-- IDLE
---------------------------------------------------------------------
-- When idle, outputs and bit counters are cleared, while waiting
-- for a start condition.
---------------------------------------------------------------------
when IDLE =>
bit_cnt <= (others => '0');
sda_en_o <= '0';
done_p_o <= '0';
watchdog_rst <= '1';
stat_o <= c_i2cs_idle;
-- ---------------------------------------------------------------------
-- -- STA
-- ---------------------------------------------------------------------
-- -- When a start condition is received, the bit counter gets cleared
-- -- to prepare for receiving the address byte. On the falling edge of
-- -- SCL, we go into the address state.
-- ---------------------------------------------------------------------
-- when STA =>
-- bit_cnt <= (others => '0');
-- if (scl_f_edge_p = '1') then
-- state <= ADDR;
-- end if;
---------------------------------------------------------------------
-- ADDR
---------------------------------------------------------------------
-- Shift in the seven address bits and the R/W bit, and go to address
-- acknowledgement. When the eighth bit has been shifted in, check
-- if address is ours and signal to external module. Then, go to
-- ADDR_ACK state.
---------------------------------------------------------------------
when ADDR =>
-- Shifting in is done on rising edge of SCL
if (scl_r_edge_p = '1') then
rxsr <= rxsr(6 downto 0) & sda_deglitched;
bit_cnt <= bit_cnt + 1;
-- Shifted in 8 bits, go to ADDR_ACK. Check to see if received
-- address is ours and set op_o if so.
if (bit_cnt = 7) then
state <= ADDR_ACK;
if (rxsr(6 downto 0) = i2c_addr_i) then
op_o <= sda_deglitched;
done_p_o <= '1';
stat_o <= c_i2cs_addr_good;
end if;
end if;
end if;
---------------------------------------------------------------------
-- ADDR_ACK
---------------------------------------------------------------------
-- Here, we check to see if the address is ours and ACK/NACK
-- accordingly. The next action is dependent upon the state of the
-- R/W bit received via I2C.
---------------------------------------------------------------------
when ADDR_ACK =>
-- Clear done pulse
done_p_o <= '0';
-- we write the ACK bit, so enable output
sda_en_o <= i2c_ack_i;
-- If the received address is ours, send the ACK set by external
-- module and, on the falling edge of SCL, go to appropriate state
-- based on R/W bit.
if (rxsr(7 downto 1) = i2c_addr_i) then
if (scl_f_edge_p = '1') then
sda_en_o <= '0';
if (rxsr(0) = '0') then
state <= RD;
else
state <= WR_LOAD_TXSR;
end if;
end if;
-- If received address is not ours, NACK and go back to IDLE
else
sda_en_o <= '0';
state <= IDLE;
end if;
---------------------------------------------------------------------
-- RD
---------------------------------------------------------------------
-- Shift in bits sent by the master.
---------------------------------------------------------------------
when RD =>
-- Shifting occurs on falling edge of SCL
if (scl_f_edge_p = '1') then
rxsr <= rxsr(6 downto 0) & sda_deglitched;
bit_cnt <= bit_cnt + 1;
-- Received 8 bits, go to RD_ACK and signal external module
if (bit_cnt = 7) then
state <= RD_ACK;
done_p_o <= '1';
stat_o <= c_i2cs_rd_done;
end if;
end if;
---------------------------------------------------------------------
-- RD_ACK
---------------------------------------------------------------------
-- Send ACK/NACK, as received from external command
---------------------------------------------------------------------
when RD_ACK =>
-- Clear done pulse
done_p_o <= '0';
-- we write the ACK bit, so enable output and send the ACK bit
sda_en_o <= i2c_ack_i;
-- based on the ACK received by external command, we read the next
-- bit (ACK) or go back to idle state (NACK)
if (scl_f_edge_p = '1') then
sda_en_o <= '0';
if (i2c_ack_i = '1') then
state <= RD;
else
state <= IDLE;
end if;
end if;
---------------------------------------------------------------------
-- WR_LOAD_TXSR
---------------------------------------------------------------------
-- Load TXSR with the input value.
---------------------------------------------------------------------
when WR_LOAD_TXSR =>
txsr <= tx_byte_i;
state <= WR;
---------------------------------------------------------------------
-- WR
---------------------------------------------------------------------
-- Shift out the eight bits of TXSR.
---------------------------------------------------------------------
when WR =>
-- slave writes, so enable output
sda_en_o <= txsr(7);
-- Shift TXSR on falling edge of SCL
if (scl_f_edge_p = '1') then
txsr <= txsr(6 downto 0) & '0';
bit_cnt <= bit_cnt + 1;
-- Eight bits sent, disable SDA end go to WR_ACK
if (bit_cnt = 7) then
sda_en_o <= '0';
state <= WR_ACK;
done_p_o <= '1';
stat_o <= c_i2cs_wr_done;
end if;
end if;
---------------------------------------------------------------------
-- WR_ACK
---------------------------------------------------------------------
-- The master drives the ACK bit here, so on the falling edge of
-- SCL, we check the ack bit. A '0' (ACK) means more bits should be sent,
-- so we load the next value of the TXSR. A '1' (NACK) means the
-- master is done reading and a STO follows, so we go back to IDLE
-- state.
---------------------------------------------------------------------
when WR_ACK =>
done_p_o <= '0';
if (scl_f_edge_p = '1') then
if (sda_deglitched = '0') then
state <= WR_LOAD_TXSR;
else
state <= IDLE;
end if;
end if;
---------------------------------------------------------------------
-- Any other state: go back to idle.
---------------------------------------------------------------------
when others =>
state <= IDLE;
end case;
end if;
end if;
end process p_fsm;
--============================================================================
-- Watchdog counter process
-- Resets the FSM after one second. The watchdog_rst signal is controlled by
-- the FSM and resets the watchdog if the I2C master still controls the
-- slave, signaled by the SCL line going low. If for one second the master
-- does not toggle the SCL line, the FSM gets reset.
--============================================================================
p_watchdog: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') or (watchdog_rst = '1') then
watchdog_cnt <= (others => '0');
rst_fr_watchdog <= '0';
else
watchdog_cnt <= watchdog_cnt + 1;
rst_fr_watchdog <= '0';
if (watchdog_cnt = 124999999) then
watchdog_cnt <= (others => '0');
rst_fr_watchdog <= '1';
end if;
end if;
end if;
end process p_watchdog;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
modules/vbcp_wb/i2c_slave_pkg.vhd 0 → 100644
View file @ def26966
--==============================================================================
-- CERN (BE-CO-HT)
-- Package for i2c_slave.vhd
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-06-06
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-06-06 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package i2c_slave_pkg is
--============================================================================
-- Constant declarations
--============================================================================
constant c_i2cs_idle : std_logic_vector(1 downto 0) := "00";
constant c_i2cs_addr_good : std_logic_vector(1 downto 0) := "01";
constant c_i2cs_rd_done : std_logic_vector(1 downto 0) := "10";
constant c_i2cs_wr_done : std_logic_vector(1 downto 0) := "11";
--============================================================================
-- Component declarations
--============================================================================
component i2c_slave is
port
(
-- Clock, reset ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C lines
scl_i : in std_logic;
scl_o : out std_logic;
scl_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
-- Slave address
i2c_addr_i : in std_logic_vector(6 downto 0);
-- ACK input, should be set after done_p_o = '1'
-- (note that the bit is reversed wrt I2C ACK bit)
-- '1' - ACK
-- '0' - NACK
i2c_ack_i : in std_logic;
-- I2C bus operation, set after address detection
-- '0' - write
-- '1' - read
op_o : out std_logic;
-- Byte to send, should be loaded while done_p_o = '1'
tx_byte_i : in std_logic_vector(7 downto 0);
-- Received byte, valid after done_p_o = '1'
rx_byte_o : out std_logic_vector(7 downto 0);
-- Done pulse signal, valid when
-- * received address matches i2c_addr_i, signaling valid op_o;
-- * a byte was received, signaling valid rx_byte_o and an ACK/NACK should be
-- sent to master;
-- * sent a byte, should set tx_byte_i.
done_p_o : out std_logic;
-- I2C transfer state
-- "00" - Idle
-- "01" - Got address, matches i2c_addr_i
-- "10" - Read done, waiting ACK/NACK
-- "11" - Write done, waiting next byte
stat_o : out std_logic_vector(1 downto 0)
);
end component i2c_slave;
end package i2c_slave_pkg;
modules/vbcp_wb/vbcp_wb.vhd 0 → 100644
View file @ def26966
--==============================================================================
-- CERN (BE-CO-HT)
-- VME Board Control Protocol (VBCP) to Wishbone bridge for VME64x crates
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-02-15
--
-- version: 1.0
--
-- description:
-- This module implements an I2C to Wishbone bridge for VME64x crates,
-- following the protocol defined in [1]. It uses a low-level I2C slave module
-- reacting to transfers initiated by an I2C master, in this case, a VME64x
-- system monitor (SysMon) [2].
--
-- The I2C slave module sets its done_p_o pin high when the I2C address received
-- from the SysMon corresponds to the slave address and every time a byte has
-- been received or sent correctly. The done_p_o pin of the slave module is
-- de-asserted when the slave performs a transfer.
--
-- The bridge module employs a state machine that checks for low-to-high
-- transitions in the slave done_p_o pin and shifts bytes in and out over I2C
-- to implement the protocol defined in [1].
--
-- dependencies:
-- none.
--
-- references:
-- [1] ELMA SNMP Specification
-- http://www.ohwr.org/documents/227
-- [2] System Monitor's Users Manual
-- http://www.ohwr.org/documents/226
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-02-28 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.i2c_slave_pkg.all;
entity vbcp_wb is
port
(
-- Clock, reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C lines
sda_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
-- I2C address
i2c_addr_i : in std_logic_vector(6 downto 0);
-- Transfer In Progress (TIP) and Error outputs
-- TIP : '1' when the I2C slave detects a matching I2C address, thus a
-- transfer is in progress
-- '0' when idle
-- ERR : '1' when the SysMon attempts to access an invalid WB slave
-- '0' when idle
tip_o : out std_logic;
err_o : out std_logic;
-- Wishbone master signals
wbm_stb_o : out std_logic;
wbm_cyc_o : out std_logic;
wbm_sel_o : out std_logic_vector(3 downto 0);
wbm_we_o : out std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_adr_o : out std_logic_vector(31 downto 0);
wbm_ack_i : in std_logic;
wbm_rty_i : in std_logic;
wbm_err_i : in std_logic
);
end entity vbcp_wb;
architecture behav of vbcp_wb is
--============================================================================
-- Type declarations
--============================================================================
type t_state is
(
IDLE, -- idle state
SYSMON_WB_ADR, -- get the WB register address
SIM_WB_TRANSF, -- simulate a WB transfer with the received address
OPER, -- operation to perform on the WB register
SYSMON_RD_WB, -- perform a WB read transfer, for sending word to the SysMon
SYSMON_RD, -- send the word to the SysMon during read transfer
SYSMON_WR, -- read the word sent by the SysMon during write transfer
SYSMON_WR_WB -- perform a WB write transfer, storing the received word
);
--============================================================================
-- Signal declarations
--============================================================================
-- Slave component signals
signal i2c_ack : std_logic;
signal op : std_logic;
signal start_op : std_logic;
signal tx_byte : std_logic_vector(7 downto 0);
signal rx_byte : std_logic_vector(7 downto 0);
signal done : std_logic;
signal done_d0 : std_logic;
signal stat : std_logic_vector(1 downto 0);
-- Wishbone temporary signals
signal wb_dat_out : std_logic_vector(31 downto 0);
signal wb_dat_in : std_logic_vector(31 downto 0);
signal wb_adr : std_logic_vector(15 downto 0);
signal wb_cyc : std_logic;
signal wb_stb : std_logic;
signal wb_we : std_logic;
signal wb_ack : std_logic;
signal wb_err : std_logic;
signal wb_rty : std_logic;
-- FSM control signals
signal state : t_state;
signal dat_byte_cnt : unsigned(1 downto 0);
signal adr_byte_cnt : unsigned(0 downto 0);
begin
--============================================================================
-- Slave component instantiation and connection
--============================================================================
cmp_i2c_slave: i2c_slave
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
-- I2C lines
scl_i => scl_i,
scl_o => scl_o,
scl_en_o => scl_en_o,
sda_i => sda_i,
sda_o => sda_o,
sda_en_o => sda_en_o,
-- Slave address
i2c_addr_i => i2c_addr_i,
-- ACK input, should be set after done_p_o = '1'
-- '0' - ACK
-- '1' - NACK
i2c_ack_i => i2c_ack,
-- I2C bus operation, set after address detection
-- '0' - write
-- '1' - read
op_o => op,
-- Byte to send, should be loaded while done_p_o = '1'
tx_byte_i => tx_byte,
-- Received byte, valid after done_p_o = '1'
rx_byte_o => rx_byte,
-- Done signal, valid when
-- * received address matches i2c_addr_i, signaling valid op_o;
-- * a byte was received, signaling valid rx_byte_o and an ACK/NACK should be
-- sent to master;
-- * sent a byte, should set tx_byte_i.
done_p_o => done,
stat_o => stat
);
--============================================================================
-- I2C to Wishbone bridge FSM logic
--============================================================================
-- First, assign Wishbone outputs
wbm_dat_o <= wb_dat_out;
wbm_adr_o <= x"0000" & wb_adr;
wbm_cyc_o <= wb_cyc;
wbm_stb_o <= wb_stb;
wbm_we_o <= wb_we;
wbm_sel_o <= (others => '1');
-- Next, assign some Wishbone inputs to internal signals
wb_ack <= wbm_ack_i;
wb_err <= wbm_err_i;
wb_rty <= wbm_rty_i;
-- Then, assign the I2C byte to TX to the first byte of the internal WB input
-- data signal; shifting is handled inside the FSM.
tx_byte <= wb_dat_in(7 downto 0);
-- Finally, the FSM logic
p_fsm: process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state <= IDLE;
wb_adr <= (others => '0');
wb_dat_out <= (others => '0');
wb_dat_in <= (others => '0');
wb_cyc <= '0';
wb_stb <= '0';
wb_we <= '0';
start_op <= '0';
i2c_ack <= '0';
tip_o <= '0';
err_o <= '0';
adr_byte_cnt <= (others => '0');
dat_byte_cnt <= (others => '0');
else
case state is
---------------------------------------------------------------------
-- IDLE
---------------------------------------------------------------------
-- After the slave acknowledges its I2C address, the register address
-- bytes have to be shifted in. The start-of-transfer operation
-- is also stored here, to check versus the third I2C transfer in
-- the protocol. At this point, since the SysMon writes the WB
-- address, start_op will be '0' (write).
---------------------------------------------------------------------
when IDLE =>
err_o <= '0';
tip_o <= '0';
i2c_ack <= '0';
dat_byte_cnt <= (others => '0');
if (done = '1') and (stat = c_i2cs_addr_good) then
tip_o <= '1';
i2c_ack <= '1';
state <= SYSMON_WB_ADR;
start_op <= op;
end if;
---------------------------------------------------------------------
-- SYSMON_WB_ADR
---------------------------------------------------------------------
-- Shift in the two address bytes sent by the SysMon and ACK each of
-- them. The second byte's ACK is also controlled by the next state.
---------------------------------------------------------------------
when SYSMON_WB_ADR =>
if (done = '1') then
if (stat = c_i2cs_rd_done) then
wb_adr <= wb_adr(7 downto 0) & rx_byte;
i2c_ack <= '1';
adr_byte_cnt <= adr_byte_cnt + 1;
if (adr_byte_cnt = 1) then
state <= SIM_WB_TRANSF;
end if;
else
i2c_ack <= '0';
state <= IDLE;
end if;
end if;
---------------------------------------------------------------------
-- SIM_WB_TRANSF
---------------------------------------------------------------------
-- Simulate a Wishbone transfer with the received address and go
-- to operation state if we get a WB ACK, or back to idle if we get
-- a WB error. In the latter case, an NACK is sent to the SysMon.
---------------------------------------------------------------------
when SIM_WB_TRANSF =>
wb_cyc <= '1';
wb_stb <= '1';
if (wb_ack = '1') then
i2c_ack <= '1';
wb_cyc <= '0';
wb_stb <= '0';
state <= OPER;
elsif (wb_err = '1') then
err_o <= '1';
i2c_ack <= '0';
wb_cyc <= '0';
wb_stb <= '0';
state <= IDLE;
end if;
---------------------------------------------------------------------
-- OPER
---------------------------------------------------------------------
-- This is the third I2C transfer occuring in the protocol. At this
-- point, the first byte of a SysMon write transfer is sent, or a
-- restart, I2C slave address and read bit are sent to signal a
-- SysMon read transfer.
--
-- So, here we shift in the received byte in case of a SysMon write
-- transfer and then check the OP signal. This is set by the slave
-- while it is in its I2C address read state and will be different
-- from the starting case if a read transfer ('1') occurs.
--
-- If a read transfer follows, the data byte counter and WB data
-- output are cleared to avoid conflicts with future transfers.
---------------------------------------------------------------------
when OPER =>
if (done = '1') then
if (stat = c_i2cs_rd_done) then
wb_dat_out <= rx_byte & wb_dat_out(31 downto 8);
dat_byte_cnt <= dat_byte_cnt + 1;
i2c_ack <= '1';
state <= SYSMON_WR;
elsif (stat = c_i2cs_addr_good) and (op /= start_op) then
i2c_ack <= '1';
state <= SYSMON_RD_WB;
else
i2c_ack <= '0';
state <= IDLE;
end if;
end if;
---------------------------------------------------------------------
-- SYSMON_WR
---------------------------------------------------------------------
-- During write transfers, each byte is shifted in, until all bytes
-- in the transfer have been sent. When this has occured, a Wishbone
-- write transfer is initiated in the next state.
---------------------------------------------------------------------
when SYSMON_WR =>
if (done = '1') then
if (stat = c_i2cs_rd_done) then
wb_dat_out <= rx_byte & wb_dat_out(31 downto 8);
dat_byte_cnt <= dat_byte_cnt + 1;
i2c_ack <= '1';
if (dat_byte_cnt = 3) then
state <= SYSMON_WR_WB;
end if;
else
i2c_ack <= '0';
state <= IDLE;
end if;
end if;
---------------------------------------------------------------------
-- SYSMON_WR_WB
---------------------------------------------------------------------
-- Perform a write transfer over Wishbone bus with the received
-- data word.
---------------------------------------------------------------------
when SYSMON_WR_WB =>
wb_cyc <= '1';
wb_stb <= '1';
wb_we <= '1';
if (wb_ack = '1') then -- or (wb_err = '1') then
wb_cyc <= '0';
wb_stb <= '0';
wb_we <= '0';
state <= SYSMON_WR; --IDLE;
elsif (wb_err = '1') then
err_o <= '1';
state <= IDLE;
end if;
---------------------------------------------------------------------
-- SYSMON_RD_WB
---------------------------------------------------------------------
-- This state is reached from the operation state; here, we perform
-- a read transfer on the Wishbone bus to prepare the data that
-- should be sent to the SysMon. If the WB address is incorrect, we
-- go back to the IDLE state.
---------------------------------------------------------------------
when SYSMON_RD_WB =>
wb_cyc <= '1';
wb_stb <= '1';
if (wb_ack = '1') then
wb_dat_in <= wbm_dat_i;
wb_cyc <= '0';
wb_stb <= '0';
state <= SYSMON_RD;
elsif (wb_err = '1') then
err_o <= '1';
wb_cyc <= '0';
wb_stb <= '0';
state <= IDLE;
end if;
---------------------------------------------------------------------
-- SYSMON_RD
---------------------------------------------------------------------
-- Shift out the bytes over I2C and go back to IDLE state.
---------------------------------------------------------------------
when SYSMON_RD =>
if (done = '1') then
if (stat = c_i2cs_wr_done) then
wb_dat_in <= x"00" & wb_dat_in(31 downto 8);
dat_byte_cnt <= dat_byte_cnt + 1;
i2c_ack <= '1';
if (dat_byte_cnt = 3) then
state <= IDLE;
end if;
else
i2c_ack <= '0';
state <= IDLE;
end if;
end if;
---------------------------------------------------------------------
-- Any other state: go back to idle.
---------------------------------------------------------------------
when others =>
state <= IDLE;
end case;
end if;
end if;
end process p_fsm;
end behav;
modules/xil_multiboot/Manifest.py 0 → 100644
View file @ def26966
files = [
"spi_master.vhd",
"multiboot_fsm.vhd",
"multiboot_regs.vhd",
"xil_multiboot.vhd"
]
modules/xil_multiboot/multiboot_fsm.vhd 0 → 100644
View file @ def26966
--==============================================================================
-- CERN (BE-CO-HT)
-- Xilinx MultiBoot FSM
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-08-19
--
-- version: 1.0
--
-- description:
-- The finite-state machine (FSM) module for the xil_multiboot module. Based
-- on input received from the MultiBoot module registers, it starts one of
-- three sequences:
-- - SPI -- shift out up to three bytes (based on the NBYTES)
-- value in FAR
-- - RDCFGREG -- read a configuration register from the Xilinx FPGA
-- configuration logic
-- - IPROG -- issue an IPROG command to the Xilinx FPGA configuration
-- logic
--
-- references:
-- [1] Xilinx UG380 Spartan-6 FPGA Configuration Guide v2.5
-- http://www.xilinx.com/support/documentation/user_guides/ug380.pdf
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-08-19 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity multiboot_fsm is
port
(
-- Clock and reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Control register inputs
reg_rdcfgreg_i : in std_logic;
reg_cfgregadr_i : in std_logic_vector(5 downto 0);
reg_iprog_i : in std_logic;
-- Multiboot and golden bitstream start addresses
reg_gbbar_i : in std_logic_vector(31 downto 0);
reg_mbbar_i : in std_logic_vector(31 downto 0);
-- Outputs to status register
reg_cfgreg_img_o : out std_logic_vector(15 downto 0);
reg_cfgreg_valid_o : out std_logic;
-- Flash access register signals
reg_far_data_i : in std_logic_vector(23 downto 0);
reg_far_data_o : out std_logic_vector(23 downto 0);
reg_far_nbytes_i : in std_logic_vector(1 downto 0);
reg_far_xfer_i : in std_logic;
reg_far_cs_i : in std_logic;
reg_far_ready_o : out std_logic;
-- SPI master signals
spi_xfer_o : out std_logic;
spi_cs_o : out std_logic;
spi_data_i : in std_logic_vector(7 downto 0);
spi_data_o : out std_logic_vector(7 downto 0);
spi_ready_i : in std_logic;
-- Ports for the external ICAP component
icap_dat_i : in std_logic_vector(15 downto 0);
icap_dat_o : out std_logic_vector(15 downto 0);
icap_busy_i : in std_logic;
icap_ce_n_o : out std_logic;
icap_wr_n_o : out std_logic
);
end entity multiboot_fsm;
architecture behav of multiboot_fsm is
--============================================================================
-- Type declarations
--============================================================================
type t_state is
(
-- idle state
IDLE,
-- SPI states
SPI_XFER1,
SPI_XFER2,
-- Config logic synchronization states
DUMMY_1,
DUMMY_2,
SYNC_H,
SYNC_L,
SYNC_NOOP,
-- IPROG states
GEN_1,
MBA_L,
GEN_2,
MBA_H,
GEN_3,
GBA_L,
GEN_4,
GBA_H,
IPROG_CMD,
IPROG,
-- RDCFGREG read states
RDCFGREG_CMD,
RDCFGREG_NOOP_1,
RDCFGREG_NOOP_2,
RDCFGREG_NOOP_3,
RDCFGREG_NOOP_4,
RDCFGREG_SETRD_1,
RDCFGREG_SETRD_2,
RDCFGREG_SETRD_3,
RDCFGREG,
RDCFGREG_SETWR_1,
RDCFGREG_SETWR_2,
RDCFGREG_SETWR_3,
DESYNC_CMD,
DESYNC,
-- NOOPs after RDCFGREG and IPROG sequences
FINAL_NOOP_1,
FINAL_NOOP_2,
PREPARE_IDLE
);
--============================================================================
-- Signal declarations
--============================================================================
signal state : t_state;
signal fsm_cmd : std_logic_vector(2 downto 0);
signal fsm_cmd_reg : std_logic_vector(2 downto 0);
signal fl_bcnt : unsigned(1 downto 0);
signal fl_sreg : std_logic_vector(31 downto 0);
signal first : std_logic;
signal spi_data_int : std_logic_vector(23 downto 0);
signal spi_cnt : unsigned(1 downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- FSM logic
--============================================================================
-- Form state machine command vector from inputs
fsm_cmd <= reg_far_xfer_i &
reg_iprog_i &
reg_rdcfgreg_i;
-- Assign SPI outputs
spi_cs_o <= reg_far_cs_i;
spi_data_o <= spi_data_int(7 downto 0);
-- The state machine process
p_fsm : process(clk_i)
variable v_idx : integer := 0;
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state <= IDLE;
fsm_cmd_reg <= (others => '0');
icap_dat_o <= (others => '0');
icap_ce_n_o <= '1';
icap_wr_n_o <= '1';
reg_cfgreg_img_o <= (others => '0');
reg_cfgreg_valid_o <= '0';
reg_far_ready_o <= '1';
reg_far_data_o <= (others => '0');
spi_data_int <= (others => '0');
spi_cnt <= "00";
spi_xfer_o <= '0';
else
case state is
--====================================================================
-- IDLE: wait for a register bit to be set
--====================================================================
when IDLE =>
icap_ce_n_o <= '1';
icap_wr_n_o <= '1';
fsm_cmd_reg <= fsm_cmd;
case fsm_cmd is
when "010" | "001" =>
state <= DUMMY_1;
when "100" =>
spi_cnt <= "00";
spi_data_int <= reg_far_data_i;
reg_far_data_o <= (others => '0');
reg_far_ready_o <= '0';
state <= SPI_XFER1;
when others =>
state <= IDLE;
end case;
--====================================================================
-- Flash read sequence
--====================================================================
-- set the transfer bit to the SPI master
when SPI_XFER1 =>
spi_xfer_o <= '1';
state <= SPI_XFER2;
-- wait for SPI master to be ready and shift out new bytes, or go back
-- to idle if we've finished the number of bytes we have to send
when SPI_XFER2 =>
spi_xfer_o <= '0';
if (spi_ready_i = '1') then
-- prepare next byte to be sent
spi_cnt <= spi_cnt + 1;
spi_data_int <= x"00" & spi_data_int(23 downto 8);
state <= SPI_XFER1;
-- or if we've sent NBYTES, go back to IDLE
if (spi_cnt = unsigned(reg_far_nbytes_i)) then
reg_far_ready_o <= '1';
state <= IDLE;
end if;
-- finally, place the received byte in the appropriate position
-- of the FAR data field
v_idx := to_integer(unsigned(spi_cnt));
reg_far_data_o((1+v_idx)*8 - 1 downto v_idx*8) <= spi_data_i;
end if;
--====================================================================
-- Synchronization sequence + four NOOPs
-- as per Table 6-1, p. 113 [1], steps 1-10
--====================================================================
-- two dummy words
when DUMMY_1 =>
icap_dat_o <= x"ffff";
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
state <= DUMMY_2;
when DUMMY_2 =>
icap_dat_o <= x"ffff";
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
state <= SYNC_H;
-- now the two sync words
when SYNC_H =>
icap_dat_o <= x"aa99";
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
state <= SYNC_L;
when SYNC_L =>
icap_dat_o <= x"5566";
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
state <= SYNC_NOOP;
-- and the NOOP after the sync words, after which we go to IPROG or
-- RDCFGREG read, depending on what command we got at the beginning
when SYNC_NOOP =>
icap_dat_o <= x"2000";
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
case fsm_cmd_reg is
when "010" =>
state <= GEN_1;
when "001" =>
state <= RDCFGREG_CMD;
when others =>
state <= IDLE;
end case;
--====================================================================
-- IPROG sequence
-- as per Table 7-1, p. 130 [1], starting from step 4 onward
--====================================================================
when GEN_1 =>
icap_dat_o <= x"3261";
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
state <= MBA_L;
when MBA_L =>
icap_dat_o <= reg_mbbar_i(15 downto 0);
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
state <= GEN_2;
when GEN_2 =>
icap_dat_o <= x"3281";
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
state <= MBA_H;
when MBA_H =>
icap_dat_o <= reg_mbbar_i(31 downto 16);
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
state <= GEN_3;
when GEN_3 =>
icap_dat_o <= x"32a1";
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
state <= GBA_L;
when GBA_L =>
icap_dat_o <= reg_gbbar_i(15 downto 0);
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
state <= GEN_4;
when GEN_4 =>
icap_dat_o <= x"32c1";
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
state <= GBA_H;
when GBA_H =>
icap_dat_o <= reg_gbbar_i(31 downto 16);
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
state <= IPROG_CMD;
when IPROG_CMD =>
icap_dat_o <= x"30a1";
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
state <= IPROG;
when IPROG =>
icap_dat_o <= x"000e";
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
state <= FINAL_NOOP_1;
--====================================================================
-- RDCFGREG read sequence
-- as per Table 6-1, p.113 [1], starting from step 6
--====================================================================
-- write type1 packet header to read CFGREGADR register
-- (packet headers can be found on page 93 of [1])
when RDCFGREG_CMD =>
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
icap_dat_o <= "001" & "01" & reg_cfgregadr_i & "00001";
state <= RDCFGREG_NOOP_1;
-- then four noops
when RDCFGREG_NOOP_1 =>
icap_dat_o <= x"2000";
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
state <= RDCFGREG_NOOP_2;
when RDCFGREG_NOOP_2 =>
icap_dat_o <= x"2000";
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
state <= RDCFGREG_NOOP_3;
when RDCFGREG_NOOP_3 =>
icap_dat_o <= x"2000";
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
state <= RDCFGREG_NOOP_4;
when RDCFGREG_NOOP_4 =>
icap_dat_o <= x"2000";
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
state <= RDCFGREG_SETRD_1;
-- smooth transition of the ICAP write input from write to read
-- (keep CS high while changing WRITE)
when RDCFGREG_SETRD_1 =>
icap_ce_n_o <= '1';
icap_wr_n_o <= '0';
state <= RDCFGREG_SETRD_2;
when RDCFGREG_SETRD_2 =>
icap_ce_n_o <= '1';
icap_wr_n_o <= '1';
state <= RDCFGREG_SETRD_3;
when RDCFGREG_SETRD_3 =>
icap_ce_n_o <= '0';
icap_wr_n_o <= '1';
state <= RDCFGREG;
-- this is where we actually read the value of RDCFGREG;
-- data retrieved by ICAP interface is valid when busy is low
when RDCFGREG =>
icap_ce_n_o <= '0';
icap_wr_n_o <= '1';
if (icap_busy_i = '0') then
reg_cfgreg_img_o <= icap_dat_i;
reg_cfgreg_valid_o <= '1';
state <= RDCFGREG_SETWR_1;
end if;
-- smooth transition of the ICAP write input from read to write
-- (keep CS high while changing WRITE)
when RDCFGREG_SETWR_1 =>
icap_ce_n_o <= '1';
icap_wr_n_o <= '1';
state <= RDCFGREG_SETWR_2;
when RDCFGREG_SETWR_2 =>
icap_ce_n_o <= '1';
icap_wr_n_o <= '0';
state <= RDCFGREG_SETWR_3;
when RDCFGREG_SETWR_3 =>
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
if (icap_busy_i = '0') then
state <= DESYNC_CMD;
end if;
-- write 1 word to CMD register
when DESYNC_CMD =>
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
icap_dat_o <= x"30a1";
state <= DESYNC;
-- write the DESYNC command
when DESYNC =>
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
icap_dat_o <= x"000d";
state <= FINAL_NOOP_1;
--====================================================================
-- Two NOOPs at end of all prog sequences
--====================================================================
when FINAL_NOOP_1 =>
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
icap_dat_o <= x"2000";
state <= FINAL_NOOP_2;
when FINAL_NOOP_2 =>
icap_ce_n_o <= '0';
icap_wr_n_o <= '0';
icap_dat_o <= x"2000";
state <= PREPARE_IDLE;
--====================================================================
-- Prepare transition to CE='1', WR='1' in IDLE state
--====================================================================
when PREPARE_IDLE =>
icap_ce_n_o <= '1';
icap_wr_n_o <= '0';
state <= IDLE;
--====================================================================
-- Go to IDLE in case of state error
--====================================================================
when others =>
state <= IDLE;
end case;
end if;
end if;
end process p_fsm;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
modules/xil_multiboot/multiboot_regs.vhd 0 → 100644
View file @ def26966
--==============================================================================
-- CERN (BE-CO-HT)
-- Wishbone registers for xil_multiboot design
--==============================================================================
--
-- author: auto-generated by wbgen2 from conv_regs.wb and modified by
-- Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-08-19
--
-- version: 1.0
--
-- description:
-- Implements the registers and Wishbone interface for the MultiBoot design.
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-08-19 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity multiboot_regs is
port (
-- Clock and reset inputs
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
-- Wishbone ports
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Fields of control register
multiboot_cr_rdcfgreg_o : out std_logic;
multiboot_cr_cfgregadr_o : out std_logic_vector(5 downto 0);
multiboot_cr_iprog_o : out std_logic;
-- Fields of status register
multiboot_sr_cfgreg_img_i : in std_logic_vector(15 downto 0);
multiboot_sr_valid_i : in std_logic;
-- Fields of bitstream address registers
multiboot_gbbar_o : out std_logic_vector(31 downto 0);
multiboot_mbbar_o : out std_logic_vector(31 downto 0);
-- Fields of FAR register
multiboot_far_data_i : in std_logic_vector(23 downto 0);
multiboot_far_data_o : out std_logic_vector(23 downto 0);
multiboot_far_nbytes_o : out std_logic_vector(1 downto 0);
multiboot_far_xfer_o : out std_logic;
multiboot_far_cs_o : out std_logic;
multiboot_far_ready_i : in std_logic
);
end multiboot_regs;
architecture behav of multiboot_regs is
signal multiboot_cr_rdcfgreg_int : std_logic;
signal multiboot_cr_cfgregadr_int : std_logic_vector(5 downto 0);
signal multiboot_cr_iprog_int : std_logic;
signal multiboot_cr_iprog_unl_int : std_logic;
signal multiboot_cr_flr_int : std_logic;
signal multiboot_cr_flw_int : std_logic;
signal multiboot_sr_cfgreg_img_int : std_logic_vector(15 downto 0);
signal multiboot_sr_valid_int : std_logic;
signal multiboot_sr_flrrdy_int : std_logic;
signal multiboot_sr_flwrdy_int : std_logic;
signal multiboot_gbbar_int : std_logic_vector(31 downto 0);
signal multiboot_mbbar_int : std_logic_vector(31 downto 0);
signal multiboot_flrdr_int : std_logic_vector(31 downto 0);
signal multiboot_flwdr_int : std_logic_vector(31 downto 0);
signal multiboot_far_data_load_int : std_logic;
signal multiboot_far_data_int : std_logic_vector(23 downto 0);
signal multiboot_far_nbytes_int : std_logic_vector(1 downto 0);
signal multiboot_far_xfer_int : std_logic;
signal multiboot_far_cs_int : std_logic;
signal multiboot_far_ready_int : std_logic;
signal ack_sreg : std_logic_vector(1 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic;
begin
-- Some internal signals assignments.
wrdata_reg <= wb_dat_i;
rwaddr_reg <= wb_adr_i;
multiboot_sr_cfgreg_img_int <= multiboot_sr_cfgreg_img_i;
multiboot_sr_valid_int <= multiboot_sr_valid_i;
multiboot_far_ready_int <= multiboot_far_ready_i;
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= (others => '0');
ack_in_progress <= '0';
rddata_reg <= (others => '0');
multiboot_cr_rdcfgreg_int <= '0';
multiboot_cr_cfgregadr_int <= (others => '0');
multiboot_cr_iprog_int <= '0';
multiboot_cr_iprog_unl_int <= '0';
multiboot_gbbar_int <= (others => '0');
multiboot_mbbar_int <= (others => '0');
multiboot_far_nbytes_int <= "00";
multiboot_far_data_int <= (others => '0');
multiboot_far_cs_int <= '0';
multiboot_far_xfer_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(0) <= ack_sreg(1);
ack_sreg(1) <= '0';
if (ack_in_progress = '1') then
multiboot_cr_rdcfgreg_int <= '0';
multiboot_far_xfer_int <= '0';
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg is
when "000" =>
if (wb_we_i = '1') then
multiboot_cr_cfgregadr_int <= wrdata_reg(5 downto 0);
multiboot_cr_rdcfgreg_int <= wrdata_reg(6);
multiboot_cr_iprog_unl_int <= wrdata_reg(16);
if (multiboot_cr_iprog_unl_int = '1') then
multiboot_cr_iprog_int <= wrdata_reg(17);
end if;
end if;
rddata_reg(5 downto 0) <= multiboot_cr_cfgregadr_int;
rddata_reg(6) <= multiboot_cr_rdcfgreg_int;
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= multiboot_cr_iprog_unl_int;
rddata_reg(17) <= multiboot_cr_iprog_int;
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "001" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= multiboot_sr_cfgreg_img_int;
rddata_reg(16) <= multiboot_sr_valid_int;
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
if (wb_we_i = '1') then
multiboot_gbbar_int <= wrdata_reg;
end if;
rddata_reg <= multiboot_gbbar_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
if (wb_we_i = '1') then
multiboot_mbbar_int <= wrdata_reg;
end if;
rddata_reg <= multiboot_mbbar_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
if (wb_we_i = '1') then
multiboot_far_data_int <= wrdata_reg(23 downto 0);
multiboot_far_nbytes_int <= wrdata_reg(25 downto 24);
multiboot_far_xfer_int <= wrdata_reg(26);
multiboot_far_cs_int <= wrdata_reg(27);
end if;
rddata_reg(23 downto 0) <= multiboot_far_data_i;
rddata_reg(25 downto 24) <= multiboot_far_nbytes_int;
rddata_reg(26) <= multiboot_far_xfer_int;
rddata_reg(27) <= multiboot_far_cs_int;
rddata_reg(28) <= multiboot_far_ready_int;
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Drive the stall line
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- Configuration register address
multiboot_cr_cfgregadr_o <= multiboot_cr_cfgregadr_int;
-- Read configuration register
multiboot_cr_rdcfgreg_o <= multiboot_cr_rdcfgreg_int;
-- IPROG
multiboot_cr_iprog_o <= multiboot_cr_iprog_int;
-- GBBAR
multiboot_gbbar_o <= multiboot_gbbar_int;
-- MBBAR
multiboot_mbbar_o <= multiboot_mbbar_int;
-- FAR outputs
multiboot_far_data_o <= multiboot_far_data_int; --wrdata_reg(23 downto 0);
multiboot_far_nbytes_o <= multiboot_far_nbytes_int;
multiboot_far_xfer_o <= multiboot_far_xfer_int;
multiboot_far_cs_o <= multiboot_far_cs_int;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end behav;
modules/xil_multiboot/spi_master.vhd 0 → 100644
View file @ def26966
-----------------------------------------------------------------------------
-- Title : SPI Bus Master
-- Project : Simple VME64x FMC Carrier (SVEC)
-------------------------------------------------------------------------------
-- File : spi_master.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2013-01-25
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Just a simple SPI master (bus-less).
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011-2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_master is
generic(
-- clock division ratio (SCLK = clk_sys_i / (2 ** g_div_ratio_log2).
g_div_ratio_log2 : integer := 2;
-- number of data bits per transfer
g_num_data_bits : integer := 2);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- state of the Chip select line (1 = CS active). External control
-- allows for multi-transfer commands (SPI master itself does not
-- control the state of spi_cs_n_o)
cs_i : in std_logic;
-- 1: start next transfer (using CPOL, DATA and SEL from the inputs below)
start_i : in std_logic;
-- Clock polarity: 1: slave clocks in the data on rising SCLK edge, 0: ...
-- on falling SCLK edge
cpol_i : in std_logic;
-- TX Data input
data_i : in std_logic_vector(g_num_data_bits - 1 downto 0);
-- 1: data_o contains the result of last read operation. Core is ready to initiate
-- another transfer.
ready_o : out std_logic;
-- data read from selected slave, valid when ready_o == 1.
data_o : out std_logic_vector(g_num_data_bits - 1 downto 0);
-- these are obvious
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end spi_master;
architecture behavioral of spi_master is
signal divider : unsigned(11 downto 0);
signal tick : std_logic;
signal sreg : std_logic_vector(g_num_data_bits-1 downto 0);
signal rx_sreg : std_logic_vector(g_num_data_bits-1 downto 0);
type t_state is (IDLE, TX_CS, TX_DAT1, TX_DAT2, TX_SCK1, TX_SCK2, TX_CS2, TX_GAP);
signal state : t_state;
signal sclk : std_logic;
signal counter : unsigned(4 downto 0);
begin -- rtl
-- Simple clock divder. Produces a 'tick' signal which defines the timing for
-- the main state machine transitions.
p_divide_spi_clock: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
divider <= (others => '0');
else
if(start_i = '1' or tick = '1') then
divider <= (others => '0');
else
divider <= divider + 1;
end if;
end if;
end if;
end process;
tick <= divider(g_div_ratio_log2);
-- Main state machine. Executes SPI transfers
p_main_fsm: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
state <= IDLE;
sclk <= '0';
sreg <= (others => '0');
rx_sreg <= (others => '0');
spi_mosi_o <= '0';
data_o <= (others => '0');
counter <= (others => '0');
else
case state is
-- Waits for start of transfer command
when IDLE =>
sclk <= '0';
counter <= (others => '0');
if(start_i = '1') then
sreg <= data_i;
state <= TX_CS;
spi_mosi_o <= data_i(sreg'high);
end if;
-- Generates a gap between the externally asserted Chip Select and
-- the beginning of data transfer
when TX_CS =>
if tick = '1' then
state <= TX_DAT1;
end if;
-- Outputs subsequent bits to MOSI line.
when TX_DAT1 =>
if(tick = '1') then
spi_mosi_o <= sreg(sreg'high);
sreg <= sreg(sreg'high-1 downto 0) & '0';
state <= TX_SCK1;
end if;
-- Flips the SCLK (active edge)
when TX_SCK1 =>
if(tick = '1') then
sclk <= not sclk;
counter <= counter + 1;
state <= TX_DAT2;
end if;
-- Shifts in bits read from the slave
when TX_DAT2 =>
if(tick = '1') then
rx_sreg <= rx_sreg(rx_sreg'high-1 downto 0) & spi_miso_i;
state <= TX_SCK2;
end if;
-- Flips the SCLK (inactive edge). Checks if all bits have been
-- transferred.
when TX_SCK2 =>
if(tick = '1') then
sclk <= not sclk;
if(counter = g_num_data_bits) then
state <= TX_CS2;
else
state <= TX_DAT1;
end if;
end if;
-- Generates a gap for de-assertoin of CS line
when TX_CS2 =>
if(tick = '1') then
state <= TX_GAP;
data_o <= rx_sreg;
end if;
when TX_GAP =>
if (tick = '1') then
state <= IDLE;
end if;
end case;
end if;
end if;
end process;
ready_o <= '1' when (state = IDLE and start_i = '0') else '0';
-- SCLK polarity control
spi_sclk_o <= sclk xor cpol_i;
spi_cs_n_o <= not cs_i;
end behavioral;
modules/xil_multiboot/xil_multiboot.vhd 0 → 100644
View file @ def26966
--==============================================================================
-- CERN (BE-CO-HT)
-- Xilinx MultiBoot core top-level file
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-08-19
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-08-19 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
use work.wishbone_pkg.all;
entity xil_multiboot is
port
(
-- Clock and reset input ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone ports
wbs_i : in t_wishbone_slave_in;
wbs_o : out t_wishbone_slave_out;
-- SPI ports
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end entity xil_multiboot;
architecture behav of xil_multiboot is
--============================================================================
-- Component declarations
--============================================================================
-- Register component
component multiboot_regs is
port (
-- Clock and reset inputs
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
-- Wishbone ports
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Fields of control register
multiboot_cr_rdcfgreg_o : out std_logic;
multiboot_cr_cfgregadr_o : out std_logic_vector(5 downto 0);
multiboot_cr_iprog_o : out std_logic;
-- Fields of status register
multiboot_sr_cfgreg_img_i : in std_logic_vector(15 downto 0);
multiboot_sr_valid_i : in std_logic;
-- Fields of bitstream address registers
multiboot_gbbar_o : out std_logic_vector(31 downto 0);
multiboot_mbbar_o : out std_logic_vector(31 downto 0);
-- Fields of FAR register
multiboot_far_data_i : in std_logic_vector(23 downto 0);
multiboot_far_data_o : out std_logic_vector(23 downto 0);
multiboot_far_nbytes_o : out std_logic_vector(1 downto 0);
multiboot_far_xfer_o : out std_logic;
multiboot_far_cs_o : out std_logic;
multiboot_far_ready_i : in std_logic
);
end component multiboot_regs;
-- FSM component
component multiboot_fsm is
port
(
-- Clock and reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Control register inputs
reg_rdcfgreg_i : in std_logic;
reg_cfgregadr_i : in std_logic_vector(5 downto 0);
reg_iprog_i : in std_logic;
-- Multiboot and golden bitstream start addresses
reg_gbbar_i : in std_logic_vector(31 downto 0);
reg_mbbar_i : in std_logic_vector(31 downto 0);
-- Outputs to status register
reg_cfgreg_img_o : out std_logic_vector(15 downto 0);
reg_cfgreg_valid_o : out std_logic;
-- Flash access register signals
reg_far_data_i : in std_logic_vector(23 downto 0);
reg_far_data_o : out std_logic_vector(23 downto 0);
reg_far_nbytes_i : in std_logic_vector(1 downto 0);
reg_far_xfer_i : in std_logic;
reg_far_cs_i : in std_logic;
reg_far_ready_o : out std_logic;
-- SPI master signals
spi_xfer_o : out std_logic;
spi_cs_o : out std_logic;
spi_data_i : in std_logic_vector(7 downto 0);
spi_data_o : out std_logic_vector(7 downto 0);
spi_ready_i : in std_logic;
-- Ports for the external ICAP component
icap_dat_i : in std_logic_vector(15 downto 0);
icap_dat_o : out std_logic_vector(15 downto 0);
icap_busy_i : in std_logic;
icap_ce_n_o : out std_logic;
icap_wr_n_o : out std_logic
);
end component multiboot_fsm;
-- SPI master
component spi_master is
generic(
-- clock division ratio (SCLK = clk_sys_i / (2 ** g_div_ratio_log2).
g_div_ratio_log2 : integer := 2;
-- number of data bits per transfer
g_num_data_bits : integer := 2);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- state of the Chip select line (1 = CS active). External control
-- allows for multi-transfer commands (SPI master itself does not
-- control the state of spi_cs_n_o)
cs_i : in std_logic;
-- 1: start next transfer (using CPOL, DATA and SEL from the inputs below)
start_i : in std_logic;
-- Clock polarity: 1: slave clocks in the data on rising SCLK edge, 0: ...
-- on falling SCLK edge
cpol_i : in std_logic;
-- TX Data input
data_i : in std_logic_vector(g_num_data_bits - 1 downto 0);
-- 1: data_o contains the result of last read operation. Core is ready to initiate
-- another transfer.
ready_o : out std_logic;
-- data read from selected slave, valid when ready_o == 1.
data_o : out std_logic_vector(g_num_data_bits - 1 downto 0);
-- these are obvious
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end component spi_master;
--============================================================================
-- Signal declarations
--============================================================================
-- Control and status register signals
signal rdcfgreg : std_logic;
signal cfgregadr : std_logic_vector(5 downto 0);
signal iprog : std_logic;
signal cfgreg_img : std_logic_vector(15 downto 0);
signal sr_valid : std_logic;
signal gbbar, mbbar : std_logic_vector(31 downto 0);
-- FSM signals
signal fsm_icap_din : std_logic_vector(15 downto 0);
signal fsm_icap_dout : std_logic_vector(15 downto 0);
-- Flash controller signals
signal far_data_out : std_logic_vector(23 downto 0);
signal far_data_in : std_logic_vector(23 downto 0);
signal far_nbytes : std_logic_vector(1 downto 0);
signal far_xfer : std_logic;
signal far_cs : std_logic;
signal far_ready : std_logic;
-- SPI master signals
signal spi_data_in : std_logic_vector(7 downto 0);
signal spi_data_out : std_logic_vector(7 downto 0);
signal spi_xfer : std_logic;
signal spi_cs : std_logic;
signal spi_ready : std_logic;
-- ICAP signals
signal icap_ce_n : std_logic;
signal icap_wr_n : std_logic;
signal icap_busy : std_logic;
signal icap_din : std_logic_vector(15 downto 0);
signal icap_dout : std_logic_vector(15 downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Register component instantiation
--============================================================================
cmp_regs : multiboot_regs
port map
(
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
wb_adr_i => wbs_i.adr(4 downto 2),
wb_dat_i => wbs_i.dat,
wb_dat_o => wbs_o.dat,
wb_cyc_i => wbs_i.cyc,
wb_sel_i => wbs_i.sel,
wb_stb_i => wbs_i.stb,
wb_we_i => wbs_i.we,
wb_ack_o => wbs_o.ack,
wb_stall_o => wbs_o.stall,
multiboot_cr_rdcfgreg_o => rdcfgreg,
multiboot_cr_cfgregadr_o => cfgregadr,
multiboot_cr_iprog_o => iprog,
multiboot_sr_cfgreg_img_i => cfgreg_img,
multiboot_sr_valid_i => sr_valid,
multiboot_gbbar_o => gbbar,
multiboot_mbbar_o => mbbar,
multiboot_far_data_i => far_data_in,
multiboot_far_data_o => far_data_out,
multiboot_far_nbytes_o => far_nbytes,
multiboot_far_xfer_o => far_xfer,
multiboot_far_cs_o => far_cs,
multiboot_far_ready_i => far_ready
);
--============================================================================
-- FSM component instantiation
--============================================================================
cmp_fsm : multiboot_fsm
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
reg_rdcfgreg_i => rdcfgreg,
reg_cfgregadr_i => cfgregadr,
reg_iprog_i => iprog,
reg_gbbar_i => gbbar,
reg_mbbar_i => mbbar,
reg_cfgreg_img_o => cfgreg_img,
reg_cfgreg_valid_o => sr_valid,
reg_far_data_i => far_data_out,
reg_far_data_o => far_data_in,
reg_far_nbytes_i => far_nbytes,
reg_far_xfer_i => far_xfer,
reg_far_cs_i => far_cs,
reg_far_ready_o => far_ready,
spi_xfer_o => spi_xfer,
spi_cs_o => spi_cs,
spi_data_i => spi_data_out,
spi_data_o => spi_data_in,
spi_ready_i => spi_ready,
icap_dat_i => fsm_icap_din,
icap_dat_o => fsm_icap_dout,
icap_busy_i => icap_busy,
icap_ce_n_o => icap_ce_n,
icap_wr_n_o => icap_wr_n
);
--============================================================================
-- Flash controller instantiation
--============================================================================
cmp_spi_master : spi_master
generic map
(
g_div_ratio_log2 => 0,
g_num_data_bits => 8
)
port map
(
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
cs_i => spi_cs,
start_i => spi_xfer,
cpol_i => '0',
data_i => spi_data_in,
data_o => spi_data_out,
ready_o => spi_ready,
spi_cs_n_o => spi_cs_n_o,
spi_sclk_o => spi_sclk_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i
);
--============================================================================
-- Xilinx ICAP logic
--============================================================================
-- First, bit-flip the data to/from the FSM
icap_din( 0) <= fsm_icap_dout( 7);
icap_din( 1) <= fsm_icap_dout( 6);
icap_din( 2) <= fsm_icap_dout( 5);
icap_din( 3) <= fsm_icap_dout( 4);
icap_din( 4) <= fsm_icap_dout( 3);
icap_din( 5) <= fsm_icap_dout( 2);
icap_din( 6) <= fsm_icap_dout( 1);
icap_din( 7) <= fsm_icap_dout( 0);
icap_din( 8) <= fsm_icap_dout(15);
icap_din( 9) <= fsm_icap_dout(14);
icap_din(10) <= fsm_icap_dout(13);
icap_din(11) <= fsm_icap_dout(12);
icap_din(12) <= fsm_icap_dout(11);
icap_din(13) <= fsm_icap_dout(10);
icap_din(14) <= fsm_icap_dout( 9);
icap_din(15) <= fsm_icap_dout( 8);
fsm_icap_din( 0) <= icap_dout( 7);
fsm_icap_din( 1) <= icap_dout( 6);
fsm_icap_din( 2) <= icap_dout( 5);
fsm_icap_din( 3) <= icap_dout( 4);
fsm_icap_din( 4) <= icap_dout( 3);
fsm_icap_din( 5) <= icap_dout( 2);
fsm_icap_din( 6) <= icap_dout( 1);
fsm_icap_din( 7) <= icap_dout( 0);
fsm_icap_din( 8) <= icap_dout(15);
fsm_icap_din( 9) <= icap_dout(14);
fsm_icap_din(10) <= icap_dout(13);
fsm_icap_din(11) <= icap_dout(12);
fsm_icap_din(12) <= icap_dout(11);
fsm_icap_din(13) <= icap_dout(10);
fsm_icap_din(14) <= icap_dout( 9);
fsm_icap_din(15) <= icap_dout( 8);
-- and instantiate the ICAP component
cmp_icap : ICAP_SPARTAN6
port map
(
CLK => clk_i,
CE => icap_ce_n,
WRITE => icap_wr_n,
I => icap_din,
O => icap_dout,
BUSY => icap_busy
);
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
syn/Release/Makefile 0 → 100644
View file @ def26966
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := conv_ttl_blo.xise
ISE_CRAP := *.b conv_ttl_blo_summary.html *.tcl conv_ttl_blo.bld conv_ttl_blo.cmd_log *.drc conv_ttl_blo.lso *.ncd conv_ttl_blo.ngc conv_ttl_blo.ngd conv_ttl_blo.ngr conv_ttl_blo.pad conv_ttl_blo.par conv_ttl_blo.pcf conv_ttl_blo.prj conv_ttl_blo.ptwx conv_ttl_blo.stx conv_ttl_blo.syr conv_ttl_blo.twr conv_ttl_blo.twx conv_ttl_blo.gise conv_ttl_blo.unroutes conv_ttl_blo.ut conv_ttl_blo.xpi conv_ttl_blo.xst conv_ttl_blo_bitgen.xwbt conv_ttl_blo_envsettings.html conv_ttl_blo_guide.ncd conv_ttl_blo_map.map conv_ttl_blo_map.mrp conv_ttl_blo_map.ncd conv_ttl_blo_map.ngm conv_ttl_blo_map.xrpt conv_ttl_blo_ngdbuild.xrpt conv_ttl_blo_pad.csv conv_ttl_blo_pad.txt conv_ttl_blo_par.xrpt conv_ttl_blo_summary.xml conv_ttl_blo_usage.xml conv_ttl_blo_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
USER:=$(HDLMAKE_USER)#take the value from the environment
SERVER:=$(HDLMAKE_SERVER)#take the value from the environment
R_NAME:=conv_ttl_blo
__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
endif
ifeq (x$(SERVER),x)
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
endif
CWD := $(shell pwd)
FILES := ../../top/Release/conv_ttl_blo.ucf \
../../top/Release/conv_ttl_blo.vhd \
../../modules/Release/conv_regs.vhd \
../../modules/ctb_pulse_gen.vhd \
../../modules/glitch_filt.vhd \
../../modules/reset_gen.vhd \
../../modules/rtm_detector.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../ip_cores/general-cores/modules/common/gc_reset.vhd \
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../../modules/vbcp_wb/i2c_slave_pkg.vhd \
../../modules/vbcp_wb/i2c_slave.vhd \
../../modules/vbcp_wb/vbcp_wb.vhd \
../../modules/xil_multiboot/spi_master.vhd \
../../modules/xil_multiboot/multiboot_fsm.vhd \
../../modules/xil_multiboot/multiboot_regs.vhd \
../../modules/xil_multiboot/xil_multiboot.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v \
run.tcl \
conv_ttl_blo.xise
#target for running simulation in the remote location
remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
__send_back:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
syn/Release/Manifest.py 0 → 100644
View file @ def26966
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "conv_ttl_blo"
syn_project = "conv_ttl_blo.xise"
modules = {
"local" : [
"../../top/Release"
]
}
syn/Release/conv_ttl_blo.xise 0 → 100644
View file @ def26966
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
<properties>
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<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
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<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
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<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
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<file xil_pn:name="../../modules/xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="111"/>
</file>
<file xil_pn:name="../../modules/xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="112"/>
</file>
<file xil_pn:name="../../modules/xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="113"/>
</file>
<file xil_pn:name="../../modules/xil_multiboot/xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="114"/>
</file>
<file xil_pn:name="../../top/Release/conv_ttl_blo.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="115"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
</project>
syn/pulsetest/Makefile 0 → 100644
View file @ def26966
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := pulsetest.xise
ISE_CRAP := *.b pulsetest_summary.html *.tcl pulsetest.bld pulsetest.cmd_log *.drc pulsetest.lso *.ncd pulsetest.ngc pulsetest.ngd pulsetest.ngr pulsetest.pad pulsetest.par pulsetest.pcf pulsetest.prj pulsetest.ptwx pulsetest.stx pulsetest.syr pulsetest.twr pulsetest.twx pulsetest.gise pulsetest.unroutes pulsetest.ut pulsetest.xpi pulsetest.xst pulsetest_bitgen.xwbt pulsetest_envsettings.html pulsetest_guide.ncd pulsetest_map.map pulsetest_map.mrp pulsetest_map.ncd pulsetest_map.ngm pulsetest_map.xrpt pulsetest_ngdbuild.xrpt pulsetest_pad.csv pulsetest_pad.txt pulsetest_par.xrpt pulsetest_summary.xml pulsetest_usage.xml pulsetest_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
USER:=$(HDLMAKE_USER)#take the value from the environment
SERVER:=$(HDLMAKE_SERVER)#take the value from the environment
R_NAME:=pulsetest
__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
endif
ifeq (x$(SERVER),x)
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
endif
CWD := $(shell pwd)
FILES := ../../top/pulsetest/pulsetest.ucf \
../../top/pulsetest/pulsetest.vhd \
../../modules/pulsetest/conv_regs.vhd \
../../modules/pulsetest/pulse_cnt_regs.vhd \
../../modules/pulsetest/pgen_ctrl_regs.vhd \
../../modules/pulsetest/pulse_gen_gp.vhd \
../../modules/ctb_pulse_gen.vhd \
../../modules/glitch_filt.vhd \
../../modules/reset_gen.vhd \
../../modules/rtm_detector.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../ip_cores/general-cores/modules/common/gc_reset.vhd \
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_async_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_handshaking_flags.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_fwft_ext_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss_fwft.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_fwft.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_logic.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_blk_ramfifo.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_ss.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_ss.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_handshaking_flags.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_dc_fwft_ext_as.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_logic.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_status_flags_sshft.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_sshft.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_sshft.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_sshft.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_sshft.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_ramfifo.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_comps_builtin.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/delay.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/clk_x_pntrs_builtin.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/bin_cntr.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/logic_builtin.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/reset_builtin.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_prim_v6.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_extdepth_v6.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/builtin_top_v6.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_builtin.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rgtw.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wgtr.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_block_fifo16_patch.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_block_fifo16_patch.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo16_patch_top.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_fifo16_patch.vhd \
../../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../../modules/vbcp_wb/i2c_slave_pkg.vhd \
../../modules/vbcp_wb/i2c_slave.vhd \
../../modules/vbcp_wb/vbcp_wb.vhd \
../../modules/xil_multiboot/spi_master.vhd \
../../modules/xil_multiboot/multiboot_fsm.vhd \
../../modules/xil_multiboot/multiboot_regs.vhd \
../../modules/xil_multiboot/xil_multiboot.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v \
run.tcl \
pulsetest.xise
#target for running simulation in the remote location
remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
__send_back:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
syn/pulsetest/Manifest.py 0 → 100644
View file @ def26966
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "pulsetest"
syn_project = "pulsetest.xise"
modules = {
"local" : [
"../../top/pulsetest"
]
}
syn/pulsetest/pulsetest.xise 0 → 100644
View file @ def26966
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|pulsetest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/pulsetest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="pulsetest" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="pulsetest_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="pulsetest_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="pulsetest_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="pulsetest_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="pulsetest" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-11-19T10:18:12" xil_pn:valueState="non-default"/>
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<libraries>
<library xil_pn:name="blk_mem_gen_v4_1"/>
<library xil_pn:name="fifo_generator_v6_1"/>
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<files>
<file xil_pn:name="../../top/pulsetest/pulsetest.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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<file xil_pn:name="../../top/pulsetest/pulsetest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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<file xil_pn:name="../../modules/pulsetest/conv_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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<file xil_pn:name="../../modules/pulsetest/pulse_cnt_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
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<file xil_pn:name="../../modules/pulsetest/pgen_ctrl_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
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<file xil_pn:name="../../modules/pulsetest/pulse_gen_gp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
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<file xil_pn:name="../../modules/ctb_pulse_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
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<file xil_pn:name="../../modules/glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
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<file xil_pn:name="../../modules/reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
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<file xil_pn:name="../../modules/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd" xil_pn:type="FILE_VHDL">
<library xil_pn:name="blk_mem_gen_v4_1"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="144"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="145"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="146"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="147"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="148"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="149"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="150"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="151"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="152"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="153"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="154"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="155"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="156"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="157"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="158"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="159"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="160"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="161"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="162"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="163"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="164"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="165"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="169"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="170"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="171"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="172"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="173"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="174"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="175"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="176"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="177"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="178"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="179"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="180"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="181"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="182"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="183"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="184"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="185"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="186"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="187"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="188"/>
</file>
<file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="189"/>
</file>
<file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="190"/>
</file>
<file xil_pn:name="../../modules/vbcp_wb/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="191"/>
</file>
<file xil_pn:name="../../modules/vbcp_wb/i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="192"/>
</file>
<file xil_pn:name="../../modules/vbcp_wb/vbcp_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="193"/>
</file>
<file xil_pn:name="../../modules/xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="194"/>
</file>
<file xil_pn:name="../../modules/xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
</file>
<file xil_pn:name="../../modules/xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
</file>
<file xil_pn:name="../../modules/xil_multiboot/xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
</project>
syn/regtest/Makefile 0 → 100644
View file @ def26966
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := regtest.xise
ISE_CRAP := *.b regtest_summary.html *.tcl regtest.bld regtest.cmd_log *.drc regtest.lso *.ncd regtest.ngc regtest.ngd regtest.ngr regtest.pad regtest.par regtest.pcf regtest.prj regtest.ptwx regtest.stx regtest.syr regtest.twr regtest.twx regtest.gise regtest.unroutes regtest.ut regtest.xpi regtest.xst regtest_bitgen.xwbt regtest_envsettings.html regtest_guide.ncd regtest_map.map regtest_map.mrp regtest_map.ncd regtest_map.ngm regtest_map.xrpt regtest_ngdbuild.xrpt regtest_pad.csv regtest_pad.txt regtest_par.xrpt regtest_summary.xml regtest_usage.xml regtest_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
USER:=$(HDLMAKE_USER)#take the value from the environment
SERVER:=$(HDLMAKE_SERVER)#take the value from the environment
R_NAME:=regtest
__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
endif
ifeq (x$(SERVER),x)
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
endif
CWD := $(shell pwd)
FILES := ../../top/regtest/regtest.ucf \
../../top/regtest/regtest.vhd \
../../modules/ctb_pulse_gen.vhd \
../../modules/glitch_filt.vhd \
../../modules/reset_gen.vhd \
../../modules/rtm_detector.vhd \
../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../ip_cores/general-cores/modules/common/gc_reset.vhd \
../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../../modules/vbcp_wb/i2c_slave_pkg.vhd \
../../modules/vbcp_wb/i2c_slave.vhd \
../../modules/vbcp_wb/vbcp_wb.vhd \
../../modules/xil_multiboot/spi_master.vhd \
../../modules/xil_multiboot/multiboot_fsm.vhd \
../../modules/xil_multiboot/multiboot_regs.vhd \
../../modules/xil_multiboot/xil_multiboot.vhd \
../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v \
../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v \
run.tcl \
regtest.xise
#target for running simulation in the remote location
remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
__send_back:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
syn/regtest/Manifest.py 0 → 100644
View file @ def26966
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "regtest"
syn_project = "regtest.xise"
modules = {
"local" : [
"../../top/regtest"
]
}
syn/regtest/regtest.xise 0 → 100644
View file @ def26966
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
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<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
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<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
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<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
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<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="regtest" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/>
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<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="regtest_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="regtest_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="regtest_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="regtest_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
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</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" xil_pn:type="FILE_VHDL">
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</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="75"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="78"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="79"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="90"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="92"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file>
<file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="105"/>
</file>
<file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="106"/>
</file>
<file xil_pn:name="../../modules/vbcp_wb/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="107"/>
</file>
<file xil_pn:name="../../modules/vbcp_wb/i2c_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="108"/>
</file>
<file xil_pn:name="../../modules/vbcp_wb/vbcp_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="109"/>
</file>
<file xil_pn:name="../../modules/xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="110"/>
</file>
<file xil_pn:name="../../modules/xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="111"/>
</file>
<file xil_pn:name="../../modules/xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="112"/>
</file>
<file xil_pn:name="../../modules/xil_multiboot/xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="113"/>
</file>
<file xil_pn:name="../../top/regtest/regtest.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="114"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>
</project>
top/Release/Manifest.py
View file @ def26966
......@@ -6,13 +6,7 @@ files = [
modules = {
"local" : [
"../../ip_cores/general-cores",
"../../reset_gen",
"../rtl",
"../../vbcp_wb",
"../../ctb_pulse_gen",
"../../multiboot/",
"../../rtm_detector",
"../../bicolor_led_ctrl",
"../../../../../ip_cores/general-cores"
"../../modules/Release",
"../../modules"
]
}
top/pulsetest/Manifest.py
View file @ def26966
......@@ -5,16 +5,8 @@ files = [
modules = {
"local" : [
"../../reset_gen",
"../../bicolor_led_ctrl",
"../../vbcp_wb",
"../../pulse_gen_gp",
"../../multiboot",
"../rtl"
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git"
"../../ip_cores/general-cores",
"../../modules/pulsetest",
"../../modules"
]
}
fetchto = "../../../../../ip_cores"
top/regtest/Manifest.py
View file @ def26966
......@@ -6,8 +6,6 @@ files = [
modules = {
"local" : [
"../../ip_cores/general-cores",
"../../reset_gen",
"../../bicolor_led_ctrl",
"../../vbcp_wb"
"../../modules/"
],
}
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