Commit def26966 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

New folder structure

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 5cbef60e
general-cores @ fec74c4d
Subproject commit fec74c4d983ee96a985a05d3384f467ec97376ce
modules = {
"local" : [
# pulsetest module added from pulsetest syn folder
# Release module added from Release syn folder
"bicolor_led_ctrl",
"vbcp_wb",
"xil_multiboot"
]
}
files = [
"ctb_pulse_gen.vhd",
"glitch_filt.vhd",
"reset_gen.vhd",
"rtm_detector.vhd"
]
files = [
"conv_regs.vhd"
];
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Converter board registers
---------------------------------------------------------------------------------------
-- File : conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created : Fri Aug 2 16:02:13 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID register'
conv_regs_id_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'fwvers' in reg: 'Status register'
conv_regs_sr_fwvers_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'switches' in reg: 'Status register'
conv_regs_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status register'
conv_regs_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Port for BIT field: 'Reset unlock bit' in reg: 'Control register'
conv_regs_cr_rst_unlock_o : out std_logic;
-- Port for BIT field: 'Reset bit' in reg: 'Control register'
conv_regs_cr_rst_o : out std_logic
);
end conv_regs;
architecture syn of conv_regs is
signal conv_regs_id_bits_int : std_logic_vector(31 downto 0);
signal conv_regs_cr_rst_unlock_int : std_logic ;
signal conv_regs_cr_rst_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
conv_regs_id_bits_int <= x"424c4f32";
conv_regs_cr_rst_unlock_int <= '0';
conv_regs_cr_rst_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
conv_regs_id_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= conv_regs_id_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= conv_regs_sr_fwvers_i;
rddata_reg(23 downto 16) <= conv_regs_sr_switches_i;
rddata_reg(29 downto 24) <= conv_regs_sr_rtm_i;
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
conv_regs_cr_rst_unlock_int <= wrdata_reg(0);
conv_regs_cr_rst_int <= wrdata_reg(1);
end if;
rddata_reg(0) <= conv_regs_cr_rst_unlock_int;
if (conv_regs_cr_rst_unlock_int = '1') then
rddata_reg(1) <= conv_regs_cr_rst_int;
end if;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- bits
conv_regs_id_bits_o <= conv_regs_id_bits_int;
-- fwvers
-- switches
-- RTM detection
-- Reset unlock bit
conv_regs_cr_rst_unlock_o <= conv_regs_cr_rst_unlock_int;
-- Reset bit
conv_regs_cr_rst_o <= conv_regs_cr_rst_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
peripheral {
name = "Converter board registers";
hdl_entity = "conv_regs";
prefix = "conv_regs";
reg {
name = "Board ID register";
description = "Bits of ID register, defaulting to ASCII string of BLO2";
prefix = "id";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "Status register";
description = "Contains fields for firmware version, switches, RTM detection lines";
prefix = "sr";
field {
name = "fwvers";
prefix = "fwvers";
type = SLV;
size = 16;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "switches";
prefix = "switches";
type = SLV;
size = 8;
align = 16;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "RTM detection";
prefix = "rtm";
type = SLV;
size = 6;
align = 24;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "Control register";
description = "Contains bits that control operation of the converter modules";
prefix = "cr";
-- field {
-- name = "blocking chan 1 enable";
-- prefix = "bch1_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 2 enable";
-- prefix = "bch2_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 3 enable";
-- prefix = "bch3_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 4 enable";
-- prefix = "bch4_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 5 enable";
-- prefix = "bch5_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 6 enable";
-- prefix = "bch6_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
field {
name = "Reset unlock bit";
prefix = "rst_unlock";
description = "1 - unlock reset bit\
0 - lock reset bit";
type = BIT;
align = 30;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reset bit";
prefix = "rst";
description = "1 - initiate logic reset\
0 - no reset";
type = BIT;
align = 31;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
files = [
"bicolor_led_ctrl_pkg.vhd",
"bicolor_led_ctrl.vhd"
]
Taken from:
http://www.ohwr.org/projects/svec/repository/revisions/master/show/hdl/top/bicolor_led_test
Revision: 220c7837
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Bi-color LED controller
-- http://www.ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: bicolor_led_ctrl
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 11-07-2012
--
-- version: 1.0
--
-- description: Bi-color LED controller. It controls a matrix of bi-color LED.
-- The FPGA ouputs for the columns (C) are connected to buffers
-- and serial resistances and then to the LEDs. The FPGA outputs
-- for lines (L) are connected to tri-state buffers and the to
-- the LEDs. The FPGA outputs for lines output enable (L_OEN) are
-- connected to the output enable of the tri-state buffers.
--
-- Example with three lines and two columns:
--
-- |<refresh period>|
--
-- L1/L2/L3 __|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__
--
-- L1_OEN -----|___________|-----|___________|-----|___________|-----|___________|--
--
-- L2_OEN _____|-----|___________|-----|___________|-----|___________|-----|________
--
-- L3_OEN ___________|-----|___________|-----|___________|-----|___________|-----|__
--
-- Cn __|--|__|--|__|--|_________________|-----------------|--|__|--|__|--|__|--
--
-- LED Ln/Cn OFF | color_1 | color_2 | both_colors |
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.bicolor_led_ctrl_pkg.all;
entity bicolor_led_ctrl is
generic(
g_NB_COLUMN : natural := 4;
g_NB_LINE : natural := 2;
g_CLK_FREQ : natural := 125000000; -- in Hz
g_REFRESH_RATE : natural := 250 -- in Hz
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
led_intensity_i : in std_logic_vector(6 downto 0);
led_state_i : in std_logic_vector((g_NB_LINE * g_NB_COLUMN * 2) - 1 downto 0);
column_o : out std_logic_vector(g_NB_COLUMN - 1 downto 0);
line_o : out std_logic_vector(g_NB_LINE - 1 downto 0);
line_oen_o : out std_logic_vector(g_NB_LINE - 1 downto 0)
);
end bicolor_led_ctrl;
architecture rtl of bicolor_led_ctrl is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_REFRESH_CNT_INIT : natural := natural(g_CLK_FREQ/(2 * g_NB_LINE * g_REFRESH_RATE)) - 1;
constant c_REFRESH_CNT_NB_BITS : natural := log2_ceil(c_REFRESH_CNT_INIT);
constant c_LINE_OEN_CNT_NB_BITS : natural := log2_ceil(g_NB_LINE);
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal refresh_rate_cnt : unsigned(c_REFRESH_CNT_NB_BITS - 1 downto 0);
signal refresh_rate : std_logic;
signal line_ctrl : std_logic;
signal intensity_ctrl_cnt : unsigned(c_REFRESH_CNT_NB_BITS - 1 downto 0);
signal intensity_ctrl : std_logic;
signal line_oen_cnt : unsigned(c_LINE_OEN_CNT_NB_BITS - 1 downto 0);
signal line_oen : std_logic_vector(2**c_LINE_OEN_CNT_NB_BITS - 1 downto 0);
signal led_state : std_logic_vector((g_NB_LINE * g_NB_COLUMN) -1 downto 0);
begin
------------------------------------------------------------------------------
-- Refresh rate counter
------------------------------------------------------------------------------
p_refresh_rate_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
refresh_rate_cnt <= (others => '0');
refresh_rate <= '0';
elsif refresh_rate_cnt = 0 then
refresh_rate_cnt <= to_unsigned(c_REFRESH_CNT_INIT, c_REFRESH_CNT_NB_BITS);
refresh_rate <= '1';
else
refresh_rate_cnt <= refresh_rate_cnt - 1;
refresh_rate <= '0';
end if;
end if;
end process p_refresh_rate_cnt;
------------------------------------------------------------------------------
-- Intensity control
------------------------------------------------------------------------------
p_intensity_ctrl_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
intensity_ctrl_cnt <= (others => '0');
elsif refresh_rate = '1' then
intensity_ctrl_cnt <= to_unsigned(natural(c_REFRESH_CNT_INIT/100) * to_integer(unsigned(led_intensity_i)), c_REFRESH_CNT_NB_BITS);
else
intensity_ctrl_cnt <= intensity_ctrl_cnt - 1;
end if;
end if;
end process p_intensity_ctrl_cnt;
p_intensity_ctrl : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
intensity_ctrl <= '0';
elsif refresh_rate = '1' then
intensity_ctrl <= '1';
elsif intensity_ctrl_cnt = 0 then
intensity_ctrl <= '0';
end if;
end if;
end process p_intensity_ctrl;
------------------------------------------------------------------------------
-- Lines ouput
------------------------------------------------------------------------------
p_line_ctrl : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
line_ctrl <= '0';
elsif refresh_rate = '1' then
line_ctrl <= not(line_ctrl);
end if;
end if;
end process p_line_ctrl;
f_line_o : for I in 0 to g_NB_LINE - 1 generate
line_o(I) <= line_ctrl and intensity_ctrl;
end generate f_line_o;
------------------------------------------------------------------------------
-- Lines output enable
------------------------------------------------------------------------------
p_line_oen_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
line_oen_cnt <= (others => '0');
elsif line_ctrl = '1' and refresh_rate = '1' then
if line_oen_cnt = 0 then
line_oen_cnt <= to_unsigned(g_NB_LINE - 1, c_LINE_OEN_CNT_NB_BITS);
else
line_oen_cnt <= line_oen_cnt - 1;
end if;
end if;
end if;
end process p_line_oen_cnt;
p_line_oen_decode : process(line_oen_cnt)
variable v_onehot : std_logic_vector((2**line_oen_cnt'length)-1 downto 0);
variable v_index : integer range 0 to (2**line_oen_cnt'length)-1;
begin
v_onehot := (others => '0');
v_index := 0;
for i in line_oen_cnt'range loop
if (line_oen_cnt(i) = '1') then
v_index := 2*v_index+1;
else
v_index := 2*v_index;
end if;
end loop;
v_onehot(v_index) := '1';
line_oen <= v_onehot;
end process p_line_oen_decode;
line_oen_o <= line_oen(line_oen_o'left downto 0);
------------------------------------------------------------------------------
-- Columns output
------------------------------------------------------------------------------
f_led_state : for I in 0 to (g_NB_COLUMN * g_NB_LINE) - 1 generate
led_state(I) <= '0' when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED else
'1' when led_state_i(2 * I + 1 downto 2 * I) = c_LED_GREEN else
not(line_ctrl and intensity_ctrl) when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED_GREEN else
(line_ctrl and intensity_ctrl);-- when led_state_i(2 * I + 1 downto 2 * I) = c_LED_OFF else
end generate f_led_state;
f_column_o : for C in 0 to g_NB_COLUMN - 1 generate
column_o(C) <= led_state(g_NB_COLUMN * to_integer(line_oen_cnt) + C);
end generate f_column_o;
end rtl;
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Bi-color LED controller package
-- http://www.ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: bicolor_led_ctrl_pkg
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 11-07-2012
--
-- version: 1.0
--
-- description: Package for Bi-color LED controller.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package bicolor_led_ctrl_pkg is
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_LED_RED : std_logic_vector(1 downto 0) := "10";
constant c_LED_GREEN : std_logic_vector(1 downto 0) := "01";
constant c_LED_RED_GREEN : std_logic_vector(1 downto 0) := "11";
constant c_LED_OFF : std_logic_vector(1 downto 0) := "00";
------------------------------------------------------------------------------
-- Functions declaration
------------------------------------------------------------------------------
function log2_ceil(N : natural) return positive;
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component bicolor_led_ctrl
generic(
g_NB_COLUMN : natural := 4;
g_NB_LINE : natural := 2;
g_CLK_FREQ : natural := 125000000; -- in Hz
g_REFRESH_RATE : natural := 250 -- in Hz
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
led_intensity_i : in std_logic_vector(6 downto 0);
led_state_i : in std_logic_vector((g_NB_LINE * g_NB_COLUMN * 2) - 1 downto 0);
column_o : out std_logic_vector(g_NB_COLUMN - 1 downto 0);
line_o : out std_logic_vector(g_NB_LINE - 1 downto 0);
line_oen_o : out std_logic_vector(g_NB_LINE - 1 downto 0)
);
end component;
end bicolor_led_ctrl_pkg;
package body bicolor_led_ctrl_pkg is
------------------------------------------------------------------------------
-- Function : Returns log of 2 of a natural number
------------------------------------------------------------------------------
function log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end;
end bicolor_led_ctrl_pkg;
This diff is collapsed.
--==============================================================================
-- CERN (BE-CO-HT)
-- Glitch filter with selectable length
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-03-12
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-03-12 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;