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Conv TTL Blocking - Gateware
Commit def26966 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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New folder structure 

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 5cbef60e
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general-cores @ fec74c4d
Subproject commit fec74c4d983ee96a985a05d3384f467ec97376ce
modules/Manifest.py 0 → 100644
View file @ def26966
modules = {
"local" : [
# pulsetest module added from pulsetest syn folder
# Release module added from Release syn folder
"bicolor_led_ctrl",
"vbcp_wb",
"xil_multiboot"
]
}
files = [
"ctb_pulse_gen.vhd",
"glitch_filt.vhd",
"reset_gen.vhd",
"rtm_detector.vhd"
]
modules/Release/Manifest.py 0 → 100644
View file @ def26966
files = [
"conv_regs.vhd"
];
modules/Release/conv_regs.vhd 0 → 100644
View file @ def26966
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Converter board registers
---------------------------------------------------------------------------------------
-- File : conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created : Fri Aug 2 16:02:13 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID register'
conv_regs_id_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'fwvers' in reg: 'Status register'
conv_regs_sr_fwvers_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'switches' in reg: 'Status register'
conv_regs_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status register'
conv_regs_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Port for BIT field: 'Reset unlock bit' in reg: 'Control register'
conv_regs_cr_rst_unlock_o : out std_logic;
-- Port for BIT field: 'Reset bit' in reg: 'Control register'
conv_regs_cr_rst_o : out std_logic
);
end conv_regs;
architecture syn of conv_regs is
signal conv_regs_id_bits_int : std_logic_vector(31 downto 0);
signal conv_regs_cr_rst_unlock_int : std_logic ;
signal conv_regs_cr_rst_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
conv_regs_id_bits_int <= x"424c4f32";
conv_regs_cr_rst_unlock_int <= '0';
conv_regs_cr_rst_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
conv_regs_id_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= conv_regs_id_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= conv_regs_sr_fwvers_i;
rddata_reg(23 downto 16) <= conv_regs_sr_switches_i;
rddata_reg(29 downto 24) <= conv_regs_sr_rtm_i;
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
conv_regs_cr_rst_unlock_int <= wrdata_reg(0);
conv_regs_cr_rst_int <= wrdata_reg(1);
end if;
rddata_reg(0) <= conv_regs_cr_rst_unlock_int;
if (conv_regs_cr_rst_unlock_int = '1') then
rddata_reg(1) <= conv_regs_cr_rst_int;
end if;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- bits
conv_regs_id_bits_o <= conv_regs_id_bits_int;
-- fwvers
-- switches
-- RTM detection
-- Reset unlock bit
conv_regs_cr_rst_unlock_o <= conv_regs_cr_rst_unlock_int;
-- Reset bit
conv_regs_cr_rst_o <= conv_regs_cr_rst_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
modules/Release/conv_regs.wb 0 → 100644
View file @ def26966
peripheral {
name = "Converter board registers";
hdl_entity = "conv_regs";
prefix = "conv_regs";
reg {
name = "Board ID register";
description = "Bits of ID register, defaulting to ASCII string of BLO2";
prefix = "id";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "Status register";
description = "Contains fields for firmware version, switches, RTM detection lines";
prefix = "sr";
field {
name = "fwvers";
prefix = "fwvers";
type = SLV;
size = 16;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "switches";
prefix = "switches";
type = SLV;
size = 8;
align = 16;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "RTM detection";
prefix = "rtm";
type = SLV;
size = 6;
align = 24;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
reg {
name = "Control register";
description = "Contains bits that control operation of the converter modules";
prefix = "cr";
-- field {
-- name = "blocking chan 1 enable";
-- prefix = "bch1_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 2 enable";
-- prefix = "bch2_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 3 enable";
-- prefix = "bch3_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 4 enable";
-- prefix = "bch4_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 5 enable";
-- prefix = "bch5_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
-- field {
-- name = "blocking chan 6 enable";
-- prefix = "bch6_en";
-- type = BIT;
-- access_bus = READ_WRITE;
-- access_dev = READ_ONLY;
-- };
field {
name = "Reset unlock bit";
prefix = "rst_unlock";
description = "1 - unlock reset bit\
0 - lock reset bit";
type = BIT;
align = 30;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reset bit";
prefix = "rst";
description = "1 - initiate logic reset\
0 - no reset";
type = BIT;
align = 31;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
modules/bicolor_led_ctrl/Manifest.py 0 → 100644
View file @ def26966
files = [
"bicolor_led_ctrl_pkg.vhd",
"bicolor_led_ctrl.vhd"
]
modules/bicolor_led_ctrl/README 0 → 100644
View file @ def26966
Taken from:
http://www.ohwr.org/projects/svec/repository/revisions/master/show/hdl/top/bicolor_led_test
Revision: 220c7837
modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd 0 → 100644
View file @ def26966
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Bi-color LED controller
-- http://www.ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: bicolor_led_ctrl
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 11-07-2012
--
-- version: 1.0
--
-- description: Bi-color LED controller. It controls a matrix of bi-color LED.
-- The FPGA ouputs for the columns (C) are connected to buffers
-- and serial resistances and then to the LEDs. The FPGA outputs
-- for lines (L) are connected to tri-state buffers and the to
-- the LEDs. The FPGA outputs for lines output enable (L_OEN) are
-- connected to the output enable of the tri-state buffers.
--
-- Example with three lines and two columns:
--
-- |<refresh period>|
--
-- L1/L2/L3 __|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__|--|__
--
-- L1_OEN -----|___________|-----|___________|-----|___________|-----|___________|--
--
-- L2_OEN _____|-----|___________|-----|___________|-----|___________|-----|________
--
-- L3_OEN ___________|-----|___________|-----|___________|-----|___________|-----|__
--
-- Cn __|--|__|--|__|--|_________________|-----------------|--|__|--|__|--|__|--
--
-- LED Ln/Cn OFF | color_1 | color_2 | both_colors |
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.bicolor_led_ctrl_pkg.all;
entity bicolor_led_ctrl is
generic(
g_NB_COLUMN : natural := 4;
g_NB_LINE : natural := 2;
g_CLK_FREQ : natural := 125000000; -- in Hz
g_REFRESH_RATE : natural := 250 -- in Hz
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
led_intensity_i : in std_logic_vector(6 downto 0);
led_state_i : in std_logic_vector((g_NB_LINE * g_NB_COLUMN * 2) - 1 downto 0);
column_o : out std_logic_vector(g_NB_COLUMN - 1 downto 0);
line_o : out std_logic_vector(g_NB_LINE - 1 downto 0);
line_oen_o : out std_logic_vector(g_NB_LINE - 1 downto 0)
);
end bicolor_led_ctrl;
architecture rtl of bicolor_led_ctrl is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_REFRESH_CNT_INIT : natural := natural(g_CLK_FREQ/(2 * g_NB_LINE * g_REFRESH_RATE)) - 1;
constant c_REFRESH_CNT_NB_BITS : natural := log2_ceil(c_REFRESH_CNT_INIT);
constant c_LINE_OEN_CNT_NB_BITS : natural := log2_ceil(g_NB_LINE);
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal refresh_rate_cnt : unsigned(c_REFRESH_CNT_NB_BITS - 1 downto 0);
signal refresh_rate : std_logic;
signal line_ctrl : std_logic;
signal intensity_ctrl_cnt : unsigned(c_REFRESH_CNT_NB_BITS - 1 downto 0);
signal intensity_ctrl : std_logic;
signal line_oen_cnt : unsigned(c_LINE_OEN_CNT_NB_BITS - 1 downto 0);
signal line_oen : std_logic_vector(2**c_LINE_OEN_CNT_NB_BITS - 1 downto 0);
signal led_state : std_logic_vector((g_NB_LINE * g_NB_COLUMN) -1 downto 0);
begin
------------------------------------------------------------------------------
-- Refresh rate counter
------------------------------------------------------------------------------
p_refresh_rate_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
refresh_rate_cnt <= (others => '0');
refresh_rate <= '0';
elsif refresh_rate_cnt = 0 then
refresh_rate_cnt <= to_unsigned(c_REFRESH_CNT_INIT, c_REFRESH_CNT_NB_BITS);
refresh_rate <= '1';
else
refresh_rate_cnt <= refresh_rate_cnt - 1;
refresh_rate <= '0';
end if;
end if;
end process p_refresh_rate_cnt;
------------------------------------------------------------------------------
-- Intensity control
------------------------------------------------------------------------------
p_intensity_ctrl_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
intensity_ctrl_cnt <= (others => '0');
elsif refresh_rate = '1' then
intensity_ctrl_cnt <= to_unsigned(natural(c_REFRESH_CNT_INIT/100) * to_integer(unsigned(led_intensity_i)), c_REFRESH_CNT_NB_BITS);
else
intensity_ctrl_cnt <= intensity_ctrl_cnt - 1;
end if;
end if;
end process p_intensity_ctrl_cnt;
p_intensity_ctrl : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
intensity_ctrl <= '0';
elsif refresh_rate = '1' then
intensity_ctrl <= '1';
elsif intensity_ctrl_cnt = 0 then
intensity_ctrl <= '0';
end if;
end if;
end process p_intensity_ctrl;
------------------------------------------------------------------------------
-- Lines ouput
------------------------------------------------------------------------------
p_line_ctrl : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
line_ctrl <= '0';
elsif refresh_rate = '1' then
line_ctrl <= not(line_ctrl);
end if;
end if;
end process p_line_ctrl;
f_line_o : for I in 0 to g_NB_LINE - 1 generate
line_o(I) <= line_ctrl and intensity_ctrl;
end generate f_line_o;
------------------------------------------------------------------------------
-- Lines output enable
------------------------------------------------------------------------------
p_line_oen_cnt : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
line_oen_cnt <= (others => '0');
elsif line_ctrl = '1' and refresh_rate = '1' then
if line_oen_cnt = 0 then
line_oen_cnt <= to_unsigned(g_NB_LINE - 1, c_LINE_OEN_CNT_NB_BITS);
else
line_oen_cnt <= line_oen_cnt - 1;
end if;
end if;
end if;
end process p_line_oen_cnt;
p_line_oen_decode : process(line_oen_cnt)
variable v_onehot : std_logic_vector((2**line_oen_cnt'length)-1 downto 0);
variable v_index : integer range 0 to (2**line_oen_cnt'length)-1;
begin
v_onehot := (others => '0');
v_index := 0;
for i in line_oen_cnt'range loop
if (line_oen_cnt(i) = '1') then
v_index := 2*v_index+1;
else
v_index := 2*v_index;
end if;
end loop;
v_onehot(v_index) := '1';
line_oen <= v_onehot;
end process p_line_oen_decode;
line_oen_o <= line_oen(line_oen_o'left downto 0);
------------------------------------------------------------------------------
-- Columns output
------------------------------------------------------------------------------
f_led_state : for I in 0 to (g_NB_COLUMN * g_NB_LINE) - 1 generate
led_state(I) <= '0' when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED else
'1' when led_state_i(2 * I + 1 downto 2 * I) = c_LED_GREEN else
not(line_ctrl and intensity_ctrl) when led_state_i(2 * I + 1 downto 2 * I) = c_LED_RED_GREEN else
(line_ctrl and intensity_ctrl);-- when led_state_i(2 * I + 1 downto 2 * I) = c_LED_OFF else
end generate f_led_state;
f_column_o : for C in 0 to g_NB_COLUMN - 1 generate
column_o(C) <= led_state(g_NB_COLUMN * to_integer(line_oen_cnt) + C);
end generate f_column_o;
end rtl;
modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd 0 → 100644
View file @ def26966
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Bi-color LED controller package
-- http://www.ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: bicolor_led_ctrl_pkg
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 11-07-2012
--
-- version: 1.0
--
-- description: Package for Bi-color LED controller.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
package bicolor_led_ctrl_pkg is
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_LED_RED : std_logic_vector(1 downto 0) := "10";
constant c_LED_GREEN : std_logic_vector(1 downto 0) := "01";
constant c_LED_RED_GREEN : std_logic_vector(1 downto 0) := "11";
constant c_LED_OFF : std_logic_vector(1 downto 0) := "00";
------------------------------------------------------------------------------
-- Functions declaration
------------------------------------------------------------------------------
function log2_ceil(N : natural) return positive;
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component bicolor_led_ctrl
generic(
g_NB_COLUMN : natural := 4;
g_NB_LINE : natural := 2;
g_CLK_FREQ : natural := 125000000; -- in Hz
g_REFRESH_RATE : natural := 250 -- in Hz
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic;
led_intensity_i : in std_logic_vector(6 downto 0);
led_state_i : in std_logic_vector((g_NB_LINE * g_NB_COLUMN * 2) - 1 downto 0);
column_o : out std_logic_vector(g_NB_COLUMN - 1 downto 0);
line_o : out std_logic_vector(g_NB_LINE - 1 downto 0);
line_oen_o : out std_logic_vector(g_NB_LINE - 1 downto 0)
);
end component;
end bicolor_led_ctrl_pkg;
package body bicolor_led_ctrl_pkg is
------------------------------------------------------------------------------
-- Function : Returns log of 2 of a natural number
------------------------------------------------------------------------------
function log2_ceil(N : natural) return positive is
begin
if N <= 2 then
return 1;
elsif N mod 2 = 0 then
return 1 + log2_ceil(N/2);
else
return 1 + log2_ceil((N+1)/2);
end if;
end;
end bicolor_led_ctrl_pkg;
modules/ctb_pulse_gen.vhd 0 → 100644
View file @ def26966
This diff is collapsed.
modules/glitch_filt.vhd 0 → 100644
View file @ def26966
--==============================================================================
-- CERN (BE-CO-HT)
-- Glitch filter with selectable length
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-03-12
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-03-12 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity glitch_filt is
generic
(
-- Length of glitch filter:
-- g_len = 1 => data width should be > 1 clk_i cycle
-- g_len = 2 => data width should be > 2 clk_i cycle
-- etc.
g_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Data input
dat_i : in std_logic;
-- Data output
-- latency: g_len+1 clk_i cycles
dat_o : out std_logic
);
end entity glitch_filt;
architecture behav of glitch_filt is
--============================================================================
-- Component declarations
--============================================================================
component gc_sync_ffs is
generic(
g_sync_edge : string := "positive"
);
port(
clk_i : in std_logic; -- clock from the destination clock domain
rst_n_i : in std_logic; -- reset
data_i : in std_logic; -- async input
synced_o : out std_logic; -- synchronized output
npulse_o : out std_logic; -- negative edge detect output (single-clock
-- pulse)
ppulse_o : out std_logic -- positive edge detect output (single-clock
-- pulse)
);
end component gc_sync_ffs;
--============================================================================
-- Signal declarations
--============================================================================
signal glitch_filt : std_logic_vector(g_len downto 0);
signal dat_synced : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Glitch filtration logic
--============================================================================
-- First, synchronize the data input in the clk_i domain
cmp_sync : gc_sync_ffs
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => dat_i,
synced_o => dat_synced,
npulse_o => open,
ppulse_o => open
);
-- Then, assign the current sample of the glitch filter
glitch_filt(0) <= dat_synced;
-- Generate glitch filter FFs when the filter length is > 0
gen_glitch_filt: if (g_len > 0) generate
p_glitch_filt: process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
glitch_filt(g_len downto 1) <= (others => '0');
else
glitch_filt(g_len downto 1) <= glitch_filt(g_len-1 downto 0);
end if;
end if;
end process p_glitch_filt;
end generate gen_glitch_filt;
-- and set the data output based on the state of the glitch filter
p_output: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
dat_o <= '0';
elsif (glitch_filt = (glitch_filt'range => '1')) then
dat_o <= '1';
elsif (glitch_filt = (glitch_filt'range => '0')) then
dat_o <= '0';
end if;
end if;
end process p_output;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
modules/pulsetest/Manifest.py 0 → 100644
View file @ def26966
files = [
"conv_regs.vhd",
"pulse_cnt_regs.vhd",
"pgen_ctrl_regs.vhd",
"pulse_gen_gp.vhd"
]
modules/pulsetest/conv_regs.vhd 0 → 100644
View file @ def26966
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Converter board registers
---------------------------------------------------------------------------------------
-- File : conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created : Fri Aug 2 16:02:13 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity conv_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID register'
conv_regs_id_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'fwvers' in reg: 'Status register'
conv_regs_sr_fwvers_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'switches' in reg: 'Status register'
conv_regs_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status register'
conv_regs_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Port for BIT field: 'Reset unlock bit' in reg: 'Control register'
conv_regs_cr_rst_unlock_o : out std_logic;
-- Port for BIT field: 'Reset bit' in reg: 'Control register'
conv_regs_cr_rst_o : out std_logic
);
end conv_regs;
architecture syn of conv_regs is
signal conv_regs_id_bits_int : std_logic_vector(31 downto 0);
signal conv_regs_cr_rst_unlock_int : std_logic ;
signal conv_regs_cr_rst_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
conv_regs_id_bits_int <= x"424c4f32";
conv_regs_cr_rst_unlock_int <= '0';
conv_regs_cr_rst_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
conv_regs_id_bits_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= conv_regs_id_bits_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= conv_regs_sr_fwvers_i;
rddata_reg(23 downto 16) <= conv_regs_sr_switches_i;
rddata_reg(29 downto 24) <= conv_regs_sr_rtm_i;
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
conv_regs_cr_rst_unlock_int <= wrdata_reg(0);
conv_regs_cr_rst_int <= wrdata_reg(31);
end if;
rddata_reg(0) <= conv_regs_cr_rst_unlock_int;
rddata_reg(31) <= conv_regs_cr_rst_int;
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- bits
conv_regs_id_bits_o <= conv_regs_id_bits_int;
-- fwvers
-- switches
-- RTM detection
-- Reset unlock bit
conv_regs_cr_rst_unlock_o <= conv_regs_cr_rst_unlock_int;
-- Reset bit
conv_regs_cr_rst_o <= conv_regs_cr_rst_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
modules/pulsetest/pgen_ctrl_regs.vhd 0 → 100644
View file @ def26966
This diff is collapsed.
modules/pulsetest/pgen_ctrl_regs.wb 0 → 100644
View file @ def26966
peripheral {
name = "Pulse generation control registers";
description = "Registers containing control signals for the general-purpose pulse generator blocks";
hdl_entity = "pgen_ctrl_regs";
prefix = "pgen_ctrl_regs";
reg {
name = "Enable register";
prefix = "en";
field {
name = "channel enable";
prefix = "ch";
type = SLV;
size = 6;
};
};
reg {
name = "CH1 delay register";
prefix = "ch1_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH2 delay register";
prefix = "ch2_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH3 delay register";
prefix = "ch3_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH4 delay register";
prefix = "ch4_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH5 delay register";
prefix = "ch5_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH6 delay register";
prefix = "ch6_delay";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH1 pulse width register";
prefix = "ch1_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH2 pulse width register";
prefix = "ch2_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH3 pulse width register";
prefix = "ch3_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH4 pulse width register";
prefix = "ch4_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH5 pulse width register";
prefix = "ch5_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH6 pulse width register";
prefix = "ch6_pwidth";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH1 frequency register";
prefix = "ch1_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH2 frequency register";
prefix = "ch2_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH3 frequency register";
prefix = "ch3_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH4 frequency register";
prefix = "ch4_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH5 frequency register";
prefix = "ch5_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
reg {
name = "CH6 frequency register";
prefix = "ch6_freq";
field {
name = "bits";
prefix = "bits";
type = SLV;
size = 32;
};
};
};
modules/pulsetest/pulse_cnt_regs.vhd 0 → 100644
View file @ def26966
This diff is collapsed.
modules/pulsetest/pulse_cnt_regs.wb 0 → 100644
View file @ def26966
peripheral {
name = "Pulse counter registers";
description = "Registers containing the values for input and output generated pulses";
hdl_entity = "pulse_cnt_regs";
prefix = "pulse_cnt";
reg {
name = "CH1 input";
prefix = "ch1i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH1 output";
prefix = "ch1o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH2 input";
prefix = "ch2i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH2 output";
prefix = "ch2o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH3 input";
prefix = "ch3i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH3 output";
prefix = "ch3o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH4 input";
prefix = "ch4i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH4 output";
prefix = "ch4o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH5 input";
prefix = "ch5i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH5 output";
prefix = "ch5o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH6 input";
prefix = "ch6i";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "CH6 output";
prefix = "ch6o";
field {
name = "number of pulses";
prefix = "val";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Counter reset";
prefix = "rst";
field {
name = "reset";
prefix = "bit";
type = BIT;
};
};
};
modules/pulsetest/pulse_gen_gp.vhd 0 → 100644
View file @ def26966
--==============================================================================
-- CERN (BE-CO-HT)
-- General-purpose pulse generator
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-02-28
--
-- version: 2.0
--
-- description:
--
-- This module generates pulses with configurable frequency, width and delay.
--
-- In order to generate pulses, the module must be enabled via the en_i port.
-- Once en_i is high, pulses are generated at the frequency specified via
-- freq_i, with the width specified via pwidth_i.
--
-- An optional delay can be added before the start of the pulse, via the delay_i
-- port.
--
-- Note that this delay can be set only before the module is enabled.
--
-- freq_i, pwidth_i and delay_i are given in clk_i cycles.
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-02-28 Theodor Stana t.stana@cern.ch File created
-- 2013 08-15 Theodor Stana t.stana@cern.ch v2.0, delay, pwidth, freq
-- now controllable via
-- inputs (regs, etc.)
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_gen_gp is
port
(
-- Input clock and active-low reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Active high enable signal
en_i : in std_logic;
-- Delay, pulse width and frequency inputs, in number of clk_i cycles
delay_i : in std_logic_vector(31 downto 0);
pwidth_i : in std_logic_vector(31 downto 0);
freq_i : in std_logic_vector(31 downto 0);
-- Output pulse signal
pulse_o : out std_logic
);
end entity pulse_gen_gp;
architecture behav of pulse_gen_gp is
--============================================================================
-- Function and procedure declarations
--============================================================================
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
--============================================================================
-- Signal declarations
--============================================================================
signal inp_delay : unsigned(31 downto 0);
signal inp_pwidth : unsigned(31 downto 0);
signal inp_freq : unsigned(31 downto 0);
signal freq_cnt : unsigned(31 downto 0);
signal delay_cnt : unsigned(31 downto 0);
signal delay_en : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Convert std_logic_vector inputs to unsigned
--============================================================================
inp_delay <= unsigned(delay_i);
inp_pwidth <= unsigned(pwidth_i);
inp_freq <= unsigned(freq_i);
--============================================================================
-- Delay logic
--============================================================================
p_delay: process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') or (en_i = '0') then
delay_en <= '1';
delay_cnt <= (others => '0');
else
if (inp_delay = (inp_delay'range => '0')) then
delay_en <= '0';
elsif (delay_en = '1') then
delay_cnt <= delay_cnt + 1;
if (delay_cnt = inp_delay) then
delay_en <= '0';
delay_cnt <= (others => '0');
end if;
end if;
end if;
end if;
end process p_delay;
--============================================================================
-- Pulse generation logic
--============================================================================
p_gen_pulse: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') or (en_i = '0') then
freq_cnt <= (others => '0');
pulse_o <= '0';
elsif (delay_en = '0') then
freq_cnt <= freq_cnt + 1;
pulse_o <= '0';
if (freq_cnt < inp_pwidth) then
pulse_o <= '1';
elsif (freq_cnt = inp_freq-1) then
freq_cnt <= (others => '0');
end if;
end if;
end if;
end process p_gen_pulse;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
modules/reset_gen.vhd 0 → 100644
View file @ def26966
--==============================================================================
-- CERN (BE-CO-HT)
-- Reset generator for CONV-TTL-* boards
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-03-05
--
-- version: 1.0
--
-- description:
-- This module generates a variable-width reset pulse. The width of the pulse
-- is set via the g_reset_time pulse; an internal counter counts up to this
-- value and de-asserts the active-low reset line when the value has been
-- reached. At the same time, the module is de-activated.
--
-- By default, a 125 MHz clock is assumed (8ns period), resulting in a 96ms
-- reset width.
--
-- dependencies:
-- none
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-03-05 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reset_gen is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time : positive := 12_000_000
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
rst_n_o : out std_logic
);
end entity reset_gen;
architecture behav of reset_gen is
--============================================================================
-- Function and procedure declarations
--============================================================================
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
--============================================================================
-- Signal declarations
--============================================================================
signal cnt : unsigned(f_log2_size(g_reset_time)-1 downto 0) := (others => '0');
signal cnt_en : std_logic := '1';
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Reset generation logic
--============================================================================
p_rst_gen: process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
cnt_en <= '1';
cnt <= (others => '0');
elsif (cnt_en = '1') then
rst_n_o <= '0';
cnt <= cnt + 1;
if (cnt = g_reset_time) then
rst_n_o <= '1';
cnt_en <= '0';
end if;
end if;
end if;
end process p_rst_gen;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
modules/rtm_detector.vhd 0 → 100644
View file @ def26966
--==============================================================================
-- CERN (BE-CO-HT)
-- Rear transition module (RTM) detector
--==============================================================================
--
-- author: Carlos Gil Soriano
-- Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-01-09
--
-- version: 2.0
--
-- description:
--
-- This module detects the presence of rear transition module motherboards
-- (RTMMs) and piggybacks (RTMPs). Detection works by checking the RTMM and
-- RTMP input pins and these pins are pulled up on the front module. The
-- RTMM_OK and RTMP_OK ouputs are set if the corresponding inputs do not
-- yield errors. Different boards have the RTMM/P pins setup differently,
-- as outlined in the tables below:
--
-- Table 1. RTMM detection pins.
-- __________________________________________
-- | Board | RTMM[2] | RTMM[1] | RTMM[0] |
-- +-----------------------------------------+
-- | Error | '1' | '1' | '1' |
-- | RTMM_V1 | '1' | '1' | '0' |
-- | RTMM_V2 | '1' | '0' | '1' |
-- | Reserved | '1' | '0' | '0' |
-- | Reserved | '0' | '1' | '1' |
-- | Reserved | '0' | '1' | '0' |
-- | Reserved | '0' | '0' | '1' |
-- | Reserved | '0' | '0' | '0' |
-- +-----------+---------+---------+---------+
--
--
-- Table 2. RTMP detection pins.
-- _____________________________________________
-- | Board | RTMP[2] | RTMP[1] | RTMP[0] |
-- +-------------------------------------------+
-- | Error OR | '1' | '1' | '1' |
-- | Blocking_V1 | | | |
-- | RS485_V1 | '1' | '1' | '0' |
-- | -Reserved- | '1' | '0' | '1' |
-- | -Reserved- | '1' | '0' | '0' |
-- | -Reserved- | '0' | '1' | '1' |
-- | -Reserved- | '0' | '1' | '0' |
-- | -Reserved- | '0' | '0' | '1' |
-- | Error | '0' | '0' | '0' |
-- +-------------+---------+---------+---------+
--
--
-- dependencies:
-- none
--
-- references:
-- http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-01-09 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library IEEE;
library work;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity rtm_detector is
port
(
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
rtmm_ok_o : out std_logic;
rtmp_ok_o : out std_logic
);
end entity rtm_detector;
architecture Behavioral of rtm_detector is
begin
rtmm_ok_o <= '0' when (rtmm_i = "111") else '1';
rtmp_ok_o <= '0' when (rtmp_i = "111") else '1';
end Behavioral;
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files = [
"i2c_slave_pkg.vhd",
"i2c_slave.vhd",
"vbcp_wb.vhd"
]
modules = {
"local" : ".."
}
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--==============================================================================
-- CERN (BE-CO-HT)
-- Package for i2c_slave.vhd
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-06-06
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-06-06 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package i2c_slave_pkg is
--============================================================================
-- Constant declarations
--============================================================================
constant c_i2cs_idle : std_logic_vector(1 downto 0) := "00";
constant c_i2cs_addr_good : std_logic_vector(1 downto 0) := "01";
constant c_i2cs_rd_done : std_logic_vector(1 downto 0) := "10";
constant c_i2cs_wr_done : std_logic_vector(1 downto 0) := "11";
--============================================================================
-- Component declarations
--============================================================================
component i2c_slave is
port
(
-- Clock, reset ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C lines
scl_i : in std_logic;
scl_o : out std_logic;
scl_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_en_o : out std_logic;
-- Slave address
i2c_addr_i : in std_logic_vector(6 downto 0);
-- ACK input, should be set after done_p_o = '1'
-- (note that the bit is reversed wrt I2C ACK bit)
-- '1' - ACK
-- '0' - NACK
i2c_ack_i : in std_logic;
-- I2C bus operation, set after address detection
-- '0' - write
-- '1' - read
op_o : out std_logic;
-- Byte to send, should be loaded while done_p_o = '1'
tx_byte_i : in std_logic_vector(7 downto 0);
-- Received byte, valid after done_p_o = '1'
rx_byte_o : out std_logic_vector(7 downto 0);
-- Done pulse signal, valid when
-- * received address matches i2c_addr_i, signaling valid op_o;
-- * a byte was received, signaling valid rx_byte_o and an ACK/NACK should be
-- sent to master;
-- * sent a byte, should set tx_byte_i.
done_p_o : out std_logic;
-- I2C transfer state
-- "00" - Idle
-- "01" - Got address, matches i2c_addr_i
-- "10" - Read done, waiting ACK/NACK
-- "11" - Write done, waiting next byte
stat_o : out std_logic_vector(1 downto 0)
);
end component i2c_slave;
end package i2c_slave_pkg;
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files = [
"spi_master.vhd",
"multiboot_fsm.vhd",
"multiboot_regs.vhd",
"xil_multiboot.vhd"
]
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-----------------------------------------------------------------------------
-- Title : SPI Bus Master
-- Project : Simple VME64x FMC Carrier (SVEC)
-------------------------------------------------------------------------------
-- File : spi_master.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2013-01-25
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Just a simple SPI master (bus-less).
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011-2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_master is
generic(
-- clock division ratio (SCLK = clk_sys_i / (2 ** g_div_ratio_log2).
g_div_ratio_log2 : integer := 2;
-- number of data bits per transfer
g_num_data_bits : integer := 2);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- state of the Chip select line (1 = CS active). External control
-- allows for multi-transfer commands (SPI master itself does not
-- control the state of spi_cs_n_o)
cs_i : in std_logic;
-- 1: start next transfer (using CPOL, DATA and SEL from the inputs below)
start_i : in std_logic;
-- Clock polarity: 1: slave clocks in the data on rising SCLK edge, 0: ...
-- on falling SCLK edge
cpol_i : in std_logic;
-- TX Data input
data_i : in std_logic_vector(g_num_data_bits - 1 downto 0);
-- 1: data_o contains the result of last read operation. Core is ready to initiate
-- another transfer.
ready_o : out std_logic;
-- data read from selected slave, valid when ready_o == 1.
data_o : out std_logic_vector(g_num_data_bits - 1 downto 0);
-- these are obvious
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end spi_master;
architecture behavioral of spi_master is
signal divider : unsigned(11 downto 0);
signal tick : std_logic;
signal sreg : std_logic_vector(g_num_data_bits-1 downto 0);
signal rx_sreg : std_logic_vector(g_num_data_bits-1 downto 0);
type t_state is (IDLE, TX_CS, TX_DAT1, TX_DAT2, TX_SCK1, TX_SCK2, TX_CS2, TX_GAP);
signal state : t_state;
signal sclk : std_logic;
signal counter : unsigned(4 downto 0);
begin -- rtl
-- Simple clock divder. Produces a 'tick' signal which defines the timing for
-- the main state machine transitions.
p_divide_spi_clock: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
divider <= (others => '0');
else
if(start_i = '1' or tick = '1') then
divider <= (others => '0');
else
divider <= divider + 1;
end if;
end if;
end if;
end process;
tick <= divider(g_div_ratio_log2);
-- Main state machine. Executes SPI transfers
p_main_fsm: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
state <= IDLE;
sclk <= '0';
sreg <= (others => '0');
rx_sreg <= (others => '0');
spi_mosi_o <= '0';
data_o <= (others => '0');
counter <= (others => '0');
else
case state is
-- Waits for start of transfer command
when IDLE =>
sclk <= '0';
counter <= (others => '0');
if(start_i = '1') then
sreg <= data_i;
state <= TX_CS;
spi_mosi_o <= data_i(sreg'high);
end if;
-- Generates a gap between the externally asserted Chip Select and
-- the beginning of data transfer
when TX_CS =>
if tick = '1' then
state <= TX_DAT1;
end if;
-- Outputs subsequent bits to MOSI line.
when TX_DAT1 =>
if(tick = '1') then
spi_mosi_o <= sreg(sreg'high);
sreg <= sreg(sreg'high-1 downto 0) & '0';
state <= TX_SCK1;
end if;
-- Flips the SCLK (active edge)
when TX_SCK1 =>
if(tick = '1') then
sclk <= not sclk;
counter <= counter + 1;
state <= TX_DAT2;
end if;
-- Shifts in bits read from the slave
when TX_DAT2 =>
if(tick = '1') then
rx_sreg <= rx_sreg(rx_sreg'high-1 downto 0) & spi_miso_i;
state <= TX_SCK2;
end if;
-- Flips the SCLK (inactive edge). Checks if all bits have been
-- transferred.
when TX_SCK2 =>
if(tick = '1') then
sclk <= not sclk;
if(counter = g_num_data_bits) then
state <= TX_CS2;
else
state <= TX_DAT1;
end if;
end if;
-- Generates a gap for de-assertoin of CS line
when TX_CS2 =>
if(tick = '1') then
state <= TX_GAP;
data_o <= rx_sreg;
end if;
when TX_GAP =>
if (tick = '1') then
state <= IDLE;
end if;
end case;
end if;
end if;
end process;
ready_o <= '1' when (state = IDLE and start_i = '0') else '0';
-- SCLK polarity control
spi_sclk_o <= sclk xor cpol_i;
spi_cs_n_o <= not cs_i;
end behavioral;
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target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "conv_ttl_blo"
syn_project = "conv_ttl_blo.xise"
modules = {
"local" : [
"../../top/Release"
]
}
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target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "pulsetest"
syn_project = "pulsetest.xise"
modules = {
"local" : [
"../../top/pulsetest"
]
}
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top/regtest/Manifest.py
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......@@ -6,8 +6,6 @@ files = [
modules = {
"local" : [
"../../ip_cores/general-cores",
"../../reset_gen",
"../../bicolor_led_ctrl",
"../../vbcp_wb"
"../../modules/"
],
}
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