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Conv TTL Blocking - Gateware
Commit cd8852bb authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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doc/hwguide/fig/rtmdet.svg 0 → 100644
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doc/hwguide/hwguide-conv-ttl-blo.bib
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......@@ -38,7 +38,18 @@
title = {{TPS40210, TPS40211, 4.5~V to 52~V Input Current Mode Boost Controller}},
howpublished = {\url{http://www.ohwr.org/documents/227}}
}
@misc{spec,
title = {{Simple PCIE FMC Carrier (SPEC)}},
howpublished = {\url{http://www.ohwr.org/projects/spec}}
}
@misc{svec,
title = {{Simple VME FMC Carrier (SVEC)}},
howpublished = {\url{http://www.ohwr.org/projects/svec}}
}
@misc{rtmdet,
title = {{Rear Transition Module Detection}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection}}
}
doc/hwguide/hwguide-conv-ttl-blo.tex
View file @ cd8852bb
......@@ -132,6 +132,50 @@ The schematics of the CONV-TTL-BLO board can be found at \cite{conv-ttl-blo-sch}
\label{fig:conv-ttl-blo-bd}
\end{figure}
%------------------------------------------------------------------------------
% SEC: VME conn
%------------------------------------------------------------------------------
\subsection{VME connector}
\label{sec:vme}
\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 8 \\
\hline
\end{tabular}
\vspace*{11pt}
\noindent
The VME backplane consists in two connectors, P1 and P2. The following connections
provided by the P1 connector are used on the CONV-TTL-BLO:
\begin{itemize}
\item the VME power supply pins (3.3~V, 5~V and 12~V)
\item \textit{SERCLK} and \textit{SERDAT} pins, for I$^2$C communication
\item the geographical addressing pins, also necessary for I$^2$C communication
\item the active-low system reset line, connected to the FPGA for resetting the
logic implemented therein
\end{itemize}
Serial communication lines, geographical addressing lines and the system reset line
are isolated from the FPGA by means of a Texas Instruments SN74VMEH22501DGGR bus
transceiver. Their use is based on the SVEC design \cite{svec} and is due to their
compatibility to the VME standard.
Apart from the bus grant and IACK lines, which are daisy-chained, the rest of the
VME signals are not used on the CONV-TTL-BLO board.
The user-defined part of the P2 connector is used for carrying signals from the
CONV-TTL-BLO to the RTM and ultimately the piggyback. The following signals are
routed via the VME P2 connector:
\begin{itemize}
\item blocking input signals (Section~\ref{sec:blo-inp})
\item blocking output signals (Section~\ref{sec:blo-outp})
\item RTM detection and rear panel pulse LED signals (Section~\ref{sec:rmtdet})
\end{itemize}
%------------------------------------------------------------------------------
% SUBSEC: Power
%------------------------------------------------------------------------------
......@@ -146,11 +190,11 @@ The schematics of the CONV-TTL-BLO board can be found at \cite{conv-ttl-blo-sch}
\vspace*{11pt}
Various power levels are needed on the CONV-TTL-BLO board. They are listed in
\noindent Various power levels are needed on the CONV-TTL-BLO board. They are listed in
Table~\ref{tbl:voltage-levels}. All power supplies on the board are derived
in some way from the 3.3~V, 5~V and 12~V VME power supplies.
\begin{table}
\begin{table}[h]
\caption{Voltage levels on CONV-TTL-BLO}
\label{tbl:voltage-levels}
\centerline{
......@@ -193,7 +237,7 @@ using the first design example in the datasheet of the device~\cite{blo-ps-datas
\vspace*{11pt}
There are multiple clock signals on the CONV-TTL-BLO (Table~\ref{tbl:clocks}).
\noindent There are multiple clock signals on the CONV-TTL-BLO (Table~\ref{tbl:clocks}).
A 20~MHz clock for the FPGA is generated directly from a tunable VCXO (OSC3). The
second FPGA clock is a 125~MHz signal generated from a 25~MHz VCXO by means of a Texas
Instruments CDCM61004RHBT PLL IC. Two of the other PLL's output channels are used
......@@ -239,7 +283,7 @@ The design of the clock circuits is based on the SPEC board design \cite{spec}.
\vspace*{11pt}
A Xilinx XC6SLX45T Spartan-6 FPGA is present on the CONV-TTL-BLO board. It is the
\noindent A Xilinx XC6SLX45T Spartan-6 FPGA is present on the CONV-TTL-BLO board. It is the
core part of the blocking conversion system, since it is the device controlling
all the components on the board.
......@@ -271,7 +315,7 @@ HDL Guide \textcolor{red}{\textbf{REFER}}.
\vspace*{11pt}
TTL and TTL-BAR pulses may arrive on front panels of CONV-TTL-BLO boards. The two
\noindent TTL and TTL-BAR pulses may arrive on front panels of CONV-TTL-BLO boards. The two
signal types are described in Sections~4.1~and~4.2 of~\cite{ctb-ug}. Signals
arriving on an input channel go through an input stage consisting of Schmitt
trigger circuits; they are then input to the FPGA, where the pulse gets regenerated
......@@ -329,7 +373,7 @@ output of the channel.
\vspace*{11pt}
Blocking pulses arrive through the LEMO connectors on the rear panel. Through the
\noindent Blocking pulses arrive through the LEMO connectors on the rear panel. Through the
RTM and the P2 connector, they arrive at the blocking input stage on the CONV-TTL-BLO,
where an optocoupler is used to isolate the input signal from the logic levels of
the FPGA. The input pulse then goes into the FPGA, where the pulse is regenerated
......@@ -342,6 +386,7 @@ blocking level.
%------------------------------------------------------------------------------
\subsubsection{Blocking input stage}
\label{sec:blo-inp}
\begin{tabular}{p{.95\textwidth}}
\hline
......@@ -351,20 +396,27 @@ blocking level.
\vspace*{11pt}
The blocking input stage contains the 50~$\Omega$ termination, a transient voltage
suppressor diode to protect against high-voltage spikes from the RTM, a high-pass RC filter which
prevents DC signals from passing to the Avago optocoupler. The optocoupler
\noindent The blocking input stage (Figure~\ref{fig:blo-inp-nodots}) contains the 50~$\Omega$ termination,
a transient voltage suppressor diode to protect against high-voltage spikes from the RTM, a
high-pass RC filter which prevents DC signals from passing to the Avago optocoupler. The optocoupler
isolates the blocking-level stage from the logic stage on the FPGA side. Since the
optocoupler is powered from 5~V, a Schmitt trigger (not shown in Figure~\ref{fig:blo-inp})
optocoupler is powered from 5~V, a Schmitt trigger (not shown in Figure~\ref{fig:blo-inp-nodots})
adapts the 5~V level to the 3.3~V level needed by the FPGA.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/blo-inp-nodots}}
\caption{Blocking input stage}
\label{fig:blo-inp-nodots}
\end{figure}
The minimum pulse level for this circuit is 3.8~V (see Appendix~\ref{app:blo-min-level}).
The maximum 24~V pulse width that can be safely sustained by the input stage is 3.9~${\mu}s$
with a minimum period of 4.8~${\mu}s$ (see Appendix~\ref{app:blo-max-width}).
The maximum 24~V pulse width that can be safely sustained by the input stage is 3.9~$\mu$s
with a minimum period of 4.8~${\mu}$s (see Appendix~\ref{app:blo-max-width}).
%------------------------------------------------------------------------------
\subsubsection{Blocking output stage}
\label{sec:blo-outp}
\begin{tabular}{p{.95\textwidth}}
\hline
......@@ -374,6 +426,54 @@ with a minimum period of 4.8~${\mu}s$ (see Appendix~\ref{app:blo-max-width}).
\vspace*{11pt}
\noindent The blocking output stage is a flyback converter design with a 1:1 conversion
ratio, shown in Figure~\ref{fig:blo-outp-nodots}. The core part of the output stage is
the flyback transformer assuring galvanic isolation at the output. The transformer is
driven straight from the 24~V blocking supply and controlled via the BSH103 power MOSFET.
The snubber circuit next to the transformer formed by the BAR66 diode and the Zener diode
provides a means to dissipate the energy stored in the leakage inductance of the transformer
when the MOSFET is on.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/blo-outp-nodots}}
\caption{Blocking output stage}
\label{fig:blo-outp-nodots}
\end{figure}
Upstream of the MOSFET's grid pin is a circuit similar to that in the TTL output stage.
This circuit is shown in Figure~\ref{fig:blo-outp-tristate}. The tri-state buffers'
outputs are high-impedance on startup, thus avoidiing spurious signals on blocking outputs.
The pull-down resistors at the outputs ensure a low-level signal on the MOSFET's grid
on startup.
The tri-state buffers are enabled by means of two signals from the FPGA: the output enable
signal common with the TTL output enable, and a separate, blocking output enable signal.
These two signals go through the IC10 NAND gate to enable the buffers. When the FPGA does
not drive either of these signals, the output enable input of the buffers is kept high via
the pull-up resistor.
\begin{figure}[h]
\centerline{\includegraphics[scale=1]{fig/blo-outp-tristate}}
\caption{Blocking output tri-state buffers}
\label{fig:blo-outp-tristate}
\end{figure}
The maximum pulse width that can be sustained without damaging the MOSFET is
\textcolor{red}{\textbf{!!!}} (see Appendix~\ref{app:blo-max-pw}).
The maximum pulse frequency that can be sustained without damaging the MOSFET
is 210~kHz (see Appendix~\ref{app:blo-max-freq}).
%\vspace*{11pt}
\noindent \textbf{\textit{Note that if the FPGA is improperly configured, a DC high-level signal
on the power MOSFET's grid pin will yield a too high current passing through the MOSFET,
which will lead to its failure. Make sure the FPGA pins driving the blocking output stage
are properly configured to drive time-limited pulses or a DC low-level at the power
MOSFET's grid, or that the blocking output enable signal from the FPGA is low, so as to
keep the outputs of the tri-state buffers in high-impedance.}}
\textcolor{red}{\textbf{details about output circuit}}
\textcolor{red}{\textbf{galvanic isolation}}
......@@ -396,7 +496,7 @@ with a minimum period of 4.8~${\mu}s$ (see Appendix~\ref{app:blo-max-width}).
\vspace*{11pt}
The small form-factor pluggable (SFP) connector on the CONV-TTL-BLO front panel
\noindent The small form-factor pluggable (SFP) connector on the CONV-TTL-BLO front panel
can be used to input an optic fiber cable that may be used for pulse time-tagging
using White Rabbit.
......@@ -414,13 +514,69 @@ using White Rabbit.
\vspace*{11pt}
A DS18B20U+ thermometer chip is provided on board. This chip can be used to provide
\noindent A DS18B20U+ thermometer chip is provided on board. This chip can be used to provide
a unique ID for the board and measure on-board temperature. It communicates to the
FPGA via a Dallas one-wire interface and is powered from 3.3~V.
The Flash chip on-board is used to store FPGA configuration data. It is a Micron
M25P32 SPI Flash memory chip with 32~Mbits storage capability.
%------------------------------------------------------------------------------
% SEC: RTM det
%------------------------------------------------------------------------------
\subsection{RTM detection}
\label{sec:rmtdet}
\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 8 \\
\hline
\end{tabular}
\vspace*{11pt}
\noindent
The RTM detection circuitry is shown in Figure~\ref{fig:rtmdet}. It works by
connecting the RTM motherboard or piggyback detection lines to ground, based
on the motherboard or piggyback used. Lines not connected to ground are pulled
up to V$_{CC}$ by the pull-up resistor, which yields a low value after
the Schmitt triggers. The outputs of the Schmitt triggers are connected directly
to the FPGA inputs.
An up-to-date list of boards and their RTM detection line connections can be found
at \cite{rtmdet}.
\begin{figure}[h]
\centerline{\includegraphics[scale=1]{fig/rtmdet}}
\caption{RTM detection circuit}
\label{fig:rtmdet}
\end{figure}
%------------------------------------------------------------------------------
% SEC: LEDs, status and pulse
%------------------------------------------------------------------------------
\subsection{Status and pulse LEDs}
\label{sec:leds}
\begin{tabular}{p{.95\textwidth}}
\hline
\large Schematics: page 14 \\
\hline
\end{tabular}
\vspace*{11pt}
The circuit for driving the bicolor status LEDs is based on the SVEC design \cite{svec}.
It consists of the same Texas Instruments SN74VMEH22501DGGR bus buffer chip used
for buffering the VME signals. The control and data lines of the chip are driven
by logic within the FPGA, which controls lighting of each of the LEDs. An example
of how the LEDs can be driven using the FPGA is given in Section~5 of \textcolor{red}{CITE HDL GUIDE}.
TTL (front panel) and blocking (rear panel) pulse LEDs are driven by the FPGA
via a SN7414 Schmitt trigger. In the case of the blocking LEDs, the output of
the Schmitt trigger is connected directly to the VME P2 connector and through
the RTM to the piggyback, where the current-limiting resistor and the LEDare located.
%==============================================================================
% SEC: RTM, RTMP
......@@ -429,8 +585,9 @@ M25P32 SPI Flash memory chip with 32~Mbits storage capability.
\label{sec:rtm}
Rear transition modules (RTMs) are located on the rear side of the VME crate.
The two boards (motherboard and piggyback) of which the RTMs in TTL to blocking
converter systems are composed contain only passive components.
An RTM in TTL to blocking converter systems is made up of two boards, the
motherboard and the piggyback, containing only passive components. The two boards
are detailed in the next subsections.
%------------------------------------------------------------------------------
% SUBSEC: RTMM
......@@ -442,10 +599,12 @@ RTM piggyback board. It provides a female connector to the VME backplane P2
connector and links the blocking and pulse LED signals from the CONV-TTL-BLO
to the piggyback via a 100-pin connector.
\textcolor{red}{\textbf{board pic}}
RTM motherboards are used in both CONV-TTL-BLO and CONV-TTL-RS485 systems, with
different piggybacks.
The motherboard also contains 47~V transient voltage suppressor (TVS) diodes that inhibit
The motherboard also contains 47~V transient voltage suppressor diodes that inhibit
high-voltage pulses arriving on piggyback LEMO connectors.
%------------------------------------------------------------------------------
......@@ -453,11 +612,14 @@ high-voltage pulses arriving on piggyback LEMO connectors.
%------------------------------------------------------------------------------
\subsection{RTM Piggyback}
The RTM piggyback~\cite{rtmp-sch} provides the actual connectors on rear panels of TTL to blocking
converter systems. There are four LEMO connectors and one LED and its corresponding
current-limiting resistor for each of the six blocking channels. The connections for
each of the LEMOs and LEDs are provided via a 100-pin male connector, through the RTM
motherboard, to the CONV-TTL-BLO.
The RTM piggyback~\cite{rtmp-sch} provides the actual connectors on rear panels of
TTL to blocking converter systems. On each of the six blocking channels, there are
four LEMO connectors (one input and three outputs) and one LED together with its
corresponding current-limiting resistor. The connections for each of the LEMOs and
LEDs are made via the 100-pin male connector, through the RTM motherboard, to the
CONV-TTL-BLO.
\textcolor{red}{\textbf{board pic}}
%==============================================================================
% Appendices
......@@ -573,7 +735,7 @@ I_{LED,RMS} = I_{LED} \sqrt{\delta}
\delta \cong 0.81
\end{equation}
With the minimum 4.8~${\mu}s$ pulse period at the output, this gives a maximum input pulse
With the minimum 4.8~$\mu$s pulse period at the output, this gives a maximum input pulse
width of
\begin{equation}
......@@ -583,6 +745,24 @@ t_{p,max} \cong 3.9 {\mu}s
\end{appendices}
%==============================================================================
% APP: Block inp stage calc
%==============================================================================
\section{Blocking output stage calculations}
\label{app:blo-outp}
%------------------------------------------------------------------------------
% SUBSEC: max. pulse width
%------------------------------------------------------------------------------
\subsection{Maximum pulse width}
\label{app:blo-max-pw}
%------------------------------------------------------------------------------
% SUBSEC: max. pulse freq
%------------------------------------------------------------------------------
\subsection{Maximum pulse frequency at nominal pulse width}
\label{app:blo-max-freq}
%==============================================================================
% Bibliography
%==============================================================================
......
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