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Commit c08b5d55 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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regtest firmware: Made changes to accomodate additions to wb_i2c_bridge component 

interface
Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 78769118
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syn/regtest/Makefile
View file @ c08b5d55
...@@ -58,6 +58,7 @@ FILES := ../../top/regtest/regtest.ucf \ ...@@ -58,6 +58,7 @@ FILES := ../../top/regtest/regtest.ucf \
../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \ ../../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \ ../../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \
../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \ ../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \
../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \ ../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \ ../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \ ../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
......
syn/regtest/regtest.xise
View file @ c08b5d55
...@@ -403,279 +403,282 @@ ...@@ -403,279 +403,282 @@
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/> <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/> <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/> <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/> <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/> <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/> <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/> <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/> <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/> <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/> <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/> <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/> <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/> <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/> <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/> <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/> <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/> <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/> <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/> <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/> <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/> <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/> <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/> <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/> <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/> <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/> <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/> <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="49"/> <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/> <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="51"/> <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/> <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="53"/> <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="54"/> <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="55"/> <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="56"/> <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="57"/> <association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="58"/> <association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="59"/> <association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="60"/> <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="61"/> <association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="62"/> <association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="63"/> <association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="64"/> <association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="65"/> <association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="66"/> <association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="67"/> <association xil_pn:name="Implementation" xil_pn:seqID="67"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="68"/> <association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="69"/> <association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="70"/> <association xil_pn:name="Implementation" xil_pn:seqID="70"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="71"/> <association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/> <association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="73"/> <association xil_pn:name="Implementation" xil_pn:seqID="73"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="74"/> <association xil_pn:name="Implementation" xil_pn:seqID="74"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="75"/> <association xil_pn:name="Implementation" xil_pn:seqID="75"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="76"/> <association xil_pn:name="Implementation" xil_pn:seqID="76"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="77"/> <association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="78"/> <association xil_pn:name="Implementation" xil_pn:seqID="78"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="79"/> <association xil_pn:name="Implementation" xil_pn:seqID="79"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/> <association xil_pn:name="Implementation" xil_pn:seqID="80"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="81"/> <association xil_pn:name="Implementation" xil_pn:seqID="81"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="82"/> <association xil_pn:name="Implementation" xil_pn:seqID="82"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="83"/> <association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="84"/> <association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="85"/> <association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/> <association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/> <association xil_pn:name="Implementation" xil_pn:seqID="87"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="88"/> <association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="89"/> <association xil_pn:name="Implementation" xil_pn:seqID="89"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="90"/> <association xil_pn:name="Implementation" xil_pn:seqID="90"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="91"/> <association xil_pn:name="Implementation" xil_pn:seqID="91"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="92"/> <association xil_pn:name="Implementation" xil_pn:seqID="92"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="93"/> <association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="94"/> <association xil_pn:name="Implementation" xil_pn:seqID="94"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="95"/> <association xil_pn:name="Implementation" xil_pn:seqID="95"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="96"/> <association xil_pn:name="Implementation" xil_pn:seqID="96"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="97"/> <association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="98"/> <association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="99"/> <association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="100"/> <association xil_pn:name="Implementation" xil_pn:seqID="100"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="101"/> <association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="102"/> <association xil_pn:name="Implementation" xil_pn:seqID="102"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="103"/> <association xil_pn:name="Implementation" xil_pn:seqID="103"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="104"/> <association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="105"/> <association xil_pn:name="Implementation" xil_pn:seqID="105"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="106"/> <association xil_pn:name="Implementation" xil_pn:seqID="106"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="107"/> <association xil_pn:name="Implementation" xil_pn:seqID="107"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="108"/> <association xil_pn:name="Implementation" xil_pn:seqID="108"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="109"/> <association xil_pn:name="Implementation" xil_pn:seqID="109"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="110"/> <association xil_pn:name="Implementation" xil_pn:seqID="110"/>
</file> </file>
<file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="111"/> <association xil_pn:name="Implementation" xil_pn:seqID="111"/>
</file> </file>
<file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="112"/> <association xil_pn:name="Implementation" xil_pn:seqID="112"/>
</file> </file>
<file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="113"/> <association xil_pn:name="Implementation" xil_pn:seqID="113"/>
</file> </file>
<file xil_pn:name="../../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="114"/>
</file>
</files> </files>
<bindings/> <bindings/>
......
top/regtest/regtest.ucf
View file @ c08b5d55
...@@ -62,7 +62,7 @@ NET "mr_n_o" LOC = T22; ...@@ -62,7 +62,7 @@ NET "mr_n_o" LOC = T22;
NET "mr_n_o" IOSTANDARD = LVCMOS33; NET "mr_n_o" IOSTANDARD = LVCMOS33;
NET "clk20_vcxo_i" LOC = E16; NET "clk20_vcxo_i" LOC = E16;
NET "clk20_vcxo_i" TNM_NET=clk20_vcxo_i; NET "clk20_vcxo_i" TNM_NET = "clk20_vcxo_i";
TIMESPEC TSCLK20 = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %; TIMESPEC TSCLK20 = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %;
##============================================================================= ##=============================================================================
...@@ -225,30 +225,30 @@ NET "inv_out_o[4]" IOSTANDARD = LVCMOS33; ...@@ -225,30 +225,30 @@ NET "inv_out_o[4]" IOSTANDARD = LVCMOS33;
##-- Blocking I/O ##-- Blocking I/O
##----------------------------------------------------------------------------- ##-----------------------------------------------------------------------------
NET "fpga_blo_in_i[1]" LOC = Y9; NET "fpga_blo_in_i[1]" LOC = Y9;
NET "fpga_blo_in_i[1]" IOSTANDARD = "LVCMOS33"; NET "fpga_blo_in_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[2]" LOC = AA10; NET "fpga_blo_in_i[2]" LOC = AA10;
NET "fpga_blo_in_i[2]" IOSTANDARD = "LVCMOS33"; NET "fpga_blo_in_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[3]" LOC = W12; NET "fpga_blo_in_i[3]" LOC = W12;
NET "fpga_blo_in_i[3]" IOSTANDARD = "LVCMOS33"; NET "fpga_blo_in_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[4]" LOC = AA6; NET "fpga_blo_in_i[4]" LOC = AA6;
NET "fpga_blo_in_i[4]" IOSTANDARD = "LVCMOS33"; NET "fpga_blo_in_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[5]" LOC = Y7; NET "fpga_blo_in_i[5]" LOC = Y7;
NET "fpga_blo_in_i[5]" IOSTANDARD = "LVCMOS33"; NET "fpga_blo_in_i[5]" IOSTANDARD = LVCMOS33;
NET "fpga_blo_in_i[6]" LOC = AA8; NET "fpga_blo_in_i[6]" LOC = AA8;
NET "fpga_blo_in_i[6]" IOSTANDARD = "LVCMOS33"; NET "fpga_blo_in_i[6]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[1]" LOC = W9; NET "fpga_trig_blo_o[1]" LOC = W9;
NET "fpga_trig_blo_o[1]" IOSTANDARD = "LVCMOS33"; NET "fpga_trig_blo_o[1]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[2]" LOC = T10; NET "fpga_trig_blo_o[2]" LOC = T10;
NET "fpga_trig_blo_o[2]" IOSTANDARD = "LVCMOS33"; NET "fpga_trig_blo_o[2]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[3]" LOC = V7; NET "fpga_trig_blo_o[3]" LOC = V7;
NET "fpga_trig_blo_o[3]" IOSTANDARD = "LVCMOS33"; NET "fpga_trig_blo_o[3]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[4]" LOC = U9; NET "fpga_trig_blo_o[4]" LOC = U9;
NET "fpga_trig_blo_o[4]" IOSTANDARD = "LVCMOS33"; NET "fpga_trig_blo_o[4]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[5]" LOC = T8; NET "fpga_trig_blo_o[5]" LOC = T8;
NET "fpga_trig_blo_o[5]" IOSTANDARD = "LVCMOS33"; NET "fpga_trig_blo_o[5]" IOSTANDARD = LVCMOS33;
NET "fpga_trig_blo_o[6]" LOC = R9; NET "fpga_trig_blo_o[6]" LOC = R9;
NET "fpga_trig_blo_o[6]" IOSTANDARD = "LVCMOS33"; NET "fpga_trig_blo_o[6]" IOSTANDARD = LVCMOS33;
##============================================================================= ##=============================================================================
##-- VME CONNECTOR SIGNALS ##-- VME CONNECTOR SIGNALS
...@@ -298,13 +298,13 @@ NET "fpga_gap_i" IOSTANDARD = LVCMOS33; ...@@ -298,13 +298,13 @@ NET "fpga_gap_i" IOSTANDARD = LVCMOS33;
##-- ROM memory ##-- ROM memory
##----------------------------------------------------------------------------- ##-----------------------------------------------------------------------------
NET "fpga_prom_cclk_o" LOC = Y20; NET "fpga_prom_cclk_o" LOC = Y20;
NET "fpga_prom_cclk_o" IOSTANDARD = "LVCMOS33"; NET "fpga_prom_cclk_o" IOSTANDARD = LVCMOS33;
NET "fpga_prom_cso_b_n_o" LOC = AA3; NET "fpga_prom_cso_b_n_o" LOC = AA3;
NET "fpga_prom_cso_b_n_o" IOSTANDARD = "LVCMOS33"; NET "fpga_prom_cso_b_n_o" IOSTANDARD = LVCMOS33;
NET "fpga_prom_miso_i" LOC = AA20; NET "fpga_prom_miso_i" LOC = AA20;
NET "fpga_prom_miso_i" IOSTANDARD = "LVCMOS33"; NET "fpga_prom_miso_i" IOSTANDARD = LVCMOS33;
NET "fpga_prom_mosi_o" LOC = AB20; NET "fpga_prom_mosi_o" LOC = AB20;
NET "fpga_prom_mosi_o" IOSTANDARD = "LVCMOS33"; NET "fpga_prom_mosi_o" IOSTANDARD = LVCMOS33;
##============================================================================= ##=============================================================================
##-- WHITE RABBIT ##-- WHITE RABBIT
...@@ -335,21 +335,21 @@ NET "fpga_plldac2_sync_n_o" IOSTANDARD = LVCMOS33; ...@@ -335,21 +335,21 @@ NET "fpga_plldac2_sync_n_o" IOSTANDARD = LVCMOS33;
##----------------------------------------------------------------------------- ##-----------------------------------------------------------------------------
##-- SFP connection ##-- SFP connection
##----------------------------------------------------------------------------- ##-----------------------------------------------------------------------------
NET "fpga_sfp_los_i" LOC = G3; NET "fpga_sfp_los_i" LOC = G3;
NET "fpga_sfp_los_i" IOSTANDARD = "LVCMOS33"; NET "fpga_sfp_los_i" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_mod_def0_i" LOC = K8; NET "fpga_sfp_mod_def0_i" LOC = K8;
NET "fpga_sfp_mod_def0_i" IOSTANDARD = "LVCMOS33"; NET "fpga_sfp_mod_def0_i" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_rate_select_o" LOC = C4; NET "fpga_sfp_rate_select_o" LOC = C4;
NET "fpga_sfp_rate_select_o" IOSTANDARD = "LVCMOS33"; NET "fpga_sfp_rate_select_o" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_mod_def1_b" LOC = G4; NET "fpga_sfp_mod_def1_b" LOC = G4;
NET "fpga_sfp_mod_def1_b" IOSTANDARD = LVCMOS33; NET "fpga_sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_mod_def2_b" LOC = F3; NET "fpga_sfp_mod_def2_b" LOC = F3;
NET "fpga_sfp_mod_def2_b" IOSTANDARD = LVCMOS33; NET "fpga_sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_tx_disable_o" LOC = E4; NET "fpga_sfp_tx_disable_o" LOC = E4;
NET "fpga_sfp_tx_disable_o" IOSTANDARD = "LVCMOS33"; NET "fpga_sfp_tx_disable_o" IOSTANDARD = LVCMOS33;
NET "fpga_sfp_tx_fault_i" LOC = D2; NET "fpga_sfp_tx_fault_i" LOC = D2;
NET "fpga_sfp_tx_fault_i" IOSTANDARD = "LVCMOS33"; NET "fpga_sfp_tx_fault_i" IOSTANDARD = LVCMOS33;
###----------------------------------------------------------------------------- ###-----------------------------------------------------------------------------
###-- FPGA MGT lines ###-- FPGA MGT lines
...@@ -390,19 +390,19 @@ NET "fpga_inv_oe_o" SLEW = QUIETIO; ...@@ -390,19 +390,19 @@ NET "fpga_inv_oe_o" SLEW = QUIETIO;
##-- Configuration Switches ##-- Configuration Switches
##----------------------------------------------------------------------------- ##-----------------------------------------------------------------------------
NET "extra_switch_n_i[1]" LOC = F22; NET "extra_switch_n_i[1]" LOC = F22;
NET "extra_switch_n_i[1]" IOSTANDARD = "LVCMOS33"; NET "extra_switch_n_i[1]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[2]" LOC = G22; NET "extra_switch_n_i[2]" LOC = G22;
NET "extra_switch_n_i[2]" IOSTANDARD = "LVCMOS33"; NET "extra_switch_n_i[2]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[3]" LOC = H21; NET "extra_switch_n_i[3]" LOC = H21;
NET "extra_switch_n_i[3]" IOSTANDARD = "LVCMOS33"; NET "extra_switch_n_i[3]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[4]" LOC = H22; NET "extra_switch_n_i[4]" LOC = H22;
NET "extra_switch_n_i[4]" IOSTANDARD = "LVCMOS33"; NET "extra_switch_n_i[4]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[5]" LOC = J22; NET "extra_switch_n_i[5]" LOC = J22;
NET "extra_switch_n_i[5]" IOSTANDARD = "LVCMOS33"; NET "extra_switch_n_i[5]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[6]" LOC = K21; NET "extra_switch_n_i[6]" LOC = K21;
NET "extra_switch_n_i[6]" IOSTANDARD = "LVCMOS33"; NET "extra_switch_n_i[6]" IOSTANDARD = LVCMOS33;
NET "extra_switch_n_i[7]" LOC = K22; NET "extra_switch_n_i[7]" LOC = K22;
NET "extra_switch_n_i[7]" IOSTANDARD = "LVCMOS33"; NET "extra_switch_n_i[7]" IOSTANDARD = LVCMOS33;
NET "ttl_switch_n_i" LOC = L22; NET "ttl_switch_n_i" LOC = L22;
NET "ttl_switch_n_i" IOSTANDARD = LVCMOS33; NET "ttl_switch_n_i" IOSTANDARD = LVCMOS33;
......
top/regtest/regtest.vhd
View file @ c08b5d55
-------------------------------------------------------------------------------- --==============================================================================
-- CERN (BE-CO-HT) -- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO -- Long-term register test for CONV-TTL-* boards
-- http://www.ohwr.org/projects/conv-ttl-blo --==============================================================================
--------------------------------------------------------------------------------
-- --
-- unit name: regtest.vhd -- author: Theodor Stana (t.stana@cern.ch)
--
-- author: Theodor-Adrian Stana (t.stana@cern.ch)
-- --
-- version: 1.0 -- version: 1.0
-- --
-- description: Top entity of CONV-TTL-BLO -- description:
-- This is the top-level file for the register test for TTL pulse converter
-- boards. It instantiates a single-port RAM from the general-cores OHWR
-- repository and connects this RAM via an xwb_crossbar (also from
-- general-cores) to the i2c_bridge component.
--
-- An external program on the PC should send commands according to the I2C
-- protocol established with ELMA [2], to write and read from the single-port
-- RAM. The CONV-TTL-BLO is plugged into this ELMA crate. The wb_i2c_bridge
-- translates these commands into wishbone accesses to the RAM.
--
-- An example program can be found in the conv-ttl-blo repository [3], under
-- the software/regtest/ folder. This Python script writes to and reads back
-- all data from the RAM and checks for correct reading.
-- --
-- dependencies: -- dependencies:
-- general-cores repository [1]
-- --
-- references: -- references:
-- [1] ELMA, Access to board data using SNMP and I2C -- [1] Platform-independent core collection webpage on OHWR,
-- http://www.ohwr.org/documents/227 -- http://www.ohwr.org/projects/general-cores/repository
-- [2] ELMA, Access to board data using SNMP and I2C
-- http://www.ohwr.org/documents/227
-- [3] CONV-TTL-BLO project repository on OHWR,
-- http://www.ohwr.org/projects/conv-ttl-blo/repository
-- --
-------------------------------------------------------------------------------- --==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE -- GNU LESSER GENERAL PUBLIC LICENSE
-------------------------------------------------------------------------------- --==============================================================================
-- This source file is free software; you can redistribute it and/or modify it -- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the -- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your -- Free Software Foundation; either version 2.1 of the License, or (at your
...@@ -30,7 +45,12 @@ ...@@ -30,7 +45,12 @@
-- See the GNU Lesser General Public License for more details. You should have -- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this -- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
-------------------------------------------------------------------------------- --==============================================================================
-- last changes:
-- 26-11-2013 Theodor Stana Changed file header
--==============================================================================
-- TODO: -
--==============================================================================
library ieee; library ieee;
library unisim; library unisim;
...@@ -185,7 +205,7 @@ architecture behav of regtest is ...@@ -185,7 +205,7 @@ architecture behav of regtest is
generic generic
( (
-- Reset time in number of clk_i cycles -- Reset time in number of clk_i cycles
g_reset_time : positive := 5_000_000 g_reset_time : positive := 2_000_000
); );
port port
( (
...@@ -195,42 +215,6 @@ architecture behav of regtest is ...@@ -195,42 +215,6 @@ architecture behav of regtest is
); );
end component reset_gen; end component reset_gen;
-- I2C bridge
-- (use: convert I2C transfers into WB transfers on memmapped registers)
component wb_i2c_bridge is
port
(
-- Clock, reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C lines
sda_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
-- I2C address and status
i2c_addr_i : in std_logic_vector(6 downto 0);
tip_o : out std_logic;
err_o : out std_logic;
-- Wishbone master signals
wbm_stb_o : out std_logic;
wbm_cyc_o : out std_logic;
wbm_sel_o : out std_logic_vector(3 downto 0);
wbm_we_o : out std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_adr_o : out std_logic_vector(31 downto 0);
wbm_ack_i : in std_logic;
wbm_rty_i : in std_logic;
wbm_err_i : in std_logic
);
end component wb_i2c_bridge;
--============================================================================ --============================================================================
-- Signal declarations -- Signal declarations
--============================================================================ --============================================================================
...@@ -252,15 +236,24 @@ architecture behav of regtest is ...@@ -252,15 +236,24 @@ architecture behav of regtest is
-- I2C bridge signals -- I2C bridge signals
signal i2c_tip : std_logic; signal i2c_tip : std_logic;
signal i2c_err : std_logic; signal i2c_tip_d0 : std_logic;
signal i2c_err_led : std_logic; signal i2c_err_p : std_logic;
signal i2c_up : std_logic; signal i2c_up : std_logic;
signal i2c_wdto_p : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0); signal i2c_addr : std_logic_vector(6 downto 0);
signal led_i2c : std_logic; signal led_i2c : std_logic;
signal led_i2c_clkdiv : unsigned(22 downto 0); signal led_i2c_clkdiv : unsigned(22 downto 0);
signal led_i2c_cnt : unsigned( 2 downto 0); signal led_i2c_cnt : unsigned( 2 downto 0);
signal blink_state : std_logic; signal led_i2c_err : std_logic;
signal led_i2c_blink : std_logic;
signal led_wdto : std_logic;
-- Transfer trigger for oscilloscope
signal trig_p : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin begin
--============================================================================ --============================================================================
...@@ -298,17 +291,18 @@ begin ...@@ -298,17 +291,18 @@ begin
rst_n_i => rst_n, rst_n_i => rst_n,
-- I2C lines -- I2C lines
sda_en_o => sda_oe_o,
sda_i => sda_i,
sda_o => sda_o,
scl_en_o => scl_oe_o,
scl_i => scl_i, scl_i => scl_i,
scl_o => scl_o, scl_o => scl_o,
scl_en_o => scl_oe_o,
sda_i => sda_i,
sda_o => sda_o,
sda_en_o => sda_oe_o,
-- I2C address and status -- I2C address and status
i2c_addr_i => i2c_addr, i2c_addr_i => i2c_addr,
tip_o => i2c_tip, tip_o => i2c_tip,
err_o => i2c_err, err_p_o => i2c_err_p,
wdto_p_o => i2c_wdto_p,
-- Wishbone master signals -- Wishbone master signals
wbm_stb_o => xbar_slave_in(0).stb, wbm_stb_o => xbar_slave_in(0).stb,
...@@ -332,16 +326,16 @@ begin ...@@ -332,16 +326,16 @@ begin
if rising_edge(clk20_vcxo_i) then if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then if (rst_n = '0') then
led_i2c_clkdiv <= (others => '0'); led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= (others => '0'); led_i2c_cnt <= (others => '0');
led_i2c <= '0'; led_i2c <= '0';
blink_state <= '0'; led_i2c_blink <= '0';
else else
case blink_state is case led_i2c_blink is
when '0' => when '0' =>
led_i2c <= '0'; led_i2c <= '0';
if (i2c_tip = '1') then if (i2c_tip = '1') then
blink_state <= '1'; led_i2c_blink <= '1';
end if; end if;
when '1' => when '1' =>
...@@ -352,12 +346,12 @@ begin ...@@ -352,12 +346,12 @@ begin
led_i2c <= not led_i2c; led_i2c <= not led_i2c;
if (led_i2c_cnt = 7) then if (led_i2c_cnt = 7) then
led_i2c_cnt <= (others => '0'); led_i2c_cnt <= (others => '0');
blink_state <= '0'; led_i2c_blink <= '0';
end if; end if;
end if; end if;
when others => when others =>
blink_state <= '0'; led_i2c_blink <= '0';
end case; end case;
end if; end if;
...@@ -371,13 +365,42 @@ begin ...@@ -371,13 +365,42 @@ begin
begin begin
if rising_edge(clk20_vcxo_i) then if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then if (rst_n = '0') then
i2c_err_led <= '0'; led_i2c_err <= '0';
elsif (i2c_err = '1') then elsif (i2c_err_p = '1') then
i2c_err_led <= '1'; led_i2c_err <= '1';
end if; end if;
end if; end if;
end process p_i2c_err_led; end process p_i2c_err_led;
-- Process to light a LED in case of WDTO error
p_wdto_led : process (clk20_vcxo_i)
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
led_wdto <= '0';
elsif (i2c_wdto_p = '1') then
led_wdto <= '1';
end if;
end if;
end process p_wdto_led;
-- Pulse the first LEMO output on the card's front panel when a transfer is
-- finished. This is used to scope the bus in case of error
p_trig_oscilloscope : process (clk20_vcxo_i)
begin
if rising_edge(clk20_vcxo_i) then
if (rst_n = '0') then
i2c_tip_d0 <= '0';
trig_p <= '0';
else
i2c_tip_d0 <= i2c_tip;
trig_p <= (not i2c_tip) and (i2c_tip_d0);
end if;
end if;
end process p_trig_oscilloscope;
fpga_out_ttl_o(1) <= trig_p;
--============================================================================ --============================================================================
-- Instantiation and connection of the main Wishbone crossbar -- Instantiation and connection of the main Wishbone crossbar
--============================================================================ --============================================================================
...@@ -461,7 +484,8 @@ begin ...@@ -461,7 +484,8 @@ begin
bicolor_led_state( 7 downto 6) <= c_LED_OFF; bicolor_led_state( 7 downto 6) <= c_LED_OFF;
-- MULTICAST 0 -- MULTICAST 0
bicolor_led_state( 9 downto 8) <= c_LED_OFF; bicolor_led_state( 9 downto 8) <= c_LED_RED when led_wdto = '1' else
c_LED_OFF;
-- MULTICAST 1 -- MULTICAST 1
bicolor_led_state(11 downto 10) <= c_LED_OFF; bicolor_led_state(11 downto 10) <= c_LED_OFF;
...@@ -469,7 +493,7 @@ begin ...@@ -469,7 +493,7 @@ begin
-- I2C -- I2C
bicolor_led_state(13 downto 12) <= c_LED_GREEN when (led_i2c = '1') else bicolor_led_state(13 downto 12) <= c_LED_GREEN when (led_i2c = '1') else
c_LED_RED when (i2c_err_led = '1') else c_LED_RED when (led_i2c_err = '1') else
c_LED_OFF; c_LED_OFF;
-- State of TTL/TTL_N switch -- State of TTL/TTL_N switch
...@@ -534,14 +558,14 @@ begin ...@@ -534,14 +558,14 @@ begin
fpga_sfp_tx_disable_o <= 'Z'; fpga_sfp_tx_disable_o <= 'Z';
-- Pulse outputs and pulse LEDs -- Pulse outputs and pulse LEDs
fpga_oe_o <= '0'; fpga_oe_o <= '1';
fpga_blo_oe_o <= '0'; fpga_blo_oe_o <= '0';
fpga_trig_ttl_oe_o <= '0'; fpga_trig_ttl_oe_o <= '1';
fpga_inv_oe_o <= '0'; fpga_inv_oe_o <= '0';
pulse_front_led_n_o <= (others => '0'); pulse_front_led_n_o <= (others => '1');
pulse_rear_led_n_o <= (others => '0'); pulse_rear_led_n_o <= (others => '1');
fpga_out_ttl_o <= (others => '0'); fpga_out_ttl_o(6 downto 2) <= (others => '0');
fpga_trig_blo_o <= (others => '0'); fpga_trig_blo_o <= (others => '0');
inv_out_o <= (others => '0'); inv_out_o <= (others => '0');
...@@ -551,3 +575,7 @@ begin ...@@ -551,3 +575,7 @@ begin
fpga_prom_mosi_o <= '0'; fpga_prom_mosi_o <= '0';
end behav; end behav;
--==============================================================================
-- architecture end
--==============================================================================
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