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Conv TTL Blocking - Gateware
Commit bb4f03fc authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Adds updated project with settings from tcl scrip also added. Top module… 

Adds updated project with settings from tcl scrip also added. Top module modified to have correct LED output
parent 44d1350c
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Showing with 733 additions and 787 deletions
conv-common-gw @ 0026c3da
Subproject commit cba9c6a65dc59c0d2b16eac8ac9d9b8c707d536f
Subproject commit 0026c3da632437baef322fdb1bbca3898f375fc9
sim/Release/burst_ctrl_tb.vhd
View file @ bb4f03fc
......@@ -89,10 +89,8 @@ architecture behav of testbench is
generic
(
g_pwidth : natural range 2 to 40 := 5;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 18;
g_1_pulse_energ :in unsigned (15 downto 0);
g_max_temp_rise :in unsigned (39 downto 0)
g_1_pulse_temp_rise :in unsigned (15 downto 0);
g_max_temp :in unsigned (39 downto 0)
);
port
(
......@@ -169,11 +167,10 @@ architecture behav of testbench is
generic map
(
g_pwidth => 5,
g_duty_cycle_div => 100,
g_1_pulse_energ => x"2670",
--g_max_temp_rise => x"00000F4240" --10^6
g_1_pulse_temp_rise => x"1388",
--g_max_temp => x"00000F4240" --10^6
g_max_temp_rise => x"02540BE400" --10^10
g_max_temp => x"02540BE400" --10^10
)
port map(
clk_i => clk_20,
......@@ -205,7 +202,7 @@ architecture behav of testbench is
p_ran_gen : process
variable seed1, seed2: positive := 1; -- seed values for random generator
variable rand: real; -- random real-number value in range 0 to 1.0
variable range_of_rand : real := 10000.0; -- the range of random values created will be 0 to +1000.
variable range_of_rand : real := 1000.0; -- the range of random values created will be 0 to +10000.
begin
uniform(seed1, seed2, rand); -- generate random number
......@@ -243,13 +240,16 @@ end process p_ran_gen;
variable interval : time;-- := 1000 ns;
begin
--while t_sim1 < 5000000 ns loop
while true loop
while t_sim1 < 7000000 us loop
--while true loop
t_sim1 <= NOW - t_start;
if random_intervals then
interval := rand_num * 1 ns;
if interval < 250 ns then
interval := 250 ns;
end if;
else
interval := 250 ns;
interval := 500 ns;
end if;
burst_train <= '0';
wait for interval;
......@@ -258,29 +258,30 @@ end process p_ran_gen;
burst_train <= '0';
end loop;
-- while t_sim2 < 2000000 ns loop
-- t_sim2 <= NOW - t_sim1;
-- if random_intervals then
-- interval := rand_num * 1 ns;
-- else
-- interval := 5000 ns;
-- end if;
-- burst_train <= '0';
-- wait for interval;
-- burst_train <= '1';
-- wait for 250 ns;
-- burst_train <= '0';
-- end loop;
while t_sim2 < 800000 us loop
t_sim2 <= NOW - t_sim1;
if random_intervals then
interval := rand_num * 1 ns;
else
interval := 5000 ns;
end if;
burst_train <= '0';
wait for interval;
burst_train <= '1';
wait for 250 ns;
burst_train <= '0';
end loop;
end process p_stim_burst1;
-- p_write_output : process (temp_rise_counter)
-- file F : text open write_mode is "\\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\sim\Release\temp_rise_counter.txt";
-- file F : text open write_mode is "C:\Users\debouhir\work\CONV-TTL-BLO\conv-ttl-blo\conv-ttl-blo-gw\sim\Release\temp_rise_counter.txt";
-- variable L : line;
-- begin
-- write (L, NOW, left, 10);
-- write (L, temp_rise_counter, left, 6);
-- write (L, NOW, left, 30);
-- write (L, to_integer((temp_rise_counter (19 downto 0))), left, 50);
-- write (L, to_integer((temp_rise_counter (39 downto 20))), left, 50);
-- writeline (F, L);
-- end process p_write_output;
......
syn/Release/conv_ttl_blo.gise
View file @ bb4f03fc
......@@ -21,7 +21,9 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="conv_ttl_blo.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_NCD" xil_pn:name="conv_ttl_blo_guide.ncd" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
......
syn/Release/conv_ttl_blo.tcl
View file @ bb4f03fc
......@@ -202,14 +202,14 @@ proc set_project_props {} {
puts "$myScript: Setting project properties..."
project set family "Virtex7"
project set device "xc7vx330t"
project set package "ffg1157"
project set family "Spartan6"
project set device "xc6slx45t"
project set package "fgg484"
project set speed "-3"
project set top_level_module_type "HDL"
project set synthesis_tool "XST (VHDL/Verilog)"
project set simulator "ISim (VHDL/Verilog)"
project set "Preferred Language" "VHDL"
project set "Preferred Language" "Verilog"
project set "Enable Message Filtering" "false"
}
......@@ -256,11 +256,13 @@ proc add_source_files {} {
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_word_packer.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_shiftreg_fifo.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/inferred_async_fifo.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/inferred_sync_fifo.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd"
xfile add "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
......@@ -410,18 +412,10 @@ proc set_process_props {} {
puts "$myScript: setting process properties..."
project set "Compiled Library Directory" "C:/modeltech64_10.1c/win64"
project set "Use DSP Block" "Auto" -process "Synthesize - XST"
project set "DCI Update Mode" "As Required" -process "Generate Programming File"
project set "Enable Cyclic Redundancy Checking (CRC)" "true" -process "Generate Programming File"
project set "Configuration Rate" "3" -process "Generate Programming File"
project set "Compiled Library Directory" "\$XILINX/<language>/<simulator>"
project set "Global Optimization" "Off" -process "Map"
project set "Pack I/O Registers/Latches into IOBs" "Off" -process "Map"
project set "Place And Route Mode" "Route Only" -process "Place & Route"
project set "Number of Clock Buffers" "32" -process "Synthesize - XST"
project set "Max Fanout" "100000" -process "Synthesize - XST"
project set "Use Clock Enable" "Auto" -process "Synthesize - XST"
project set "Use Synchronous Reset" "Auto" -process "Synthesize - XST"
project set "Use Synchronous Set" "Auto" -process "Synthesize - XST"
project set "Regenerate Core" "Under Current Project Setting" -process "Regenerate Core"
project set "Filter Files From Compile Order" "true"
project set "Last Applied Goal" "Balanced"
......@@ -452,7 +446,7 @@ proc set_process_props {} {
project set "Optimization Effort" "Normal" -process "Synthesize - XST"
project set "Resource Sharing" "true" -process "Synthesize - XST"
project set "Shift Register Extraction" "true" -process "Synthesize - XST"
project set "User Browsed Strategy Files" "C:/Xilinx/14.7/ISE_DS/ISE/data/default.xds"
project set "User Browsed Strategy Files" ""
project set "VHDL Source Analysis Standard" "VHDL-93"
project set "Analysis Effort Level" "Standard" -process "Analyze Power Distribution (XPower Analyzer)"
project set "Analysis Effort Level" "Standard" -process "Generate Text Power Report"
......@@ -466,22 +460,11 @@ proc set_process_props {} {
project set "Setting Output File" "" -process "Generate Text Power Report"
project set "Produce Verbose Report" "false" -process "Generate Text Power Report"
project set "Other XPWR Command Line Options" "" -process "Generate Text Power Report"
project set "Place MultiBoot Settings into Bitstream" "false" -process "Generate Programming File"
project set "Revision Select" "00" -process "Generate Programming File"
project set "Revision Select Tristate" "Disable" -process "Generate Programming File"
project set "BPI Sync Mode" "Disable" -process "Generate Programming File"
project set "ICAP Select" "Auto" -process "Generate Programming File"
project set "SPI 32-bit Addressing" "No" -process "Generate Programming File"
project set "Set SPI Configuration Bus Width" "1" -process "Generate Programming File"
project set "Use SPI Falling Edge" "No" -process "Generate Programming File"
project set "Watchdog Timer Mode" "Off" -process "Generate Programming File"
project set "Enable External Master Clock" "Disable" -process "Generate Programming File"
project set "Encrypt Bitstream" "false" -process "Generate Programming File"
project set "User Access Register Value" "None" -process "Generate Programming File"
project set "JTAG to XADC Connection" "Enable" -process "Generate Programming File"
project set "Other Bitgen Command Line Options" "" -process "Generate Programming File"
project set "Essential Bits" "false" -process "Generate Programming File"
project set "Other Bitgen Command Line Options" "-g next_config_register_write:Disable" -process "Generate Programming File"
project set "Maximum Signal Name Length" "20" -process "Generate IBIS Model"
project set "Show All Models" "false" -process "Generate IBIS Model"
project set "VCCAUX Voltage Level" "2.5V" -process "Generate IBIS Model"
project set "Disable Detailed Package Model Insertion" "false" -process "Generate IBIS Model"
project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK with Bitstream"
project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK without Bitstream"
......@@ -497,37 +480,41 @@ proc set_process_props {} {
project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Post-Synthesis"
project set "Ignore User Timing Constraints" "false" -process "Place & Route"
project set "Other Place & Route Command Line Options" "" -process "Place & Route"
project set "BPI Reads Per Page" "1" -process "Generate Programming File"
project set "Configuration Clk (Configuration Pins)" "Pull Up" -process "Generate Programming File"
project set "Use DSP Block" "Auto" -process "Synthesize - XST"
project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File"
project set "Disable JTAG Connection" "false" -process "Generate Programming File"
project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File"
project set "Enable External Master Clock" "false" -process "Generate Programming File"
project set "Create ASCII Configuration File" "false" -process "Generate Programming File"
project set "Create Binary Configuration File" "true" -process "Generate Programming File"
project set "Create Bit File" "true" -process "Generate Programming File"
project set "Enable BitStream Compression" "false" -process "Generate Programming File"
project set "Run Design Rules Checker (DRC)" "true" -process "Generate Programming File"
project set "Enable Cyclic Redundancy Checking (CRC)" "true" -process "Generate Programming File"
project set "Create IEEE 1532 Configuration File" "false" -process "Generate Programming File"
project set "Create ReadBack Data Files" "false" -process "Generate Programming File"
project set "Configuration Pin Init" "Pull Up" -process "Generate Programming File"
project set "Configuration Pin M0" "Pull Up" -process "Generate Programming File"
project set "Configuration Pin M1" "Pull Up" -process "Generate Programming File"
project set "Configuration Pin M2" "Pull Up" -process "Generate Programming File"
project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File"
project set "Power Down Device if Over Safe Temperature" "false" -process "Generate Programming File"
project set "Place MultiBoot Settings into Bitstream" "false" -process "Generate Programming File"
project set "Configuration Rate" "2" -process "Generate Programming File"
project set "Set SPI Configuration Bus Width" "1" -process "Generate Programming File"
project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File"
project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File"
project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File"
project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File"
project set "Unused IOB Pins" "Pull Down" -process "Generate Programming File"
project set "Watchdog Timer Value" "0x1FFF" -process "Generate Programming File"
project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File"
project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File"
project set "Done (Output Events)" "Default (4)" -process "Generate Programming File"
project set "Drive Done Pin High" "false" -process "Generate Programming File"
project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File"
project set "Wait for DCI Match (Output Events)" "Auto" -process "Generate Programming File"
project set "Wait for PLL Lock (Output Events)" "No Wait" -process "Generate Programming File"
project set "Wait for DCM and PLL Lock (Output Events)" "Default (NoWait)" -process "Generate Programming File"
project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File"
project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File"
project set "Enable Internal Done Pipe" "true" -process "Generate Programming File"
project set "Enable Internal Done Pipe" "false" -process "Generate Programming File"
project set "Drive Awake Pin During Suspend/Wake Sequence" "false" -process "Generate Programming File"
project set "Enable Suspend/Wake Global Set/Reset" "false" -process "Generate Programming File"
project set "Enable Multi-Pin Wake-Up Suspend Mode" "false" -process "Generate Programming File"
project set "GTS Cycle During Suspend/Wakeup Sequence" "4" -process "Generate Programming File"
project set "GWE Cycle During Suspend/Wakeup Sequence" "5" -process "Generate Programming File"
project set "Wakeup Clock" "Startup Clock" -process "Generate Programming File"
project set "Allow Logic Optimization Across Hierarchy" "false" -process "Map"
project set "Maximum Compression" "false" -process "Map"
project set "Generate Detailed MAP Report" "true" -process "Map"
......@@ -552,9 +539,11 @@ proc set_process_props {} {
project set "Report Type" "Verbose Report" -process "Generate Post-Map Static Timing"
project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Map Static Timing"
project set "Report Unconstrained Paths" "" -process "Generate Post-Map Static Timing"
project set "Number of Clock Buffers" "16" -process "Synthesize - XST"
project set "Add I/O Buffers" "true" -process "Synthesize - XST"
project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST"
project set "Keep Hierarchy" "No" -process "Synthesize - XST"
project set "Max Fanout" "100000" -process "Synthesize - XST"
project set "Register Balancing" "No" -process "Synthesize - XST"
project set "Register Duplication" "true" -process "Synthesize - XST"
project set "Library for Verilog Sources" "" -process "Synthesize - XST"
......@@ -580,14 +569,16 @@ proc set_process_props {} {
project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST"
project set "Power Reduction" "false" -process "Synthesize - XST"
project set "Read Cores" "true" -process "Synthesize - XST"
project set "LUT-FF Pairs Utilization Ratio" "100" -process "Synthesize - XST"
project set "Use Clock Enable" "Auto" -process "Synthesize - XST"
project set "Use Synchronous Reset" "Auto" -process "Synthesize - XST"
project set "Use Synchronous Set" "Auto" -process "Synthesize - XST"
project set "Use Synthesis Constraints File" "true" -process "Synthesize - XST"
project set "Verilog Include Directories" "" -process "Synthesize - XST"
project set "Verilog Macros" "" -process "Synthesize - XST"
project set "Work Directory" "G:/Users/d/debouhir/Documents/Projects/CONV-TTL-BlO/repo/conv-ttl-blo-gw/syn/Release/xst" -process "Synthesize - XST"
project set "Work Directory" "C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/syn/Release/xst" -process "Synthesize - XST"
project set "Write Timing Constraints" "false" -process "Synthesize - XST"
project set "Other XST Command Line Options" "" -process "Synthesize - XST"
project set "Timing Mode" "Non Timing Driven" -process "Map"
project set "Timing Mode" "Performance Evaluation" -process "Map"
project set "Generate Asynchronous Delay Report" "false" -process "Place & Route"
project set "Generate Clock Region Report" "false" -process "Place & Route"
project set "Generate Post-Place & Route Power Report" "false" -process "Place & Route"
......@@ -595,6 +586,7 @@ proc set_process_props {} {
project set "Power Reduction" "false" -process "Place & Route"
project set "Place & Route Effort Level (Overall)" "High" -process "Place & Route"
project set "Auto Implementation Compile Order" "true"
project set "Equivalent Register Removal" "true" -process "Map"
project set "Placer Extra Effort" "None" -process "Map"
project set "Power Activity File" "" -process "Map"
project set "Register Duplication" "Off" -process "Map"
......@@ -603,21 +595,20 @@ proc set_process_props {} {
project set "RAM Style" "Auto" -process "Synthesize - XST"
project set "Maximum Number of Lines in Report" "1000" -process "Generate Text Power Report"
project set "MultiBoot: Insert IPROG CMD in the Bitfile" "Enable" -process "Generate Programming File"
project set "Watchdog Timer Value" "0x00000000" -process "Generate Programming File"
project set "AES Initial Vector" "" -process "Generate Programming File"
project set "HMAC Key (Hex String)" "" -process "Generate Programming File"
project set "Encrypt Key Select" "BBRAM" -process "Generate Programming File"
project set "AES Key (Hex String)" "" -process "Generate Programming File"
project set "Input Encryption Key File" "" -process "Generate Programming File"
project set "Output File Name" "conv_ttl_blo" -process "Generate IBIS Model"
project set "Timing Mode" "Performance Evaluation" -process "Place & Route"
project set "Cycles for First BPI Page Read" "1" -process "Generate Programming File"
project set "Fallback Reconfiguration" "Disable" -process "Generate Programming File"
project set "Create Binary Configuration File" "true" -process "Generate Programming File"
project set "Enable Debugging of Serial Mode BitStream" "false" -process "Generate Programming File"
project set "Create Logic Allocation File" "false" -process "Generate Programming File"
project set "Create Mask File" "false" -process "Generate Programming File"
project set "Starting Address for Fallback Configuration" "None" -process "Generate Programming File"
project set "Retry Configuration if CRC Error Occurs" "true" -process "Generate Programming File"
project set "MultiBoot: Starting Address for Next Configuration" "0x0b170000" -process "Generate Programming File"
project set "MultiBoot: Starting Address for Golden Configuration" "0x0b000044" -process "Generate Programming File"
project set "MultiBoot: Use New Mode for Next Configuration" "true" -process "Generate Programming File"
project set "MultiBoot: User-Defined Register for Failsafe Scheme" "0x0000" -process "Generate Programming File"
project set "Setup External Master Clock Division" "1" -process "Generate Programming File"
project set "Allow SelectMAP Pins to Persist" "false" -process "Generate Programming File"
project set "Mask Pins for Multi-Pin Wake-Up Suspend Mode" "0x00" -process "Generate Programming File"
project set "Enable Multi-Threading" "2" -process "Map"
project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Place & Route Static Timing"
project set "Move First Flip-Flop Stage" "true" -process "Synthesize - XST"
......@@ -626,8 +617,14 @@ proc set_process_props {} {
project set "Safe Implementation" "No" -process "Synthesize - XST"
project set "Power Activity File" "" -process "Place & Route"
project set "Extra Effort (Highest PAR level only)" "None" -process "Place & Route"
project set "MultiBoot: Next Configuration Mode" "001" -process "Generate Programming File"
project set "Encrypt Bitstream" "false" -process "Generate Programming File"
project set "Enable Multi-Threading" "Off" -process "Place & Route"
project set "Functional Model Target Language" "VHDL" -process "View HDL Source"
project set "AES Initial Vector" "" -process "Generate Programming File"
project set "Encrypt Key Select" "BBRAM" -process "Generate Programming File"
project set "AES Key (Hex String)" "" -process "Generate Programming File"
project set "Input Encryption Key File" "" -process "Generate Programming File"
project set "Functional Model Target Language" "Verilog" -process "View HDL Source"
project set "Change Device Speed To" "-3" -process "Generate Post-Place & Route Static Timing"
project set "Change Device Speed To" "-3" -process "Generate Post-Map Static Timing"
......
syn/Release/conv_ttl_blo.xise
View file @ bb4f03fc
This source diff could not be displayed because it is too large. You can view the blob instead.
top/Release/conv_ttl_blo.vhd
View file @ bb4f03fc
......@@ -493,10 +493,10 @@ begin
-----------------------------------------
-- LED outputs
--led_front_n_o <= not led_pulse;
led_front_n_o <= "101010";
--led_front_inv_n_o <= not led_inv_pulse;
led_front_inv_n_o <= "1010";
led_front_n_o <= not led_pulse;
--led_front_n_o <= "101010";
led_front_inv_n_o <= not led_inv_pulse;
--led_front_inv_n_o <= "1010";
led_rear_n_o <= not led_pulse;
......
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