Skip to content

C
Conv TTL Blocking - Gateware
Commit b4f23ad0 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
Browse files
Options

Changing folder structure 

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent f68e5997
Hide whitespace changes
Inline Side-by-side
Showing with 3928 additions and 0 deletions
.gitmodules 0 → 100644
View file @ b4f23ad0
[submodule "ip_cores/general-cores"]
path = ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
general-cores @ 97b49256
Subproject commit 97b492569df26743bc75b4e8ae57a0aecca5a1f4
top/Release/Manifest.py 0 → 100644
View file @ b4f23ad0
files = [
"conv_ttl_blo.ucf",
"conv_ttl_blo.vhd"
]
modules = {
"local" : [
"../../ip_cores/general-cores",
"../../reset_gen",
"../rtl",
"../../vbcp_wb",
"../../ctb_pulse_gen",
"../../multiboot/",
"../../rtm_detector",
"../../bicolor_led_ctrl",
"../../../../../ip_cores/general-cores"
]
}
top/Release/conv_ttl_blo.ucf 0 → 100644
View file @ b4f23ad0
##--==============================================================================
##-- CERN (BE-CO-HT)
##-- Glitch filter with selectable length
##--==============================================================================
##--
##-- author: Theodor Stana (t.stana@cern.ch)
##-- Carlos-Gil Soriano
##--
##-- date of creation: 2013-04-26
##--
##-- version: 1.0
##--
##-- description:
##-- This file contains the pin definitions for the CONV-TTL-BLO FPGA. The pin
##-- names reflect those of net names at the schematic level. To keep to CERN
##-- coding standards (http://www.ohwr.org/documents/24) and make the code more
##-- readable, the pin names have been lowercased and the pin type is indicated
##-- by its suffix. The suffix "_i" indicates an input pin, "_o" an output pin
##-- and "_b" a bidirectional pin.
##--
##-- An example of net name change is given below:
##-- LED_WR_OWNADDR_I2C -> led_wr_ownaddr_i2c_o
##--
##-- Apart from this, some pins have been renamed completely and do not resemble
##-- the schematics. These pins are:
##-- TTL/INV_TTL_N -> ttl_switch_n_i
##--
##-- dependencies:
##--
##-- references:
##--
##--==============================================================================
##-- GNU LESSER GENERAL PUBLIC LICENSE
##--==============================================================================
##-- This source file is free software; you can redistribute it and/or modify it
##-- under the terms of the GNU Lesser General Public License as published by the
##-- Free Software Foundation; either version 2.1 of the License, or (at your
##-- option) any later version. This source is distributed in the hope that it
##-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
##-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
##-- See the GNU Lesser General Public License for more details. You should have
##-- received a copy of the GNU Lesser General Public License along with this
##-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##--==============================================================================
##-- last changes:
##-- 2013-04-26 Theodor Stana t.stana@cern.ch File modified
##--==============================================================================
##-- TODO: -
##--==============================================================================
##-----------------------------------------------------------------------------
##-- Default attributes
##--
##-- IOSTANDARD = "LVCMOS25"
##-- SLEW = "SLOW"
##-- DRIVE = "12"
##-----------------------------------------------------------------------------
#NET "rst_i" LOC = N20;
#NET "rst_i" IOSTANDARD = "LVCMOS33";
#NET "fpga_sysreset_n_i" LOC = L20;
NET "mr_n_o" LOC = T22;
NET "mr_n_o" IOSTANDARD = LVCMOS33;
# NET "clk20_vcxo_i" LOC = E16;
# NET "clk20_vcxo_i" TNM_NET=clk20_vcxo_i;
# TIMESPEC TSCLK20 = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %;
NET "fpga_clk_p_i" LOC = H12;
NET "fpga_clk_n_i" LOC = G11;
##=============================================================================
##-- FRONT PANEL TTLs
##=============================================================================
##-----------------------------------------------------------------------------
##-- Status LEDs
##-----------------------------------------------------------------------------
NET "led_ctrl0_o" LOC = M18;
NET "led_ctrl0_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl0_oen_o" LOC = T20;
NET "led_ctrl0_oen_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_o" LOC = M17;
NET "led_ctrl1_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_oen_o" LOC = U19;
NET "led_ctrl1_oen_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_2_0_o" LOC = P16;
NET "led_multicast_2_0_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_3_1_o" LOC = P17;
NET "led_multicast_3_1_o" IOSTANDARD = LVCMOS33;
NET "led_wr_gmt_ttl_ttln_o" LOC = N16;
NET "led_wr_gmt_ttl_ttln_o" IOSTANDARD = LVCMOS33;
NET "led_wr_link_syserror_o" LOC = R15;
NET "led_wr_link_syserror_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ok_syspw_o" LOC = R16;
NET "led_wr_ok_syspw_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ownaddr_i2c_o" LOC = N15;
NET "led_wr_ownaddr_i2c_o" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Front channel LEDs
##-----------------------------------------------------------------------------
NET "pulse_front_led_n_o[1]" LOC = H5;
NET "pulse_front_led_n_o[1]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[1]" DRIVE = 4;
NET "pulse_front_led_n_o[1]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[2]" LOC = J6;
NET "pulse_front_led_n_o[2]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[2]" DRIVE = 4;
NET "pulse_front_led_n_o[2]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[3]" LOC = K6;
NET "pulse_front_led_n_o[3]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[3]" DRIVE = 4;
NET "pulse_front_led_n_o[3]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[4]" LOC = K5;
NET "pulse_front_led_n_o[4]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[4]" DRIVE = 4;
NET "pulse_front_led_n_o[4]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[5]" LOC = M7;
NET "pulse_front_led_n_o[5]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[5]" DRIVE = 4;
NET "pulse_front_led_n_o[5]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[6]" LOC = M6;
NET "pulse_front_led_n_o[6]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[6]" DRIVE = 4;
NET "pulse_front_led_n_o[6]" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- Rear LEDs
##-----------------------------------------------------------------------------
NET "pulse_rear_led_n_o[1]" LOC = AB17;
NET "pulse_rear_led_n_o[1]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[1]" DRIVE = 4;
NET "pulse_rear_led_n_o[1]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[2]" LOC = AB19;
NET "pulse_rear_led_n_o[2]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[2]" DRIVE = 4;
NET "pulse_rear_led_n_o[2]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[3]" LOC = AA16;
NET "pulse_rear_led_n_o[3]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[3]" DRIVE = 4;
NET "pulse_rear_led_n_o[3]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[4]" LOC = AA18;
NET "pulse_rear_led_n_o[4]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[4]" DRIVE = 4;
NET "pulse_rear_led_n_o[4]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[5]" LOC = AB16;
NET "pulse_rear_led_n_o[5]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[5]" DRIVE = 4;
NET "pulse_rear_led_n_o[5]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[6]" LOC = AB18;
NET "pulse_rear_led_n_o[6]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[6]" DRIVE = 4;
NET "pulse_rear_led_n_o[6]" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- TTL trigger I/O
##-----------------------------------------------------------------------------
NET "fpga_input_ttl_n_i[1]" LOC = T2;
NET "fpga_input_ttl_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[2]" LOC = U3;
NET "fpga_input_ttl_n_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[3]" LOC = V5;
NET "fpga_input_ttl_n_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[4]" LOC = W4;
NET "fpga_input_ttl_n_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[5]" LOC = T6;
NET "fpga_input_ttl_n_i[5]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[5]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[6]" LOC = T3;
NET "fpga_input_ttl_n_i[6]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[6]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_out_ttl_o[1]" LOC = C1;
NET "fpga_out_ttl_o[1]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[2]" LOC = F2;
NET "fpga_out_ttl_o[2]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[3]" LOC = F5;
NET "fpga_out_ttl_o[3]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[4]" LOC = H4;
NET "fpga_out_ttl_o[4]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[5]" LOC = J4;
NET "fpga_out_ttl_o[5]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[6]" LOC = H2;
NET "fpga_out_ttl_o[6]" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Inverted TTL I/O
##-----------------------------------------------------------------------------
NET "inv_in_n_i[1]" LOC = V2;
NET "inv_in_n_i[1]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[2]" LOC = W3;
NET "inv_in_n_i[2]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[3]" LOC = Y2;
NET "inv_in_n_i[3]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[4]" LOC = AA2;
NET "inv_in_n_i[4]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_out_o[1]" LOC = J3;
NET "inv_out_o[1]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[2]" LOC = L3;
NET "inv_out_o[2]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[3]" LOC = M3;
NET "inv_out_o[3]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[4]" LOC = P2;
NET "inv_out_o[4]" IOSTANDARD = LVCMOS33;
##=============================================================================
##-- RTM signals
##=============================================================================
##-----------------------------------------------------------------------------
##-- Blocking I/O
##-----------------------------------------------------------------------------
NET "fpga_blo_in_i[1]" LOC = Y9;
NET "fpga_blo_in_i[1]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[2]" LOC = AA10;
NET "fpga_blo_in_i[2]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[3]" LOC = W12;
NET "fpga_blo_in_i[3]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[4]" LOC = AA6;
NET "fpga_blo_in_i[4]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[5]" LOC = Y7;
NET "fpga_blo_in_i[5]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[6]" LOC = AA8;
NET "fpga_blo_in_i[6]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[1]" LOC = W9;
NET "fpga_trig_blo_o[1]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[2]" LOC = T10;
NET "fpga_trig_blo_o[2]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[3]" LOC = V7;
NET "fpga_trig_blo_o[3]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[4]" LOC = U9;
NET "fpga_trig_blo_o[4]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[5]" LOC = T8;
NET "fpga_trig_blo_o[5]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[6]" LOC = R9;
NET "fpga_trig_blo_o[6]" IOSTANDARD = "LVCMOS33";
##=============================================================================
##-- VME CONNECTOR SIGNALS
##=============================================================================
##-----------------------------------------------------------------------------
##-- I2C lines
##-----------------------------------------------------------------------------
NET "scl_i" LOC = F19;
NET "scl_i" IOSTANDARD = LVCMOS33;
NET "scl_o" LOC = E20;
NET "scl_o" IOSTANDARD = LVCMOS33;
NET "scl_o" DRIVE = 4;
NET "scl_oe_o" LOC = H18;
NET "scl_oe_o" IOSTANDARD = LVCMOS33;
NET "scl_oe_o" DRIVE = 4;
# NET "scl_oe_o" PULLDOWN;
NET "sda_i" LOC = G20;
NET "sda_i" IOSTANDARD = LVCMOS33;
NET "sda_o" LOC = F20;
NET "sda_o" IOSTANDARD = LVCMOS33;
NET "sda_o" SLEW = FAST;
NET "sda_o" DRIVE = 4;
# NET "sda_o" PULLUP;
NET "sda_oe_o" LOC = J19;
NET "sda_oe_o" IOSTANDARD = LVCMOS33;
NET "sda_oe_o" SLEW = FAST;
NET "sda_oe_o" DRIVE = 4;
# NET "sda_oe_o" PULLDOWN;
##-----------------------------------------------------------------------------
##-- Geographical Address
##-----------------------------------------------------------------------------
NET "fpga_ga_i[0]" LOC = H20;
NET "fpga_ga_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[1]" LOC = J20;
NET "fpga_ga_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[2]" LOC = K19;
NET "fpga_ga_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[3]" LOC = K20;
NET "fpga_ga_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[4]" LOC = L19;
NET "fpga_ga_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_gap_i" LOC = H19;
NET "fpga_gap_i" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- ROM memory
##-----------------------------------------------------------------------------
NET "fpga_prom_cclk_o" LOC = Y20;
NET "fpga_prom_cclk_o" IOSTANDARD = "LVCMOS33";
NET "fpga_prom_cso_b_n_o" LOC = AA3;
NET "fpga_prom_cso_b_n_o" IOSTANDARD = "LVCMOS33";
NET "fpga_prom_miso_i" LOC = AA20;
NET "fpga_prom_miso_i" IOSTANDARD = "LVCMOS33";
NET "fpga_prom_mosi_o" LOC = AB20;
NET "fpga_prom_mosi_o" IOSTANDARD = "LVCMOS33";
###=============================================================================
###-- WHITE RABBIT
###=============================================================================
###-----------------------------------------------------------------------------
###-- Thermo for UID
###-----------------------------------------------------------------------------
#NET "thermometer_b" LOC = B1;
#NET "thermometer_b" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- DAC control
###-----------------------------------------------------------------------------
#NET "fpga_plldac1_din_o" LOC = AB14;
#NET "fpga_plldac1_din_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac1_sclk_o" LOC = AA14;
#NET "fpga_plldac1_sclk_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac1_sync_n_o" LOC = AB15;
#NET "fpga_plldac1_sync_n_o" IOSTANDARD = LVCMOS33;
#
#NET "fpga_plldac2_din_o" LOC = W14;
#NET "fpga_plldac2_din_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac2_sclk_o" LOC = Y14;
#NET "fpga_plldac2_sclk_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac2_sync_n_o" LOC = W13;
#NET "fpga_plldac2_sync_n_o" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- SFP connection
###-----------------------------------------------------------------------------
##NET "fpga_sfp_los_i" LOC = G3;
## NET "fpga_sfp_los_i" IOSTANDARD = "LVCMOS33";
##NET "fpga_sfp_mod_def0_i" LOC = K8;
## NET "fpga_sfp_mod_def0_i" IOSTANDARD = "LVCMOS33";
##NET "fpga_sfp_rate_select_o" LOC = C4;
## NET "fpga_sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
#NET "fpga_sfp_mod_def1_b" LOC = G4;
#NET "fpga_sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
#
#NET "fpga_sfp_mod_def2_b" LOC = F3;
#NET "fpga_sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
##NET "fpga_sfp_tx_disable_o" LOC = E4;
## NET "fpga_sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
##NET "fpga_sfp_tx_fault_i" LOC = D2;
## NET "fpga_sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
###-----------------------------------------------------------------------------
###-- FPGA MGT lines
###-----------------------------------------------------------------------------
#NET "fpga_mgt_clk0_p_i" LOC = A10;
#NET "fpga_mgt_clk0_n_i" LOC = B10;
#
#NET "mgt_sfp_rx0_p_i" LOC = D7;
#NET "mgt_sfp_rx0_n_i" LOC = C7;
#
#NET "mgt_sfp_tx0_p_o" LOC = B6;
#NET "mgt_sfp_tx0_n_o" LOC = A6;
###=============================================================================
###-- ADDITIONAL PINS
###=============================================================================
NET "fpga_oe_o" LOC = R3;
NET "fpga_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_oe_o" DRIVE = 4;
NET "fpga_oe_o" SLEW = QUIETIO;
NET "fpga_blo_oe_o" LOC = P5;
NET "fpga_blo_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_blo_oe_o" DRIVE = 4;
NET "fpga_blo_oe_o" SLEW = QUIETIO;
NET "fpga_trig_ttl_oe_o" LOC = N3;
NET "fpga_trig_ttl_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_trig_ttl_oe_o" DRIVE = 4;
NET "fpga_trig_ttl_oe_o" SLEW = QUIETIO;
NET "fpga_inv_oe_o" LOC = P6;
NET "fpga_inv_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_inv_oe_o" DRIVE = 4;
NET "fpga_inv_oe_o" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- Configuration Switches
##-----------------------------------------------------------------------------
NET "extra_switch_n_i[1]" LOC = F22;
NET "extra_switch_n_i[1]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[2]" LOC = G22;
NET "extra_switch_n_i[2]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[3]" LOC = H21;
NET "extra_switch_n_i[3]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[4]" LOC = H22;
NET "extra_switch_n_i[4]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[5]" LOC = J22;
NET "extra_switch_n_i[5]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[6]" LOC = K21;
NET "extra_switch_n_i[6]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[7]" LOC = K22;
NET "extra_switch_n_i[7]" IOSTANDARD = "LVCMOS33";
NET "ttl_switch_n_i" LOC = L22;
NET "ttl_switch_n_i" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Motherboard and piggyback IDs
##-----------------------------------------------------------------------------
NET "fpga_rtmm_n_i[0]" LOC = V21;
NET "fpga_rtmm_n_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[1]" LOC = V22;
NET "fpga_rtmm_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmm_n_i[2]" LOC = U22;
NET "fpga_rtmm_n_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[0]" LOC = W22;
NET "fpga_rtmp_n_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[1]" LOC = Y22;
NET "fpga_rtmp_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_rtmp_n_i[2]" LOC = Y21;
NET "fpga_rtmp_n_i[2]" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- General purpose
###-----------------------------------------------------------------------------
# NET "fpga_header_out_n_o[1]" LOC = F15;
# NET "fpga_header_out_n_o[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[2]" LOC = F16;
# NET "fpga_header_out_n_o[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[3]" LOC = F17;
# NET "fpga_header_out_n_o[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[4]" LOC = F14;
# NET "fpga_header_out_n_o[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[5]" LOC = H14;
# NET "fpga_header_out_n_o[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[6]" LOC = H13;
# NET "fpga_header_out_n_o[6]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[1]" LOC = A17;
# NET "fpga_header_in_n_i[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[2]" LOC = A18;
# NET "fpga_header_in_n_i[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[3]" LOC = B18;
# NET "fpga_header_in_n_i[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[4]" LOC = A19;
# NET "fpga_header_in_n_i[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[5]" LOC = A20;
# NET "fpga_header_in_n_i[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[6]" LOC = B20;
# NET "fpga_header_in_n_i[6]" IOSTANDARD = "LVCMOS33";
top/Release/conv_ttl_blo.vhd 0 → 100644
View file @ b4f23ad0
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO
-- http://www.ohwr.org/projects/conv-ttl-blo
--------------------------------------------------------------------------------
--
-- unit name: conv_ttl_blo.vhd
--
-- author: Theodor-Adrian Stana (t.stana@cern.ch)
--
-- version: 1.0
--
-- description: Top entity of CONV-TTL-BLO
--
-- dependencies:
--
-- references:
-- [1] ELMA, Access to board data using SNMP and I2C
-- http://www.ohwr.org/documents/227
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use unisim.vcomponents.all;
use work.bicolor_led_ctrl_pkg.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
entity conv_ttl_blo is
generic
(
g_nr_ttl_chan : natural := 6;
g_nr_inv_chan : natural := 4
);
port
(
-- clk20_vcxo_i : in std_logic;
fpga_clk_p_i : in std_logic; --Using the 125MHz clock
fpga_clk_n_i : in std_logic;
-- LEDs
led_ctrl0_o : out std_logic;
led_ctrl0_oen_o : out std_logic;
led_ctrl1_o : out std_logic;
led_ctrl1_oen_o : out std_logic;
led_multicast_2_0_o : out std_logic;
led_multicast_3_1_o : out std_logic;
led_wr_gmt_ttl_ttln_o : out std_logic;
led_wr_link_syserror_o : out std_logic;
led_wr_ok_syspw_o : out std_logic;
led_wr_ownaddr_i2c_o : out std_logic;
-- I/Os for pulses
pulse_front_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
pulse_rear_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_input_ttl_n_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_out_ttl_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_blo_in_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_trig_blo_o : out std_logic_vector(g_nr_ttl_chan downto 1);
inv_in_n_i : in std_logic_vector(g_nr_inv_chan downto 1);
inv_out_o : out std_logic_vector(g_nr_inv_chan downto 1);
-- Output enable lines
fpga_oe_o : out std_logic;
fpga_blo_oe_o : out std_logic;
fpga_trig_ttl_oe_o : out std_logic;
fpga_inv_oe_o : out std_logic;
--TTL/INV_TTL_N
ttl_switch_n_i : in std_logic;
extra_switch_n_i : in std_logic_vector(7 downto 1);
-- Lines for the i2c_slave
scl_i : in std_logic;
scl_o : out std_logic;
scl_oe_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_oe_o : out std_logic;
fpga_ga_i : in std_logic_vector(4 downto 0);
fpga_gap_i : in std_logic;
-- Flash memory lines
fpga_prom_cclk_o : out std_logic;
fpga_prom_cso_b_n_o : out std_logic;
fpga_prom_mosi_o : out std_logic;
fpga_prom_miso_i : in std_logic;
-- It allows power sequencing of the 24V rail after a security delay
mr_n_o : out std_logic;
-- RTM identifiers, should match with the expected values
fpga_rtmm_n_i : in std_logic_vector(2 downto 0);
fpga_rtmp_n_i : in std_logic_vector(2 downto 0)
);
end conv_ttl_blo;
architecture behav of conv_ttl_blo is
--============================================================================
-- Type declarations
--============================================================================
type t_ttlbar_nosig_cnt is array (1 to g_nr_ttl_chan) of unsigned(13 downto 0);
type t_pulse_led_cnt is array (1 to g_nr_ttl_chan) of unsigned(22 downto 0);
--============================================================================
-- Constant declarations
--============================================================================
-- Firmware version
constant c_fwvers : std_logic_vector(15 downto 0) := x"0200";
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 2;
-----------------------------------------
-- Memory map
-- * all registers are word-addressable
-- * all registers are word-aligned
-----------------------------------------
-- CONV_REGS [000-040]
-- MULTIBOOT [040-080]
-----------------------------------------
-- slave order definitions
constant c_slv_conv_regs : natural := 0;
constant c_slv_multiboot : natural := 1;
-- base address definitions
constant c_addr_conv_regs : t_wishbone_address := x"00000000";
constant c_addr_multiboot : t_wishbone_address := x"00000040";
-- address mask definitions
constant c_mask_conv_regs : t_wishbone_address := x"00000FC0";
constant c_mask_multiboot : t_wishbone_address := x"00000FC0";
-- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_conv_regs => c_addr_conv_regs,
c_slv_multiboot => c_addr_multiboot
);
-- masks constant for Wishbone crossbar
constant c_masks : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_conv_regs => c_mask_conv_regs,
c_slv_multiboot => c_mask_multiboot
);
--============================================================================
-- Component declarations
--============================================================================
-- Reset generator component
-- (use: global reset generation, output reset generation)
component reset_gen is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time : positive := 5_000_000
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
rst_n_o : out std_logic
);
end component reset_gen;
-- Pulse generator component
-- (use: output pulse generation, pulse status LEDs)
component ctb_pulse_gen is
generic
(
-- Pulse width, in number of clk_i cycles
g_pwidth : natural := 15;
-- Glitch filter length:
-- g_gf_len=1 => trigger width should be > 1 clk_i cycle
-- g_gf_len=2 => trigger width should be > 2 clk_i cycles
-- etc.
g_gf_len : natural := 4
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Glitch filter enable input
-- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
-- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
gf_en_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_i : in std_logic;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: g_gf_len+3 clk_i cycles
pulse_o : out std_logic
);
end component ctb_pulse_gen;
-- I2C bridge
-- (use: convert I2C transfers into WB transfers on memmapped registers)
component vbcp_wb is
port
(
-- Clock, reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C lines
sda_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
-- I2C address
i2c_addr_i : in std_logic_vector(6 downto 0);
-- Transfer In Progress (TIP) and Error outputs
-- TIP : '1' when the I2C slave detects a matching I2C address, thus a
-- transfer is in progress
-- '0' when idle
-- ERR : '1' when the SysMon attempts to access an invalid WB slave
-- '0' when idle
tip_o : out std_logic;
err_o : out std_logic;
-- Wishbone master signals
wbm_stb_o : out std_logic;
wbm_cyc_o : out std_logic;
wbm_sel_o : out std_logic_vector(3 downto 0);
wbm_we_o : out std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_adr_o : out std_logic_vector(31 downto 0);
wbm_ack_i : in std_logic;
wbm_rty_i : in std_logic;
wbm_err_i : in std_logic
);
end component vbcp_wb;
-- Xilinx MultiBoot component
-- (use: remote reprogramming of the FPGA)
component xil_multiboot is
port
(
-- Clock and reset input ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone ports
wbs_i : in t_wishbone_slave_in;
wbs_o : out t_wishbone_slave_out;
-- SPI ports
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end component xil_multiboot;
-- RTM detector component
-- (use: detect the presence of an RTM/P module)
component rtm_detector is
port
(
rtmm_i : in std_logic_vector(2 downto 0);
rtmp_i : in std_logic_vector(2 downto 0);
rtmm_ok_o : out std_logic;
rtmp_ok_o : out std_logic
);
end component rtm_detector;
-- Converter board control registers
component conv_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID register'
conv_regs_id_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'fwvers' in reg: 'Status register'
conv_regs_sr_fwvers_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'switches' in reg: 'Status register'
conv_regs_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status register'
conv_regs_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Port for BIT field: 'Reset unlock bit' in reg: 'Control register'
conv_regs_cr_rst_unlock_o : out std_logic;
-- Port for BIT field: 'Reset bit' in reg: 'Control register'
conv_regs_cr_rst_o : out std_logic
);
end component conv_regs;
--============================================================================
-- Signal declarations
--============================================================================
-- Clock signals
signal clk125 : std_logic;
signal clk_50, clk_buf_50 : std_logic;
signal clk_200, clk_buf_200 : std_logic;
signal clk_250, clk_buf_250 : std_logic;
signal pll_fb_in, pll_fb_out : std_logic;
signal pll_locked : std_logic;
-- Reset signals
signal rst_n, rst : std_logic;
-- RTM detection signals
signal rtmm, rtmp : std_logic_vector(2 downto 0);
signal rtmm_ok, rtmp_ok : std_logic;
-- Signals to/from converter system registers component
signal rtm_lines : std_logic_vector(5 downto 0);
signal switches_n : std_logic_vector(7 downto 0);
-- Signals for pulse generation triggers
signal trig_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_inv : std_logic_vector(g_nr_inv_chan downto 1);
signal trig_ttl_a, trig_blo_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_synced_edge : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_synced : std_logic_vector(g_nr_ttl_chan downto 1);
-- TTL-BAR lack of signal counter
signal ttlbar_nosig_cnt : t_ttlbar_nosig_cnt;
signal ttlbar_nosig_n : std_logic_vector(g_nr_ttl_chan downto 1);
-- Temporary signal for blocking and TTL pulse outputs
signal pulse_outputs : std_logic_vector(g_nr_ttl_chan downto 1);
signal blo_ch_en : std_logic_vector(g_nr_ttl_chan downto 1);
-- Temporary signal for inverted-TTL pulse outputs
signal inv_outputs : std_logic_vector(g_nr_inv_chan downto 1);
-- Pulse status LED signals
signal front_led_en : std_logic_vector(g_nr_ttl_chan downto 1);
signal rear_led_en : std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse_leds : std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse_led_cnt : t_pulse_led_cnt;
-- Output enable signals
signal oe, ttl_oe, blo_oe, inv_oe : std_logic;
-- Signal for controlling the bicolor LED matrix
signal bicolor_led_state : std_logic_vector(23 downto 0);
signal tmp_pulse : std_logic;
-- Wishbone crossbar signals
signal xbar_slave_in : t_wishbone_slave_in_array (c_nr_masters - 1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_nr_masters - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_nr_slaves - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array(c_nr_slaves - 1 downto 0);
-- I2C bridge signals
signal vbcp_tip : std_logic;
signal vbcp_err : std_logic;
signal i2c_err_led : std_logic;
signal i2c_up : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0);
signal led_i2c : std_logic;
signal led_i2c_clkdiv : unsigned(22 downto 0);
signal led_i2c_cnt : unsigned( 2 downto 0);
signal blink_state : std_logic;
begin
--============================================================================
-- Generate 125 MHz global signal from differential lines
--============================================================================
cmp_125_diff_buf : IBUFGDS
generic map
(
DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE
)
port map
(
I => fpga_clk_p_i,
IB => fpga_clk_n_i,
O => clk125
);
--============================================================================
-- Internal and external reset generation
--============================================================================
-- Configure reset generator for 96ms power-on reset
cmp_reset_gen : reset_gen
generic map
(
-- Reset time: 12 * 8ns * (10**6) = 96 ms
g_reset_time => 12*(10**6)
)
port map
(
clk_i => clk125,
rst_i => '0',
rst_n_o => rst_n
);
-- rst <= not rst_n;
mr_n_o <= rst_n;
--============================================================================
-- I2C bridge logic
--============================================================================
-- Set the I2C address signal according to ELMA protocol [1]
i2c_addr <= "10" & fpga_ga_i;
-- Instantiate VBCP bridge component
cmp_vbcp_bridge : vbcp_wb
port map
(
-- Clock, reset
clk_i => clk125,
rst_n_i => rst_n,
-- I2C lines
sda_en_o => sda_oe_o,
sda_i => sda_i,
sda_o => sda_o,
scl_en_o => scl_oe_o,
scl_i => scl_i,
scl_o => scl_o,
-- I2C address and status
i2c_addr_i => i2c_addr,
-- TIP and ERR outputs
tip_o => vbcp_tip,
err_o => vbcp_err,
-- Wishbone master signals
wbm_stb_o => xbar_slave_in(0).stb,
wbm_cyc_o => xbar_slave_in(0).cyc,
wbm_sel_o => xbar_slave_in(0).sel,
wbm_we_o => xbar_slave_in(0).we,
wbm_dat_i => xbar_slave_out(0).dat,
wbm_dat_o => xbar_slave_in(0).dat,
wbm_adr_o => xbar_slave_in(0).adr,
wbm_ack_i => xbar_slave_out(0).ack,
wbm_rty_i => xbar_slave_out(0).rty,
wbm_err_i => xbar_slave_out(0).err
);
-- Process to blink the LED for a finite amount of time when the vbcp_tip
-- signal is set.
p_i2c_blink : process(clk125)
begin
if rising_edge(clk125) then
if (rst_n = '0') then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= (others => '0');
led_i2c <= '0';
blink_state <= '0';
else
case blink_state is
when '0' =>
led_i2c <= '0';
if (vbcp_tip = '1') then
blink_state <= '1';
end if;
when '1' =>
led_i2c_clkdiv <= led_i2c_clkdiv + 1;
if (led_i2c_clkdiv = 2499999) then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= led_i2c_cnt + 1;
led_i2c <= not led_i2c;
if (led_i2c_cnt = 7) then
led_i2c_cnt <= (others => '0');
blink_state <= '0';
end if;
end if;
when others =>
blink_state <= '0';
end case;
end if;
end if;
end process p_i2c_blink;
-- Process to set the I2C error LED signal for display on the front panel
-- of the front module. The I2C error signal is permanently set once an
-- error is detected from the bridge module.
p_i2c_err_led : process (clk125) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
i2c_err_led <= '0';
elsif (vbcp_err = '1') then
i2c_err_led <= '1';
end if;
end if;
end process p_i2c_err_led;
--============================================================================
-- Instantiation and connection of the main Wishbone crossbar
--============================================================================
cmp_wb_crossbar : xwb_crossbar
generic map
(
g_num_masters => c_nr_masters,
g_num_slaves => c_nr_slaves,
g_registered => false,
g_address => c_addresses,
g_mask => c_masks
)
port map
(
clk_sys_i => clk125,
rst_n_i => rst_n,
slave_i => xbar_slave_in,
slave_o => xbar_slave_out,
master_i => xbar_master_in,
master_o => xbar_master_out
);
--============================================================================
-- Converter board registers
--============================================================================
-- set unused wishbone outputs
xbar_master_in(c_slv_conv_regs).int <= '0';
xbar_master_in(c_slv_conv_regs).rty <= '0';
xbar_master_in(c_slv_conv_regs).err <= '0';
-- set SWITCH and RTM fields
switches_n <= ttl_switch_n_i & extra_switch_n_i(7 downto 1);
rtm_lines <= rtmp & rtmm;
-- and instantiate the component
cmp_conv_regs : conv_regs
port map (
rst_n_i => rst_n,
clk_sys_i => clk125,
wb_adr_i => xbar_master_out(c_slv_conv_regs).adr(3 downto 2),
wb_dat_i => xbar_master_out(c_slv_conv_regs).dat,
wb_dat_o => xbar_master_in (c_slv_conv_regs).dat,
wb_cyc_i => xbar_master_out(c_slv_conv_regs).cyc,
wb_sel_i => xbar_master_out(c_slv_conv_regs).sel,
wb_stb_i => xbar_master_out(c_slv_conv_regs).stb,
wb_we_i => xbar_master_out(c_slv_conv_regs).we,
wb_ack_o => xbar_master_in (c_slv_conv_regs).ack,
wb_stall_o => xbar_master_in (c_slv_conv_regs).stall,
conv_regs_id_bits_o => open,
conv_regs_sr_fwvers_i => c_fwvers,
conv_regs_sr_switches_i => switches_n,
conv_regs_sr_rtm_i => rtm_lines,
conv_regs_cr_rst_unlock_o => open,
conv_regs_cr_rst_o => open
);
--============================================================================
-- Output enable logic
--============================================================================
-- The general output enable is set first and the blocking, TTL
-- and INV output enable signals are set one clock cycle later.
p_oe : process(clk125)
begin
if rising_edge(clk125) then
if (rst_n = '0') then
oe <= '0';
blo_oe <= '0';
ttl_oe <= '0';
inv_oe <= '0';
else
oe <= '1';
if (oe = '1') then
blo_oe <= '1';
ttl_oe <= '1';
inv_oe <= '1';
end if;
end if;
end if;
end process p_oe;
fpga_oe_o <= oe;
fpga_blo_oe_o <= blo_oe;
fpga_trig_ttl_oe_o <= ttl_oe;
fpga_inv_oe_o <= inv_oe;
--============================================================================
-- TTL and blocking pulse generation logic
--============================================================================
-- First, the TTL trigger mux, selected via the TTL switch; ttlbar_nosig_n is
-- controlled in the process below
trig_ttl_a <= not fpga_input_ttl_n_i when (ttl_switch_n_i = '0') else
fpga_input_ttl_n_i and ttlbar_nosig_n;
-- Then, the blocking trigger
trig_blo_a <= fpga_blo_in_i;
-- And now the OR gate at the inputs of the pulse generator blocks
trig_a <= trig_ttl_a or trig_blo_a;
gen_ttl_pulse_generators : for i in 1 to g_nr_ttl_chan generate
-- First, resync the trigger signal into clk125 domain
cmp_sync_ffs: gc_sync_ffs
port map
(
clk_i => clk125,
rst_n_i => rst_n,
data_i => trig_a(i),
synced_o => trig_synced(i),
ppulse_o => trig_synced_edge(i)
);
-- Process to detect lack of signal on TTL line
--
-- If the signal line is high for 100 us, the ttlbar_nosig_n lines disable
-- the mux input.
p_ttlbar_nosig : process(clk125)
begin
if rising_edge(clk125) then
if (rst_n = '0') or (fpga_input_ttl_n_i(i) = '0') then
ttlbar_nosig_n(i) <= '1';
ttlbar_nosig_cnt(i) <= (others => '0');
elsif (fpga_input_ttl_n_i(i) = '1') then
ttlbar_nosig_cnt(i) <= ttlbar_nosig_cnt(i) + 1;
if (ttlbar_nosig_cnt(i) = 12499) then
ttlbar_nosig_n(i) <= '0';
ttlbar_nosig_cnt(i) <= (others => '0');
end if;
end if;
end if;
end process p_ttlbar_nosig;
-- Output pulse generators
cmp_ttl_pulse_gen : ctb_pulse_gen
generic map
(
g_pwidth => 150,
g_gf_len => 4
)
port map
(
clk_i => clk125,
rst_n_i => rst_n,
en_i => '1',
gf_en_n_i => extra_switch_n_i(1),
trig_i => trig_a(i),
pulse_o => pulse_outputs(i)
);
-- Pulse outputs assignment
fpga_out_ttl_o <= pulse_outputs when (ttl_switch_n_i = '0') else
not pulse_outputs;
fpga_trig_blo_o <= pulse_outputs;
-- Process to flash pulse LED on pulse reception
p_pulse_led : process (clk125, rst_n) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
pulse_led_cnt(i) <= (others => '0');
pulse_leds(i) <= '0';
else
case pulse_leds(i) is
when '0' =>
if (trig_synced_edge(i) = '1') then
pulse_leds(i) <= '1';
end if;
when '1' =>
pulse_led_cnt(i) <= pulse_led_cnt(i) + 1;
if (pulse_led_cnt(i) = (pulse_led_cnt(i)'range => '1')) then
pulse_leds(i) <= '0';
end if;
when others =>
pulse_leds(i) <= '0';
end case;
end if;
end if;
end process;
end generate gen_ttl_pulse_generators;
-- Pulse status LED output assignments
pulse_front_led_n_o <= (not pulse_leds) when (ttl_oe = '1') else
(others => '1');
pulse_rear_led_n_o <= (not pulse_leds) when (blo_oe = '1') else
(others => '1');
--============================================================================
-- General-purpose INV TTL outputs
--============================================================================
inv_out_o <= inv_in_n_i;
--============================================================================
-- MultiBoot logic
--============================================================================
xbar_master_in(c_slv_multiboot).int <= '0';
xbar_master_in(c_slv_multiboot).rty <= '0';
xbar_master_in(c_slv_multiboot).err <= '0';
cmp_multiboot : xil_multiboot
port map
(
clk_i => clk125,
rst_n_i => rst_n,
wbs_i => xbar_master_out(c_slv_multiboot),
wbs_o => xbar_master_in(c_slv_multiboot),
spi_cs_n_o => fpga_prom_cso_b_n_o,
spi_sclk_o => fpga_prom_cclk_o,
spi_mosi_o => fpga_prom_mosi_o,
spi_miso_i => fpga_prom_miso_i
);
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
-- Bicolor LED controls, corresponding to the column orders on the
-- bicolor_led_ctrl unit.
-- WR address
bicolor_led_state( 1 downto 0) <= c_LED_OFF;
-- WR GMT
bicolor_led_state( 3 downto 2) <= c_LED_OFF;
-- WR link
bicolor_led_state( 5 downto 4) <= c_LED_OFF;
-- WR OK
bicolor_led_state( 7 downto 6) <= c_LED_OFF;
-- MULTICAST 0
bicolor_led_state( 9 downto 8) <= c_LED_OFF;
-- MULTICAST 1
bicolor_led_state(11 downto 10) <= c_LED_OFF;
-- I2C
bicolor_led_state(13 downto 12) <= c_LED_GREEN when (led_i2c = '1') else
c_LED_RED when (i2c_err_led = '1') else
c_LED_OFF;
-- State of TTL/TTL_N switch
bicolor_led_state(15 downto 14) <= c_LED_GREEN when (ttl_switch_n_i = '0') else
c_LED_OFF;
-- System error
bicolor_led_state(17 downto 16) <= c_LED_RED when (rtmm_ok = '0') and (rtmp_ok = '0') else
c_LED_OFF;
-- System power
bicolor_led_state(19 downto 18) <= c_LED_GREEN;
-- MULTICAST 2
bicolor_led_state(21 downto 20) <= c_LED_OFF;
-- MULTICAST 3
bicolor_led_state(23 downto 22) <= c_LED_OFF;
cmp_bicolor_led_ctrl : bicolor_led_ctrl
generic map
(
g_NB_COLUMN => 6,
g_NB_LINE => 2,
g_clk_freq => 125000000,
g_refresh_rate => 250
)
port map
(
clk_i => clk125,
rst_n_i => rst_n,
led_intensity_i => "1111111",
led_state_i => bicolor_led_state,
column_o(0) => led_wr_ownaddr_i2c_o,
column_o(1) => led_wr_gmt_ttl_ttln_o,
column_o(2) => led_wr_link_syserror_o,
column_o(3) => led_wr_ok_syspw_o,
column_o(4) => led_multicast_2_0_o,
column_o(5) => led_multicast_3_1_o,
line_o(0) => led_ctrl0_o,
line_o(1) => led_ctrl1_o,
line_oen_o(0) => led_ctrl0_oen_o,
line_oen_o(1) => led_ctrl1_oen_o
);
--============================================================================
-- RTM detection logic
--============================================================================
rtmm <= not fpga_rtmm_n_i;
rtmp <= not fpga_rtmp_n_i;
cmp_rtm_detector : rtm_detector
port map
(
rtmm_i => rtmm,
rtmp_i => rtmp,
rtmm_ok_o => rtmm_ok,
rtmp_ok_o => rtmp_ok
);
end behav;
top/pulsetest/Manifest.py 0 → 100644
View file @ b4f23ad0
files = [
"pulsetest.ucf",
"pulsetest.vhd"
]
modules = {
"local" : [
"../../reset_gen",
"../../bicolor_led_ctrl",
"../../vbcp_wb",
"../../pulse_gen_gp",
"../../multiboot",
"../rtl"
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git"
]
}
fetchto = "../../../../../ip_cores"
top/pulsetest/pulsetest.ucf 0 → 100644
View file @ b4f23ad0
##--==============================================================================
##-- CERN (BE-CO-HT)
##-- Glitch filter with selectable length
##--==============================================================================
##--
##-- author: Theodor Stana (t.stana@cern.ch)
##-- Carlos-Gil Soriano
##--
##-- date of creation: 2013-04-26
##--
##-- version: 1.0
##--
##-- description:
##-- This file contains the pin definitions for the CONV-TTL-BLO FPGA. The pin
##-- names reflect those of net names at the schematic level. To keep to CERN
##-- coding standards (http://www.ohwr.org/documents/24) and make the code more
##-- readable, the pin names have been lowercased and the pin type is indicated
##-- by its suffix. The suffix "_i" indicates an input pin, "_o" an output pin
##-- and "_b" a bidirectional pin.
##--
##-- An example of net name change is given below:
##-- LED_WR_OWNADDR_I2C -> led_wr_ownaddr_i2c_o
##--
##-- Apart from this, some pins have been renamed completely and do not resemble
##-- the schematics. These pins are:
##-- TTL/INV_TTL_N -> ttl_switch_n_i
##--
##-- dependencies:
##--
##-- references:
##--
##--==============================================================================
##-- GNU LESSER GENERAL PUBLIC LICENSE
##--==============================================================================
##-- This source file is free software; you can redistribute it and/or modify it
##-- under the terms of the GNU Lesser General Public License as published by the
##-- Free Software Foundation; either version 2.1 of the License, or (at your
##-- option) any later version. This source is distributed in the hope that it
##-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
##-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
##-- See the GNU Lesser General Public License for more details. You should have
##-- received a copy of the GNU Lesser General Public License along with this
##-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##--==============================================================================
##-- last changes:
##-- 2013-04-26 Theodor Stana t.stana@cern.ch File modified
##--==============================================================================
##-- TODO: -
##--==============================================================================
##-----------------------------------------------------------------------------
##-- Default attributes
##--
##-- IOSTANDARD = "LVCMOS25"
##-- SLEW = "SLOW"
##-- DRIVE = "12"
##-----------------------------------------------------------------------------
#NET "rst_i" LOC = N20;
#NET "rst_i" IOSTANDARD = "LVCMOS33";
#NET "fpga_sysreset_n_i" LOC = L20;
NET "mr_n_o" LOC = T22;
NET "mr_n_o" IOSTANDARD = LVCMOS33;
# NET "clk20_vcxo_i" LOC = E16;
# NET "clk20_vcxo_i" TNM_NET=clk20_vcxo_i;
# TIMESPEC TSCLK20 = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %;
NET "fpga_clk_p_i" LOC = H12;
NET "fpga_clk_n_i" LOC = G11;
##=============================================================================
##-- FRONT PANEL TTLs
##=============================================================================
##-----------------------------------------------------------------------------
##-- Status LEDs
##-----------------------------------------------------------------------------
NET "led_ctrl0_o" LOC = M18;
NET "led_ctrl0_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl0_oen_o" LOC = T20;
NET "led_ctrl0_oen_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_o" LOC = M17;
NET "led_ctrl1_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_oen_o" LOC = U19;
NET "led_ctrl1_oen_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_2_0_o" LOC = P16;
NET "led_multicast_2_0_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_3_1_o" LOC = P17;
NET "led_multicast_3_1_o" IOSTANDARD = LVCMOS33;
NET "led_wr_gmt_ttl_ttln_o" LOC = N16;
NET "led_wr_gmt_ttl_ttln_o" IOSTANDARD = LVCMOS33;
NET "led_wr_link_syserror_o" LOC = R15;
NET "led_wr_link_syserror_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ok_syspw_o" LOC = R16;
NET "led_wr_ok_syspw_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ownaddr_i2c_o" LOC = N15;
NET "led_wr_ownaddr_i2c_o" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Front channel LEDs
##-----------------------------------------------------------------------------
NET "pulse_front_led_n_o[1]" LOC = H5;
NET "pulse_front_led_n_o[1]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[1]" DRIVE = 4;
NET "pulse_front_led_n_o[1]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[2]" LOC = J6;
NET "pulse_front_led_n_o[2]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[2]" DRIVE = 4;
NET "pulse_front_led_n_o[2]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[3]" LOC = K6;
NET "pulse_front_led_n_o[3]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[3]" DRIVE = 4;
NET "pulse_front_led_n_o[3]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[4]" LOC = K5;
NET "pulse_front_led_n_o[4]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[4]" DRIVE = 4;
NET "pulse_front_led_n_o[4]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[5]" LOC = M7;
NET "pulse_front_led_n_o[5]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[5]" DRIVE = 4;
NET "pulse_front_led_n_o[5]" SLEW = QUIETIO;
NET "pulse_front_led_n_o[6]" LOC = M6;
NET "pulse_front_led_n_o[6]" IOSTANDARD = LVCMOS33;
NET "pulse_front_led_n_o[6]" DRIVE = 4;
NET "pulse_front_led_n_o[6]" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- Rear LEDs
##-----------------------------------------------------------------------------
NET "pulse_rear_led_n_o[1]" LOC = AB17;
NET "pulse_rear_led_n_o[1]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[1]" DRIVE = 4;
NET "pulse_rear_led_n_o[1]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[2]" LOC = AB19;
NET "pulse_rear_led_n_o[2]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[2]" DRIVE = 4;
NET "pulse_rear_led_n_o[2]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[3]" LOC = AA16;
NET "pulse_rear_led_n_o[3]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[3]" DRIVE = 4;
NET "pulse_rear_led_n_o[3]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[4]" LOC = AA18;
NET "pulse_rear_led_n_o[4]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[4]" DRIVE = 4;
NET "pulse_rear_led_n_o[4]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[5]" LOC = AB16;
NET "pulse_rear_led_n_o[5]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[5]" DRIVE = 4;
NET "pulse_rear_led_n_o[5]" SLEW = QUIETIO;
NET "pulse_rear_led_n_o[6]" LOC = AB18;
NET "pulse_rear_led_n_o[6]" IOSTANDARD = LVCMOS33;
NET "pulse_rear_led_n_o[6]" DRIVE = 4;
NET "pulse_rear_led_n_o[6]" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- TTL trigger I/O
##-----------------------------------------------------------------------------
NET "fpga_input_ttl_n_i[1]" LOC = T2;
NET "fpga_input_ttl_n_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[2]" LOC = U3;
NET "fpga_input_ttl_n_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[3]" LOC = V5;
NET "fpga_input_ttl_n_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[4]" LOC = W4;
NET "fpga_input_ttl_n_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[5]" LOC = T6;
NET "fpga_input_ttl_n_i[5]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[5]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_input_ttl_n_i[6]" LOC = T3;
NET "fpga_input_ttl_n_i[6]" IOSTANDARD = LVCMOS33;
NET "fpga_input_ttl_n_i[6]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "fpga_out_ttl_o[1]" LOC = C1;
NET "fpga_out_ttl_o[1]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[2]" LOC = F2;
NET "fpga_out_ttl_o[2]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[3]" LOC = F5;
NET "fpga_out_ttl_o[3]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[4]" LOC = H4;
NET "fpga_out_ttl_o[4]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[5]" LOC = J4;
NET "fpga_out_ttl_o[5]" IOSTANDARD = LVCMOS33;
NET "fpga_out_ttl_o[6]" LOC = H2;
NET "fpga_out_ttl_o[6]" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Inverted TTL I/O
##-----------------------------------------------------------------------------
NET "inv_in_n_i[1]" LOC = V2;
NET "inv_in_n_i[1]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[2]" LOC = W3;
NET "inv_in_n_i[2]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[3]" LOC = Y2;
NET "inv_in_n_i[3]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_in_n_i[4]" LOC = AA2;
NET "inv_in_n_i[4]" IOSTANDARD = LVCMOS33;
NET "inv_in_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
NET "inv_out_o[1]" LOC = J3;
NET "inv_out_o[1]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[2]" LOC = L3;
NET "inv_out_o[2]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[3]" LOC = M3;
NET "inv_out_o[3]" IOSTANDARD = LVCMOS33;
NET "inv_out_o[4]" LOC = P2;
NET "inv_out_o[4]" IOSTANDARD = LVCMOS33;
##=============================================================================
##-- RTM signals
##=============================================================================
##-----------------------------------------------------------------------------
##-- Blocking I/O
##-----------------------------------------------------------------------------
NET "fpga_blo_in_i[1]" LOC = Y9;
NET "fpga_blo_in_i[1]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[2]" LOC = AA10;
NET "fpga_blo_in_i[2]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[3]" LOC = W12;
NET "fpga_blo_in_i[3]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[4]" LOC = AA6;
NET "fpga_blo_in_i[4]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[5]" LOC = Y7;
NET "fpga_blo_in_i[5]" IOSTANDARD = "LVCMOS33";
NET "fpga_blo_in_i[6]" LOC = AA8;
NET "fpga_blo_in_i[6]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[1]" LOC = W9;
NET "fpga_trig_blo_o[1]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[2]" LOC = T10;
NET "fpga_trig_blo_o[2]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[3]" LOC = V7;
NET "fpga_trig_blo_o[3]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[4]" LOC = U9;
NET "fpga_trig_blo_o[4]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[5]" LOC = T8;
NET "fpga_trig_blo_o[5]" IOSTANDARD = "LVCMOS33";
NET "fpga_trig_blo_o[6]" LOC = R9;
NET "fpga_trig_blo_o[6]" IOSTANDARD = "LVCMOS33";
##=============================================================================
##-- VME CONNECTOR SIGNALS
##=============================================================================
##-----------------------------------------------------------------------------
##-- I2C lines
##-----------------------------------------------------------------------------
NET "scl_i" LOC = F19;
NET "scl_i" IOSTANDARD = LVCMOS33;
NET "scl_o" LOC = E20;
NET "scl_o" IOSTANDARD = LVCMOS33;
NET "scl_o" DRIVE = 4;
NET "scl_oe_o" LOC = H18;
NET "scl_oe_o" IOSTANDARD = LVCMOS33;
NET "scl_oe_o" DRIVE = 4;
# NET "scl_oe_o" PULLDOWN;
NET "sda_i" LOC = G20;
NET "sda_i" IOSTANDARD = LVCMOS33;
NET "sda_o" LOC = F20;
NET "sda_o" IOSTANDARD = LVCMOS33;
NET "sda_o" SLEW = FAST;
NET "sda_o" DRIVE = 4;
# NET "sda_o" PULLUP;
NET "sda_oe_o" LOC = J19;
NET "sda_oe_o" IOSTANDARD = LVCMOS33;
NET "sda_oe_o" SLEW = FAST;
NET "sda_oe_o" DRIVE = 4;
# NET "sda_oe_o" PULLDOWN;
##-----------------------------------------------------------------------------
##-- Geographical Address
##-----------------------------------------------------------------------------
NET "fpga_ga_i[0]" LOC = H20;
NET "fpga_ga_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[1]" LOC = J20;
NET "fpga_ga_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[2]" LOC = K19;
NET "fpga_ga_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[3]" LOC = K20;
NET "fpga_ga_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[4]" LOC = L19;
NET "fpga_ga_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_gap_i" LOC = H19;
NET "fpga_gap_i" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- ROM memory
##-----------------------------------------------------------------------------
NET "fpga_prom_cclk_o" LOC = Y20;
NET "fpga_prom_cclk_o" IOSTANDARD = "LVCMOS33";
NET "fpga_prom_cso_b_n_o" LOC = AA3;
NET "fpga_prom_cso_b_n_o" IOSTANDARD = "LVCMOS33";
NET "fpga_prom_miso_i" LOC = AA20;
NET "fpga_prom_miso_i" IOSTANDARD = "LVCMOS33";
NET "fpga_prom_mosi_o" LOC = AB20;
NET "fpga_prom_mosi_o" IOSTANDARD = "LVCMOS33";
###=============================================================================
###-- WHITE RABBIT
###=============================================================================
###-----------------------------------------------------------------------------
###-- Thermo for UID
###-----------------------------------------------------------------------------
#NET "thermometer_b" LOC = B1;
#NET "thermometer_b" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- DAC control
###-----------------------------------------------------------------------------
#NET "fpga_plldac1_din_o" LOC = AB14;
#NET "fpga_plldac1_din_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac1_sclk_o" LOC = AA14;
#NET "fpga_plldac1_sclk_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac1_sync_n_o" LOC = AB15;
#NET "fpga_plldac1_sync_n_o" IOSTANDARD = LVCMOS33;
#
#NET "fpga_plldac2_din_o" LOC = W14;
#NET "fpga_plldac2_din_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac2_sclk_o" LOC = Y14;
#NET "fpga_plldac2_sclk_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac2_sync_n_o" LOC = W13;
#NET "fpga_plldac2_sync_n_o" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- SFP connection
###-----------------------------------------------------------------------------
##NET "fpga_sfp_los_i" LOC = G3;
## NET "fpga_sfp_los_i" IOSTANDARD = "LVCMOS33";
##NET "fpga_sfp_mod_def0_i" LOC = K8;
## NET "fpga_sfp_mod_def0_i" IOSTANDARD = "LVCMOS33";
##NET "fpga_sfp_rate_select_o" LOC = C4;
## NET "fpga_sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
#NET "fpga_sfp_mod_def1_b" LOC = G4;
#NET "fpga_sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
#
#NET "fpga_sfp_mod_def2_b" LOC = F3;
#NET "fpga_sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
##NET "fpga_sfp_tx_disable_o" LOC = E4;
## NET "fpga_sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
##NET "fpga_sfp_tx_fault_i" LOC = D2;
## NET "fpga_sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
###-----------------------------------------------------------------------------
###-- FPGA MGT lines
###-----------------------------------------------------------------------------
#NET "fpga_mgt_clk0_p_i" LOC = A10;
#NET "fpga_mgt_clk0_n_i" LOC = B10;
#
#NET "mgt_sfp_rx0_p_i" LOC = D7;
#NET "mgt_sfp_rx0_n_i" LOC = C7;
#
#NET "mgt_sfp_tx0_p_o" LOC = B6;
#NET "mgt_sfp_tx0_n_o" LOC = A6;
###=============================================================================
###-- ADDITIONAL PINS
###=============================================================================
NET "fpga_oe_o" LOC = R3;
NET "fpga_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_oe_o" DRIVE = 4;
NET "fpga_oe_o" SLEW = QUIETIO;
NET "fpga_blo_oe_o" LOC = P5;
NET "fpga_blo_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_blo_oe_o" DRIVE = 4;
NET "fpga_blo_oe_o" SLEW = QUIETIO;
NET "fpga_trig_ttl_oe_o" LOC = N3;
NET "fpga_trig_ttl_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_trig_ttl_oe_o" DRIVE = 4;
NET "fpga_trig_ttl_oe_o" SLEW = QUIETIO;
NET "fpga_inv_oe_o" LOC = P6;
NET "fpga_inv_oe_o" IOSTANDARD = LVCMOS33;
NET "fpga_inv_oe_o" DRIVE = 4;
NET "fpga_inv_oe_o" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- Configuration Switches
##-----------------------------------------------------------------------------
NET "extra_switch_n_i[1]" LOC = F22;
NET "extra_switch_n_i[1]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[2]" LOC = G22;
NET "extra_switch_n_i[2]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[3]" LOC = H21;
NET "extra_switch_n_i[3]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[4]" LOC = H22;
NET "extra_switch_n_i[4]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[5]" LOC = J22;
NET "extra_switch_n_i[5]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[6]" LOC = K21;
NET "extra_switch_n_i[6]" IOSTANDARD = "LVCMOS33";
NET "extra_switch_n_i[7]" LOC = K22;
NET "extra_switch_n_i[7]" IOSTANDARD = "LVCMOS33";
NET "ttl_switch_n_i" LOC = L22;
NET "ttl_switch_n_i" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Motherboard and piggyback IDs
##-----------------------------------------------------------------------------
# NET "fpga_rtmm_n_i[0]" LOC = V21;
# NET "fpga_rtmm_n_i[0]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmm_n_i[1]" LOC = V22;
# NET "fpga_rtmm_n_i[1]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmm_n_i[2]" LOC = U22;
# NET "fpga_rtmm_n_i[2]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmp_n_i[0]" LOC = W22;
# NET "fpga_rtmp_n_i[0]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmp_n_i[1]" LOC = Y22;
# NET "fpga_rtmp_n_i[1]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmp_n_i[2]" LOC = Y21;
# NET "fpga_rtmp_n_i[2]" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- General purpose
###-----------------------------------------------------------------------------
# NET "fpga_header_out_n_o[1]" LOC = F15;
# NET "fpga_header_out_n_o[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[2]" LOC = F16;
# NET "fpga_header_out_n_o[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[3]" LOC = F17;
# NET "fpga_header_out_n_o[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[4]" LOC = F14;
# NET "fpga_header_out_n_o[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[5]" LOC = H14;
# NET "fpga_header_out_n_o[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[6]" LOC = H13;
# NET "fpga_header_out_n_o[6]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[1]" LOC = A17;
# NET "fpga_header_in_n_i[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[2]" LOC = A18;
# NET "fpga_header_in_n_i[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[3]" LOC = B18;
# NET "fpga_header_in_n_i[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[4]" LOC = A19;
# NET "fpga_header_in_n_i[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[5]" LOC = A20;
# NET "fpga_header_in_n_i[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[6]" LOC = B20;
# NET "fpga_header_in_n_i[6]" IOSTANDARD = "LVCMOS33";
top/pulsetest/pulsetest.vhd 0 → 100644
View file @ b4f23ad0
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO
-- http://www.ohwr.org/projects/conv-ttl-blo
--------------------------------------------------------------------------------
--
-- unit name: pulsetest.vhd
--
-- author: Theodor-Adrian Stana (t.stana@cern.ch)
--
-- version: 1.0
--
-- description: Top entity of CONV-TTL-BLO
--
-- dependencies:
--
-- references:
-- [1] ELMA, Access to board data using SNMP and I2C
-- http://www.ohwr.org/documents/227
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use unisim.vcomponents.all;
use work.bicolor_led_ctrl_pkg.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
entity pulsetest is
generic
(
g_nr_ttl_chan : natural := 6;
g_nr_inv_chan : natural := 4
);
port
(
-- Clock lines
fpga_clk_p_i : in std_logic; --Using the 125MHz clock
fpga_clk_n_i : in std_logic;
-- LEDs
led_ctrl0_o : out std_logic;
led_ctrl0_oen_o : out std_logic;
led_ctrl1_o : out std_logic;
led_ctrl1_oen_o : out std_logic;
led_multicast_2_0_o : out std_logic;
led_multicast_3_1_o : out std_logic;
led_wr_gmt_ttl_ttln_o : out std_logic;
led_wr_link_syserror_o : out std_logic;
led_wr_ok_syspw_o : out std_logic;
led_wr_ownaddr_i2c_o : out std_logic;
-- I/Os for pulses
pulse_front_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
pulse_rear_led_n_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_input_ttl_n_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_out_ttl_o : out std_logic_vector(g_nr_ttl_chan downto 1);
fpga_blo_in_i : in std_logic_vector(g_nr_ttl_chan downto 1);
fpga_trig_blo_o : out std_logic_vector(g_nr_ttl_chan downto 1);
inv_in_n_i : in std_logic_vector(g_nr_inv_chan downto 1);
inv_out_o : out std_logic_vector(g_nr_inv_chan downto 1);
-- Output enable lines
fpga_oe_o : out std_logic;
fpga_blo_oe_o : out std_logic;
fpga_trig_ttl_oe_o : out std_logic;
fpga_inv_oe_o : out std_logic;
--TTL/INV_TTL_N
ttl_switch_n_i : in std_logic;
extra_switch_n_i : in std_logic_vector(7 downto 1);
-- Lines for the i2c_slave
scl_i : in std_logic;
scl_o : out std_logic;
scl_oe_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_oe_o : out std_logic;
fpga_ga_i : in std_logic_vector(4 downto 0);
fpga_gap_i : in std_logic;
-- Flash memory lines
fpga_prom_cclk_o : out std_logic;
fpga_prom_cso_b_n_o : out std_logic;
fpga_prom_mosi_o : out std_logic;
fpga_prom_miso_i : in std_logic;
-- It allows power sequencing of the 24V rail after a security delay
mr_n_o : out std_logic
);
end pulsetest;
architecture behav of pulsetest is
--============================================================================
-- Type declarations
--============================================================================
type t_pulse_counter is array(1 to g_nr_ttl_chan) of unsigned(31 downto 0);
type t_pulse_led_counter is array (1 to g_nr_ttl_chan) of unsigned(22 downto 0);
type t_pgen_ctrl_reg is array (1 to 6) of std_logic_vector(31 downto 0);
--============================================================================
-- Constant declarations
--============================================================================
-- Firmware version
constant c_fwvers : std_logic_vector(15 downto 0) := x"9999";
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 4;
-----------------------------------------
-- Memory map
-- * all registers are word-addressable
-- * all registers are word-aligned
-----------------------------------------
-- CONV_REGS [0x000-0x004]
-- PULSE_CNT [0x100-0x13F]
-- PGEN_CTRL [0x200-0x24F]
-- MULTIBOOT [0x300-0x31F]
-----------------------------------------
-- slave order definitions
constant c_slv_conv_regs : natural := 0;
constant c_slv_pulse_cnt : natural := 1;
constant c_slv_pgen_ctrl : natural := 2;
constant c_slv_multiboot : natural := 3;
-- base address definitions
constant c_addr_conv_regs : t_wishbone_address := x"00000000";
constant c_addr_pulse_cnt : t_wishbone_address := x"00000100";
constant c_addr_pgen_ctrl : t_wishbone_address := x"00000200";
constant c_addr_multiboot : t_wishbone_address := x"00000300";
-- address mask definitions
constant c_mask_conv_regs : t_wishbone_address := x"00000F00";
constant c_mask_pulse_cnt : t_wishbone_address := x"00000F00";
constant c_mask_pgen_ctrl : t_wishbone_address := x"00000F00";
constant c_mask_multiboot : t_wishbone_address := x"00000F00";
-- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_conv_regs => c_addr_conv_regs,
c_slv_pulse_cnt => c_addr_pulse_cnt,
c_slv_pgen_ctrl => c_addr_pgen_ctrl,
c_slv_multiboot => c_addr_multiboot
);
-- masks constant for Wishbone crossbar
constant c_masks : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_conv_regs => c_mask_conv_regs,
c_slv_pulse_cnt => c_mask_pulse_cnt,
c_slv_pgen_ctrl => c_mask_pgen_ctrl,
c_slv_multiboot => c_addr_multiboot
);
--============================================================================
-- Component declarations
--============================================================================
-- Reset generator component
-- (use: global reset generation, output reset generation)
component reset_gen is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time : positive := 5_000_000
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
rst_n_o : out std_logic
);
end component reset_gen;
-- I2C bridge
-- (use: convert I2C transfers into WB transfers on memmapped registers)
component vbcp_wb is
port
(
-- Clock, reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C lines
sda_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
-- I2C address and status
i2c_addr_i : in std_logic_vector(6 downto 0);
tip_o : out std_logic;
err_o : out std_logic;
-- Wishbone master signals
wbm_stb_o : out std_logic;
wbm_cyc_o : out std_logic;
wbm_sel_o : out std_logic_vector(3 downto 0);
wbm_we_o : out std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_adr_o : out std_logic_vector(31 downto 0);
wbm_ack_i : in std_logic;
wbm_rty_i : in std_logic;
wbm_err_i : in std_logic
);
end component vbcp_wb;
-- Xilinx MultiBoot component
-- (use: remote reprogramming of the FPGA)
component xil_multiboot is
port
(
-- Clock and reset input ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone ports
wbs_i : in t_wishbone_slave_in;
wbs_o : out t_wishbone_slave_out;
-- SPI ports
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end component xil_multiboot;
-- Converter registers
-- (use: ID, firmware version)
component conv_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID register'
conv_regs_id_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'fwvers' in reg: 'Status register'
conv_regs_sr_fwvers_i : in std_logic_vector(15 downto 0);
-- Port for std_logic_vector field: 'switches' in reg: 'Status register'
conv_regs_sr_switches_i : in std_logic_vector(7 downto 0);
-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status register'
conv_regs_sr_rtm_i : in std_logic_vector(5 downto 0);
-- Port for BIT field: 'Reset unlock bit' in reg: 'Control register'
conv_regs_cr_rst_unlock_o : out std_logic;
-- Port for BIT field: 'Reset bit' in reg: 'Control register'
conv_regs_cr_rst_o : out std_logic
);
end component conv_regs;
-- General-purpose pulse generator component
-- (usage: generate pulses on each channel output)
component pulse_gen_gp is
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic;
delay_i : in std_logic_vector(31 downto 0);
pwidth_i : in std_logic_vector(31 downto 0);
freq_i : in std_logic_vector(31 downto 0);
pulse_o : out std_logic
);
end component pulse_gen_gp;
-- Pulse generator control registers component
-- (usage: contains bits and values to control the pulse_gen_gp component)
component pgen_ctrl_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'channel enable' in reg: 'Enable register'
pgen_ctrl_regs_en_ch_o : out std_logic_vector(5 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 delay register'
pgen_ctrl_regs_ch1_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 delay register'
pgen_ctrl_regs_ch2_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 delay register'
pgen_ctrl_regs_ch3_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 delay register'
pgen_ctrl_regs_ch4_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 delay register'
pgen_ctrl_regs_ch5_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 delay register'
pgen_ctrl_regs_ch6_delay_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 pulse width register'
pgen_ctrl_regs_ch1_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 pulse width register'
pgen_ctrl_regs_ch2_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 pulse width register'
pgen_ctrl_regs_ch3_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 pulse width register'
pgen_ctrl_regs_ch4_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 pulse width register'
pgen_ctrl_regs_ch5_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 pulse width register'
pgen_ctrl_regs_ch6_pwidth_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH1 frequency register'
pgen_ctrl_regs_ch1_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH2 frequency register'
pgen_ctrl_regs_ch2_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH3 frequency register'
pgen_ctrl_regs_ch3_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH4 frequency register'
pgen_ctrl_regs_ch4_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH5 frequency register'
pgen_ctrl_regs_ch5_freq_bits_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'bits' in reg: 'CH6 frequency register'
pgen_ctrl_regs_ch6_freq_bits_o : out std_logic_vector(31 downto 0)
);
end component pgen_ctrl_regs;
-- Pulse counter registers component
-- (usage: store values of pulse counters)
component pulse_cnt_regs is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH1 input'
pulse_cnt_ch1i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH1 output'
pulse_cnt_ch1o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH2 input'
pulse_cnt_ch2i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH2 output'
pulse_cnt_ch2o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH3 input'
pulse_cnt_ch3i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH3 output'
pulse_cnt_ch3o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH4 input'
pulse_cnt_ch4i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH4 output'
pulse_cnt_ch4o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH5 input'
pulse_cnt_ch5i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH5 output'
pulse_cnt_ch5o_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 input'
pulse_cnt_ch6i_val_i : in std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 output'
pulse_cnt_ch6o_val_i : in std_logic_vector(31 downto 0);
-- Port for BIT field: 'reset' in reg: 'Counter reset'
pulse_cnt_rst_bit_o : out std_logic
);
end component pulse_cnt_regs;
--============================================================================
-- Signal declarations
--============================================================================
-- Clock signals
signal clk125 : std_logic;
-- Reset signals
signal rst_n, rst : std_logic;
-- Wishbone crossbar signals
signal xbar_slave_in : t_wishbone_slave_in_array (c_nr_masters - 1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_nr_masters - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_nr_slaves - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array(c_nr_slaves - 1 downto 0);
-- RAM signals
signal ram_we : std_logic;
signal ram_ack : std_logic;
-- Signal for controlling the bicolor LED matrix
signal bicolor_led_state : std_logic_vector(23 downto 0);
-- VBCP bridge signals
signal vbcp_tip : std_logic;
signal vbcp_err : std_logic;
signal i2c_err_led : std_logic;
signal i2c_up : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0);
signal led_i2c : std_logic;
signal led_i2c_clkdiv : unsigned(22 downto 0);
signal led_i2c_cnt : unsigned( 2 downto 0);
signal blink_state : std_logic;
-- Pulse enable signals
signal oe, ttl_oe : std_logic;
signal blo_oe, inv_oe : std_logic;
signal ch_en : std_logic_vector(g_nr_ttl_chan downto 1);
-- Pulse generation signals
signal trig_ttl_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_blo_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_synced : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_synced_edge: std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse, pulse_d0 : std_logic_vector(g_nr_ttl_chan downto 1);
-- Pulse LED signals
signal pulse_leds : std_logic_vector(g_nr_ttl_chan downto 1);
signal pulse_led_cnt : t_pulse_led_counter;
-- Pulse generator and counter register signals
signal cnt_in, cnt_out : t_pulse_counter;
signal cntrst : std_logic;
signal delay_reg : t_pgen_ctrl_reg;
signal pwidth_reg : t_pgen_ctrl_reg;
signal freq_reg : t_pgen_ctrl_reg;
begin
--============================================================================
-- Generate 125 MHz global signal from differential lines
--============================================================================
cmp_125_diff_buf : IBUFGDS
generic map
(
DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE
)
port map
(
I => fpga_clk_p_i,
IB => fpga_clk_n_i,
O => clk125
);
--============================================================================
-- Internal and external reset generation
--============================================================================
-- Configure reset generator for 96ms power-on reset
cmp_reset_gen : reset_gen
generic map
(
-- Reset time: 12 * 8ns * (10**6) = 96 ms
g_reset_time => 12*(10**6)
)
port map
(
clk_i => clk125,
rst_i => '0',
rst_n_o => rst_n
);
-- rst <= not rst_n;
mr_n_o <= rst_n;
--============================================================================
-- I2C bridge logic
--============================================================================
-- Set the I2C address signal according to ELMA protocol [1]
i2c_addr <= "10" & fpga_ga_i;
-- Instantiate VBCP bridge component
cmp_i2c_bridge : vbcp_wb
port map
(
-- Clock, reset
clk_i => clk125,
rst_n_i => rst_n,
-- I2C lines
sda_en_o => sda_oe_o,
sda_i => sda_i,
sda_o => sda_o,
scl_en_o => scl_oe_o,
scl_i => scl_i,
scl_o => scl_o,
-- I2C address and status
i2c_addr_i => i2c_addr,
tip_o => vbcp_tip,
err_o => vbcp_err,
-- Wishbone master signals
wbm_stb_o => xbar_slave_in(0).stb,
wbm_cyc_o => xbar_slave_in(0).cyc,
wbm_sel_o => xbar_slave_in(0).sel,
wbm_we_o => xbar_slave_in(0).we,
wbm_dat_i => xbar_slave_out(0).dat,
wbm_dat_o => xbar_slave_in(0).dat,
wbm_adr_o => xbar_slave_in(0).adr,
wbm_ack_i => xbar_slave_out(0).ack,
wbm_rty_i => xbar_slave_out(0).rty,
wbm_err_i => xbar_slave_out(0).err
);
-- Process to blink the LED for a finite amount of time when the vbcp_tip
-- signal is set.
p_i2c_blink : process(clk125)
begin
if rising_edge(clk125) then
if (rst_n = '0') then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= (others => '0');
led_i2c <= '0';
blink_state <= '0';
else
case blink_state is
when '0' =>
led_i2c <= '0';
if (vbcp_tip = '1') then
blink_state <= '1';
end if;
when '1' =>
led_i2c_clkdiv <= led_i2c_clkdiv + 1;
if (led_i2c_clkdiv = 2499999) then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= led_i2c_cnt + 1;
led_i2c <= not led_i2c;
if (led_i2c_cnt = 7) then
led_i2c_cnt <= (others => '0');
blink_state <= '0';
end if;
end if;
when others =>
blink_state <= '0';
end case;
end if;
end if;
end process p_i2c_blink;
-- Process to set the I2C error LED signal for display on the front panel
-- of the front module. The I2C error signal is permanently set once an
-- error is detected from the bridge module.
p_i2c_err_led : process (clk125) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
i2c_err_led <= '0';
elsif (vbcp_err = '1') then
i2c_err_led <= '1';
end if;
end if;
end process p_i2c_err_led;
--============================================================================
-- Instantiation and connection of the main Wishbone crossbar
--============================================================================
xbar_master_in(0).int <= '0';
xbar_master_in(0).err <= '0';
cmp_wb_crossbar : xwb_crossbar
generic map
(
g_num_masters => c_nr_masters,
g_num_slaves => c_nr_slaves,
g_registered => false,
g_address => c_addresses,
g_mask => c_masks
)
port map
(
clk_sys_i => clk125,
rst_n_i => rst_n,
slave_i => xbar_slave_in,
slave_o => xbar_slave_out,
master_i => xbar_master_in,
master_o => xbar_master_out
);
cmp_conv_regs : conv_regs
port map (
rst_n_i => rst_n,
clk_sys_i => clk125,
wb_adr_i => xbar_master_out(c_slv_conv_regs).adr(3 downto 2),
wb_dat_i => xbar_master_out(c_slv_conv_regs).dat,
wb_dat_o => xbar_master_in (c_slv_conv_regs).dat,
wb_cyc_i => xbar_master_out(c_slv_conv_regs).cyc,
wb_sel_i => xbar_master_out(c_slv_conv_regs).sel,
wb_stb_i => xbar_master_out(c_slv_conv_regs).stb,
wb_we_i => xbar_master_out(c_slv_conv_regs).we,
wb_ack_o => xbar_master_in (c_slv_conv_regs).ack,
wb_stall_o => xbar_master_in (c_slv_conv_regs).stall,
conv_regs_id_bits_o => open,
conv_regs_sr_fwvers_i => c_fwvers,
conv_regs_sr_switches_i => (others => '0'),
conv_regs_sr_rtm_i => (others => '0'),
conv_regs_cr_rst_unlock_o => open,
conv_regs_cr_rst_o => open
);
----============================================================================
---- Instantiate single-port RAM
----============================================================================
--cmp_memory: generic_spram
-- generic map (
-- g_data_width => 32,
-- g_size => 2**9
-- )
-- port map (
-- rst_n_i => rst_n,
-- clk_i => clk125,
-- bwe_i => (others => '0'),
-- we_i => ram_we,
-- a_i => xbar_master_out(c_slv_mem).adr(10 downto 2),
-- d_i => xbar_master_out(c_slv_mem).dat,
-- q_o => xbar_master_in(c_slv_mem).dat
-- );
--ram_we <= xbar_master_out(c_slv_mem).we and xbar_master_out(c_slv_mem).stb and
-- xbar_master_out(c_slv_mem).cyc;
--xbar_master_in(c_slv_mem).ack <= ram_ack;
--xbar_master_in(c_slv_mem).err <= '0';
--p_ram_ack : process (clk125) is
--begin
-- if rising_edge(clk125) then
-- if (rst_n = '0') then
-- ram_ack <= '0';
-- else
-- ram_ack <= '0';
-- if (xbar_master_out(c_slv_mem).stb = '1') and
-- (xbar_master_out(c_slv_mem).cyc = '1') then
-- ram_ack <= '1';
-- end if;
-- end if;
-- end if;
--end process p_ram_ack;
--============================================================================
-- Pulse generation control registers instantiation
--============================================================================
cmp_pulse_gen_ctrl_regs : pgen_ctrl_regs
port map
(
rst_n_i => rst_n,
clk_sys_i => clk125,
wb_adr_i => xbar_master_out(c_slv_pgen_ctrl).adr(6 downto 2),
wb_dat_i => xbar_master_out(c_slv_pgen_ctrl).dat,
wb_dat_o => xbar_master_in(c_slv_pgen_ctrl).dat,
wb_cyc_i => xbar_master_out(c_slv_pgen_ctrl).cyc,
wb_sel_i => xbar_master_out(c_slv_pgen_ctrl).sel,
wb_stb_i => xbar_master_out(c_slv_pgen_ctrl).stb,
wb_we_i => xbar_master_out(c_slv_pgen_ctrl).we,
wb_ack_o => xbar_master_in(c_slv_pgen_ctrl).ack,
wb_stall_o => xbar_master_in(c_slv_pgen_ctrl).stall,
pgen_ctrl_regs_en_ch_o => ch_en,
pgen_ctrl_regs_ch1_delay_bits_o => delay_reg(1),
pgen_ctrl_regs_ch2_delay_bits_o => delay_reg(2),
pgen_ctrl_regs_ch3_delay_bits_o => delay_reg(3),
pgen_ctrl_regs_ch4_delay_bits_o => delay_reg(4),
pgen_ctrl_regs_ch5_delay_bits_o => delay_reg(5),
pgen_ctrl_regs_ch6_delay_bits_o => delay_reg(6),
pgen_ctrl_regs_ch1_pwidth_bits_o => pwidth_reg(1),
pgen_ctrl_regs_ch2_pwidth_bits_o => pwidth_reg(2),
pgen_ctrl_regs_ch3_pwidth_bits_o => pwidth_reg(3),
pgen_ctrl_regs_ch4_pwidth_bits_o => pwidth_reg(4),
pgen_ctrl_regs_ch5_pwidth_bits_o => pwidth_reg(5),
pgen_ctrl_regs_ch6_pwidth_bits_o => pwidth_reg(6),
pgen_ctrl_regs_ch1_freq_bits_o => freq_reg(1),
pgen_ctrl_regs_ch2_freq_bits_o => freq_reg(2),
pgen_ctrl_regs_ch3_freq_bits_o => freq_reg(3),
pgen_ctrl_regs_ch4_freq_bits_o => freq_reg(4),
pgen_ctrl_regs_ch5_freq_bits_o => freq_reg(5),
pgen_ctrl_regs_ch6_freq_bits_o => freq_reg(6)
);
--============================================================================
-- Output enable logic
--============================================================================
-- The general output enable is set first and the blocking, TTL
-- and INV output enable signals are set one clock cycle later.
p_oe : process(clk125)
begin
if rising_edge(clk125) then
if (rst_n = '0') then
oe <= '0';
blo_oe <= '0';
ttl_oe <= '0';
inv_oe <= '0';
else
oe <= '1';
if (oe = '1') then
blo_oe <= '1';
ttl_oe <= '1';
inv_oe <= '1';
end if;
end if;
end if;
end process p_oe;
fpga_oe_o <= oe;
fpga_blo_oe_o <= blo_oe; --'0';
fpga_trig_ttl_oe_o <= ttl_oe;
fpga_inv_oe_o <= inv_oe;
--============================================================================
-- Pulse generation logic
--============================================================================
-- First, the TTL trigger mux, selected via the TTL switch; ttlbar_nosig_n is
-- controlled in the process below
trig_ttl_a <= not fpga_input_ttl_n_i when (ttl_switch_n_i = '0') else
fpga_input_ttl_n_i;
-- Then, the blocking trigger
trig_blo_a <= fpga_blo_in_i;
-- And now the OR gate at the inputs of the pulse generator blocks
trig_a <= trig_ttl_a or trig_blo_a;
-- Generate logic for each channel
gen_chan_logic : for i in 1 to g_nr_ttl_chan generate
-- First, resync the trigger signal into clk125 domain
cmp_sync_ffs: gc_sync_ffs
port map
(
clk_i => clk125,
rst_n_i => rst_n,
data_i => trig_a(i),
synced_o => trig_synced(i),
ppulse_o => trig_synced_edge(i)
);
-- Instantiate output pulse generators
cmp_pulse_gen : pulse_gen_gp
port map
(
clk_i => clk125,
rst_n_i => rst_n,
en_i => ch_en(i),
delay_i => delay_reg(i),
pwidth_i => pwidth_reg(i),
freq_i => freq_reg(i),
pulse_o => pulse(i)
);
-- Delay reg for output pulses
p_delay_pulse : process (clk125) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
pulse_d0(i) <= '0';
else
pulse_d0(i) <= pulse(i);
end if;
end if;
end process p_delay_pulse;
-- Pulse counting logic
p_cnt_pulses : process(clk125) is
begin
if rising_edge(clk125) then
if (rst_n = '0') or (cntrst = '1') then
cnt_in(i) <= (others => '0');
cnt_out(i) <= (others => '0');
else
if (pulse(i) = '1') and (pulse_d0(i) = '0') then
cnt_out(i) <= cnt_out(i) + 1;
end if;
if (trig_synced_edge(i) = '1') then
cnt_in(i) <= cnt_in(i) + 1;
end if;
end if;
end if;
end process p_cnt_pulses;
-- Finally, a process to flash pulse LED on pulse transmission
p_pulse_led : process (clk125, rst_n) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
pulse_led_cnt(i) <= (others => '0');
pulse_leds(i) <= '0';
else
case pulse_leds(i) is
when '0' =>
if (pulse(i) = '1') and (pulse_d0(i) = '0') then
pulse_leds(i) <= '1';
end if;
when '1' =>
pulse_led_cnt(i) <= pulse_led_cnt(i) + 1;
if (pulse_led_cnt(i) = (pulse_led_cnt(i)'range => '1')) then
pulse_leds(i) <= '0';
end if;
when others =>
pulse_leds(i) <= '0';
end case;
end if;
end if;
end process p_pulse_led;
-- Set the pulse status LED for the channel
pulse_front_led_n_o(i) <= (not pulse_leds(i)) when (ch_en(i) = '1') else '1';
pulse_rear_led_n_o(i) <= (not pulse_leds(i)) when (ch_en(i) = '1') else '1';
end generate gen_chan_logic;
-- Pulse outputs assignment
fpga_out_ttl_o <= pulse when (ttl_switch_n_i = '0') else
not pulse;
fpga_trig_blo_o <= pulse; --(others => '0');
-- Pulse status LED output assignments
-- pulse_rear_led_n_o <= (others => '1');
--============================================================================
-- Pulse counter registers instantiation
--============================================================================
cmp_pulse_cnt_regs : pulse_cnt_regs
port map
(
rst_n_i => rst_n,
clk_sys_i => clk125,
wb_adr_i => xbar_master_out(c_slv_pulse_cnt).adr(5 downto 2),
wb_dat_i => xbar_master_out(c_slv_pulse_cnt).dat,
wb_dat_o => xbar_master_in(c_slv_pulse_cnt).dat,
wb_cyc_i => xbar_master_out(c_slv_pulse_cnt).cyc,
wb_sel_i => xbar_master_out(c_slv_pulse_cnt).sel,
wb_stb_i => xbar_master_out(c_slv_pulse_cnt).stb,
wb_we_i => xbar_master_out(c_slv_pulse_cnt).we,
wb_ack_o => xbar_master_in(c_slv_pulse_cnt).ack,
wb_stall_o => xbar_master_in(c_slv_pulse_cnt).stall,
pulse_cnt_ch1i_val_i => std_logic_vector(cnt_in(1)),
pulse_cnt_ch1o_val_i => std_logic_vector(cnt_out(1)),
pulse_cnt_ch2i_val_i => std_logic_vector(cnt_in(2)),
pulse_cnt_ch2o_val_i => std_logic_vector(cnt_out(2)),
pulse_cnt_ch3i_val_i => std_logic_vector(cnt_in(3)),
pulse_cnt_ch3o_val_i => std_logic_vector(cnt_out(3)),
pulse_cnt_ch4i_val_i => std_logic_vector(cnt_in(4)),
pulse_cnt_ch4o_val_i => std_logic_vector(cnt_out(4)),
pulse_cnt_ch5i_val_i => std_logic_vector(cnt_in(5)),
pulse_cnt_ch5o_val_i => std_logic_vector(cnt_out(5)),
pulse_cnt_ch6i_val_i => std_logic_vector(cnt_in(6)),
pulse_cnt_ch6o_val_i => std_logic_vector(cnt_out(6)),
pulse_cnt_rst_bit_o => cntrst
);
--============================================================================
-- Inverter outputs assignment
--============================================================================
inv_out_o <= inv_in_n_i;
--============================================================================
-- MultiBoot logic
--============================================================================
xbar_master_in(c_slv_multiboot).int <= '0';
xbar_master_in(c_slv_multiboot).rty <= '0';
xbar_master_in(c_slv_multiboot).err <= '0';
cmp_multiboot : xil_multiboot
port map
(
clk_i => clk125,
rst_n_i => rst_n,
wbs_i => xbar_master_out(c_slv_multiboot),
wbs_o => xbar_master_in(c_slv_multiboot),
spi_cs_n_o => fpga_prom_cso_b_n_o,
spi_sclk_o => fpga_prom_cclk_o,
spi_mosi_o => fpga_prom_mosi_o,
spi_miso_i => fpga_prom_miso_i
);
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
-- Bicolor LED controls, corresponding to the column orders on the
-- bicolor_led_ctrl unit.
-- WR address
bicolor_led_state( 1 downto 0) <= c_LED_OFF;
-- WR GMT
bicolor_led_state( 3 downto 2) <= c_LED_OFF;
-- WR link
bicolor_led_state( 5 downto 4) <= c_LED_OFF;
-- WR OK
bicolor_led_state( 7 downto 6) <= c_LED_OFF;
-- MULTICAST 0
bicolor_led_state( 9 downto 8) <= c_LED_OFF;
-- MULTICAST 1
bicolor_led_state(11 downto 10) <= c_LED_OFF;
-- I2C
bicolor_led_state(13 downto 12) <= c_LED_GREEN when (led_i2c = '1') else
c_LED_RED when (i2c_err_led = '1') else
c_LED_OFF;
-- State of TTL/TTL_N switch
bicolor_led_state(15 downto 14) <= c_LED_GREEN when (ttl_switch_n_i = '0') else
c_LED_OFF;
-- System error
bicolor_led_state(17 downto 16) <= c_LED_OFF;
-- System power
bicolor_led_state(19 downto 18) <= c_LED_GREEN;
-- MULTICAST 2
bicolor_led_state(21 downto 20) <= c_LED_OFF;
-- MULTICAST 3
bicolor_led_state(23 downto 22) <= c_LED_OFF;
cmp_bicolor_led_ctrl : bicolor_led_ctrl
generic map
(
g_NB_COLUMN => 6,
g_NB_LINE => 2,
g_clk_freq => 125000000,
g_refresh_rate => 250
)
port map
(
clk_i => clk125,
rst_n_i => rst_n,
led_intensity_i => "1111111",
led_state_i => bicolor_led_state,
column_o(0) => led_wr_ownaddr_i2c_o,
column_o(1) => led_wr_gmt_ttl_ttln_o,
column_o(2) => led_wr_link_syserror_o,
column_o(3) => led_wr_ok_syspw_o,
column_o(4) => led_multicast_2_0_o,
column_o(5) => led_multicast_3_1_o,
line_o(0) => led_ctrl0_o,
line_o(1) => led_ctrl1_o,
line_oen_o(0) => led_ctrl0_oen_o,
line_oen_o(1) => led_ctrl1_oen_o
);
end behav;
top/regtest/Manifest.py 0 → 100644
View file @ b4f23ad0
files = [
"regtest.ucf",
"regtest.vhd"
]
modules = {
"local" : [
"../../ip_cores/general-cores",
"../../reset_gen",
"../../bicolor_led_ctrl",
"../../vbcp_wb"
],
}
top/regtest/regtest.ucf 0 → 100644
View file @ b4f23ad0
##--==============================================================================
##-- CERN (BE-CO-HT)
##-- Glitch filter with selectable length
##--==============================================================================
##--
##-- author: Theodor Stana (t.stana@cern.ch)
##-- Carlos-Gil Soriano
##--
##-- date of creation: 2013-04-26
##--
##-- version: 1.0
##--
##-- description:
##-- This file contains the pin definitions for the CONV-TTL-BLO FPGA. The pin
##-- names reflect those of net names at the schematic level. To keep to CERN
##-- coding standards (http://www.ohwr.org/documents/24) and make the code more
##-- readable, the pin names have been lowercased and the pin type is indicated
##-- by its suffix. The suffix "_i" indicates an input pin, "_o" an output pin
##-- and "_b" a bidirectional pin.
##--
##-- An example of net name change is given below:
##-- LED_WR_OWNADDR_I2C -> led_wr_ownaddr_i2c_o
##--
##-- Apart from this, some pins have been renamed completely and do not resemble
##-- the schematics. These pins are:
##-- TTL/INV_TTL_N -> ttl_switch_n_i
##--
##-- dependencies:
##--
##-- references:
##--
##--==============================================================================
##-- GNU LESSER GENERAL PUBLIC LICENSE
##--==============================================================================
##-- This source file is free software; you can redistribute it and/or modify it
##-- under the terms of the GNU Lesser General Public License as published by the
##-- Free Software Foundation; either version 2.1 of the License, or (at your
##-- option) any later version. This source is distributed in the hope that it
##-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
##-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
##-- See the GNU Lesser General Public License for more details. You should have
##-- received a copy of the GNU Lesser General Public License along with this
##-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
##--==============================================================================
##-- last changes:
##-- 2013-04-26 Theodor Stana t.stana@cern.ch File modified
##--==============================================================================
##-- TODO: -
##--==============================================================================
##-----------------------------------------------------------------------------
##-- Default attributes
##--
##-- IOSTANDARD = "LVCMOS25"
##-- SLEW = "SLOW"
##-- DRIVE = "12"
##-----------------------------------------------------------------------------
#NET "rst_i" LOC = N20;
#NET "rst_i" IOSTANDARD = "LVCMOS33";
#NET "fpga_sysreset_n_i" LOC = L20;
NET "mr_n_o" LOC = T22;
NET "mr_n_o" IOSTANDARD = LVCMOS33;
# NET "clk20_vcxo_i" LOC = E16;
# NET "clk20_vcxo_i" TNM_NET=clk20_vcxo_i;
# TIMESPEC TSCLK20 = PERIOD "clk20_vcxo_i" 20 MHz HIGH 50 %;
NET "fpga_clk_p_i" LOC = H12;
NET "fpga_clk_n_i" LOC = G11;
##=============================================================================
##-- FRONT PANEL TTLs
##=============================================================================
##-----------------------------------------------------------------------------
##-- Status LEDs
##-----------------------------------------------------------------------------
NET "led_ctrl0_o" LOC = M18;
NET "led_ctrl0_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl0_oen_o" LOC = T20;
NET "led_ctrl0_oen_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_o" LOC = M17;
NET "led_ctrl1_o" IOSTANDARD = LVCMOS33;
NET "led_ctrl1_oen_o" LOC = U19;
NET "led_ctrl1_oen_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_2_0_o" LOC = P16;
NET "led_multicast_2_0_o" IOSTANDARD = LVCMOS33;
NET "led_multicast_3_1_o" LOC = P17;
NET "led_multicast_3_1_o" IOSTANDARD = LVCMOS33;
NET "led_wr_gmt_ttl_ttln_o" LOC = N16;
NET "led_wr_gmt_ttl_ttln_o" IOSTANDARD = LVCMOS33;
NET "led_wr_link_syserror_o" LOC = R15;
NET "led_wr_link_syserror_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ok_syspw_o" LOC = R16;
NET "led_wr_ok_syspw_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ownaddr_i2c_o" LOC = N15;
NET "led_wr_ownaddr_i2c_o" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Front channel LEDs
##-----------------------------------------------------------------------------
# NET "pulse_front_led_n_o[1]" LOC = H5;
# NET "pulse_front_led_n_o[1]" IOSTANDARD = LVCMOS33;
# NET "pulse_front_led_n_o[1]" DRIVE = 4;
# NET "pulse_front_led_n_o[1]" SLEW = QUIETIO;
# NET "pulse_front_led_n_o[2]" LOC = J6;
# NET "pulse_front_led_n_o[2]" IOSTANDARD = LVCMOS33;
# NET "pulse_front_led_n_o[2]" DRIVE = 4;
# NET "pulse_front_led_n_o[2]" SLEW = QUIETIO;
# NET "pulse_front_led_n_o[3]" LOC = K6;
# NET "pulse_front_led_n_o[3]" IOSTANDARD = LVCMOS33;
# NET "pulse_front_led_n_o[3]" DRIVE = 4;
# NET "pulse_front_led_n_o[3]" SLEW = QUIETIO;
# NET "pulse_front_led_n_o[4]" LOC = K5;
# NET "pulse_front_led_n_o[4]" IOSTANDARD = LVCMOS33;
# NET "pulse_front_led_n_o[4]" DRIVE = 4;
# NET "pulse_front_led_n_o[4]" SLEW = QUIETIO;
# NET "pulse_front_led_n_o[5]" LOC = M7;
# NET "pulse_front_led_n_o[5]" IOSTANDARD = LVCMOS33;
# NET "pulse_front_led_n_o[5]" DRIVE = 4;
# NET "pulse_front_led_n_o[5]" SLEW = QUIETIO;
# NET "pulse_front_led_n_o[6]" LOC = M6;
# NET "pulse_front_led_n_o[6]" IOSTANDARD = LVCMOS33;
# NET "pulse_front_led_n_o[6]" DRIVE = 4;
# NET "pulse_front_led_n_o[6]" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- Rear LEDs
##-----------------------------------------------------------------------------
# NET "pulse_rear_led_n_o[1]" LOC = AB17;
# NET "pulse_rear_led_n_o[1]" IOSTANDARD = LVCMOS33;
# NET "pulse_rear_led_n_o[1]" DRIVE = 4;
# NET "pulse_rear_led_n_o[1]" SLEW = QUIETIO;
# NET "pulse_rear_led_n_o[2]" LOC = AB19;
# NET "pulse_rear_led_n_o[2]" IOSTANDARD = LVCMOS33;
# NET "pulse_rear_led_n_o[2]" DRIVE = 4;
# NET "pulse_rear_led_n_o[2]" SLEW = QUIETIO;
# NET "pulse_rear_led_n_o[3]" LOC = AA16;
# NET "pulse_rear_led_n_o[3]" IOSTANDARD = LVCMOS33;
# NET "pulse_rear_led_n_o[3]" DRIVE = 4;
# NET "pulse_rear_led_n_o[3]" SLEW = QUIETIO;
# NET "pulse_rear_led_n_o[4]" LOC = AA18;
# NET "pulse_rear_led_n_o[4]" IOSTANDARD = LVCMOS33;
# NET "pulse_rear_led_n_o[4]" DRIVE = 4;
# NET "pulse_rear_led_n_o[4]" SLEW = QUIETIO;
# NET "pulse_rear_led_n_o[5]" LOC = AB16;
# NET "pulse_rear_led_n_o[5]" IOSTANDARD = LVCMOS33;
# NET "pulse_rear_led_n_o[5]" DRIVE = 4;
# NET "pulse_rear_led_n_o[5]" SLEW = QUIETIO;
# NET "pulse_rear_led_n_o[6]" LOC = AB18;
# NET "pulse_rear_led_n_o[6]" IOSTANDARD = LVCMOS33;
# NET "pulse_rear_led_n_o[6]" DRIVE = 4;
# NET "pulse_rear_led_n_o[6]" SLEW = QUIETIO;
#
##-----------------------------------------------------------------------------
##-- TTL trigger I/O
##-----------------------------------------------------------------------------
# NET "fpga_input_ttl_n_i[1]" LOC = T2;
# NET "fpga_input_ttl_n_i[1]" IOSTANDARD = LVCMOS33;
# NET "fpga_input_ttl_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "fpga_input_ttl_n_i[2]" LOC = U3;
# NET "fpga_input_ttl_n_i[2]" IOSTANDARD = LVCMOS33;
# NET "fpga_input_ttl_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "fpga_input_ttl_n_i[3]" LOC = V5;
# NET "fpga_input_ttl_n_i[3]" IOSTANDARD = LVCMOS33;
# NET "fpga_input_ttl_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "fpga_input_ttl_n_i[4]" LOC = W4;
# NET "fpga_input_ttl_n_i[4]" IOSTANDARD = LVCMOS33;
# NET "fpga_input_ttl_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "fpga_input_ttl_n_i[5]" LOC = T6;
# NET "fpga_input_ttl_n_i[5]" IOSTANDARD = LVCMOS33;
# NET "fpga_input_ttl_n_i[5]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "fpga_input_ttl_n_i[6]" LOC = T3;
# NET "fpga_input_ttl_n_i[6]" IOSTANDARD = LVCMOS33;
# NET "fpga_input_ttl_n_i[6]" CLOCK_DEDICATED_ROUTE = FALSE;
#
# NET "fpga_out_ttl_o[1]" LOC = C1;
# NET "fpga_out_ttl_o[1]" IOSTANDARD = LVCMOS33;
# NET "fpga_out_ttl_o[2]" LOC = F2;
# NET "fpga_out_ttl_o[2]" IOSTANDARD = LVCMOS33;
# NET "fpga_out_ttl_o[3]" LOC = F5;
# NET "fpga_out_ttl_o[3]" IOSTANDARD = LVCMOS33;
# NET "fpga_out_ttl_o[4]" LOC = H4;
# NET "fpga_out_ttl_o[4]" IOSTANDARD = LVCMOS33;
# NET "fpga_out_ttl_o[5]" LOC = J4;
# NET "fpga_out_ttl_o[5]" IOSTANDARD = LVCMOS33;
# NET "fpga_out_ttl_o[6]" LOC = H2;
# NET "fpga_out_ttl_o[6]" IOSTANDARD = LVCMOS33;
#
##-----------------------------------------------------------------------------
##-- Inverted TTL I/O
##-----------------------------------------------------------------------------
# NET "inv_in_n_i[1]" LOC = V2;
# NET "inv_in_n_i[1]" IOSTANDARD = LVCMOS33;
# NET "inv_in_n_i[1]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "inv_in_n_i[2]" LOC = W3;
# NET "inv_in_n_i[2]" IOSTANDARD = LVCMOS33;
# NET "inv_in_n_i[2]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "inv_in_n_i[3]" LOC = Y2;
# NET "inv_in_n_i[3]" IOSTANDARD = LVCMOS33;
# NET "inv_in_n_i[3]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "inv_in_n_i[4]" LOC = AA2;
# NET "inv_in_n_i[4]" IOSTANDARD = LVCMOS33;
# NET "inv_in_n_i[4]" CLOCK_DEDICATED_ROUTE = FALSE;
# NET "inv_out_o[1]" LOC = J3;
# NET "inv_out_o[1]" IOSTANDARD = LVCMOS33;
# NET "inv_out_o[2]" LOC = L3;
# NET "inv_out_o[2]" IOSTANDARD = LVCMOS33;
# NET "inv_out_o[3]" LOC = M3;
# NET "inv_out_o[3]" IOSTANDARD = LVCMOS33;
# NET "inv_out_o[4]" LOC = P2;
# NET "inv_out_o[4]" IOSTANDARD = LVCMOS33;
##=============================================================================
##-- RTM signals
##=============================================================================
##-----------------------------------------------------------------------------
##-- Blocking I/O
##-----------------------------------------------------------------------------
# NET "fpga_blo_in_i[1]" LOC = Y9;
# NET "fpga_blo_in_i[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_blo_in_i[2]" LOC = AA10;
# NET "fpga_blo_in_i[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_blo_in_i[3]" LOC = W12;
# NET "fpga_blo_in_i[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_blo_in_i[4]" LOC = AA6;
# NET "fpga_blo_in_i[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_blo_in_i[5]" LOC = Y7;
# NET "fpga_blo_in_i[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_blo_in_i[6]" LOC = AA8;
# NET "fpga_blo_in_i[6]" IOSTANDARD = "LVCMOS33";
#
# NET "fpga_trig_blo_o[1]" LOC = W9;
# NET "fpga_trig_blo_o[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_trig_blo_o[2]" LOC = T10;
# NET "fpga_trig_blo_o[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_trig_blo_o[3]" LOC = V7;
# NET "fpga_trig_blo_o[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_trig_blo_o[4]" LOC = U9;
# NET "fpga_trig_blo_o[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_trig_blo_o[5]" LOC = T8;
# NET "fpga_trig_blo_o[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_trig_blo_o[6]" LOC = R9;
# NET "fpga_trig_blo_o[6]" IOSTANDARD = "LVCMOS33";
##=============================================================================
##-- VME CONNECTOR SIGNALS
##=============================================================================
##-----------------------------------------------------------------------------
##-- I2C lines
##-----------------------------------------------------------------------------
NET "scl_i" LOC = F19;
NET "scl_i" IOSTANDARD = LVCMOS33;
NET "scl_o" LOC = E20;
NET "scl_o" IOSTANDARD = LVCMOS33;
NET "scl_o" DRIVE = 4;
NET "scl_oe_o" LOC = H18;
NET "scl_oe_o" IOSTANDARD = LVCMOS33;
NET "scl_oe_o" DRIVE = 4;
# NET "scl_oe_o" PULLDOWN;
NET "sda_i" LOC = G20;
NET "sda_i" IOSTANDARD = LVCMOS33;
NET "sda_o" LOC = F20;
NET "sda_o" IOSTANDARD = LVCMOS33;
NET "sda_o" SLEW = FAST;
NET "sda_o" DRIVE = 4;
# NET "sda_o" PULLUP;
NET "sda_oe_o" LOC = J19;
NET "sda_oe_o" IOSTANDARD = LVCMOS33;
NET "sda_oe_o" SLEW = FAST;
NET "sda_oe_o" DRIVE = 4;
# NET "sda_oe_o" PULLDOWN;
##-----------------------------------------------------------------------------
##-- Geographical Address
##-----------------------------------------------------------------------------
NET "fpga_ga_i[0]" LOC = H20;
NET "fpga_ga_i[0]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[1]" LOC = J20;
NET "fpga_ga_i[1]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[2]" LOC = K19;
NET "fpga_ga_i[2]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[3]" LOC = K20;
NET "fpga_ga_i[3]" IOSTANDARD = LVCMOS33;
NET "fpga_ga_i[4]" LOC = L19;
NET "fpga_ga_i[4]" IOSTANDARD = LVCMOS33;
NET "fpga_gap_i" LOC = H19;
NET "fpga_gap_i" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- ROM memory
###-----------------------------------------------------------------------------
#NET "fpga_prom_cclk_o" LOC = Y20;
#NET "fpga_prom_cclk_o" IOSTANDARD = "LVCMOS33";
#NET "fpga_prom_cso_b_n_o" LOC = AA3;
#NET "fpga_prom_cso_b_n_o" IOSTANDARD = "LVCMOS33";
#NET "fpga_prom_miso_i" LOC = AA20;
#NET "fpga_prom_miso_i" IOSTANDARD = "LVCMOS33";
#NET "fpga_prom_mosi_o" LOC = AB20;
#NET "fpga_prom_mosi_o" IOSTANDARD = "LVCMOS33";
#
#
###=============================================================================
###-- WHITE RABBIT
###=============================================================================
###-----------------------------------------------------------------------------
###-- Thermo for UID
###-----------------------------------------------------------------------------
#NET "thermometer_b" LOC = B1;
#NET "thermometer_b" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- DAC control
###-----------------------------------------------------------------------------
#NET "fpga_plldac1_din_o" LOC = AB14;
#NET "fpga_plldac1_din_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac1_sclk_o" LOC = AA14;
#NET "fpga_plldac1_sclk_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac1_sync_n_o" LOC = AB15;
#NET "fpga_plldac1_sync_n_o" IOSTANDARD = LVCMOS33;
#
#NET "fpga_plldac2_din_o" LOC = W14;
#NET "fpga_plldac2_din_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac2_sclk_o" LOC = Y14;
#NET "fpga_plldac2_sclk_o" IOSTANDARD = LVCMOS33;
#NET "fpga_plldac2_sync_n_o" LOC = W13;
#NET "fpga_plldac2_sync_n_o" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- SFP connection
###-----------------------------------------------------------------------------
##NET "fpga_sfp_los_i" LOC = G3;
## NET "fpga_sfp_los_i" IOSTANDARD = "LVCMOS33";
##NET "fpga_sfp_mod_def0_i" LOC = K8;
## NET "fpga_sfp_mod_def0_i" IOSTANDARD = "LVCMOS33";
##NET "fpga_sfp_rate_select_o" LOC = C4;
## NET "fpga_sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
#NET "fpga_sfp_mod_def1_b" LOC = G4;
#NET "fpga_sfp_mod_def1_b" IOSTANDARD = LVCMOS33;
#
#NET "fpga_sfp_mod_def2_b" LOC = F3;
#NET "fpga_sfp_mod_def2_b" IOSTANDARD = LVCMOS33;
##NET "fpga_sfp_tx_disable_o" LOC = E4;
## NET "fpga_sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
##NET "fpga_sfp_tx_fault_i" LOC = D2;
## NET "fpga_sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
###-----------------------------------------------------------------------------
###-- FPGA MGT lines
###-----------------------------------------------------------------------------
#NET "fpga_mgt_clk0_p_i" LOC = A10;
#NET "fpga_mgt_clk0_n_i" LOC = B10;
#
#NET "mgt_sfp_rx0_p_i" LOC = D7;
#NET "mgt_sfp_rx0_n_i" LOC = C7;
#
#NET "mgt_sfp_tx0_p_o" LOC = B6;
#NET "mgt_sfp_tx0_n_o" LOC = A6;
###=============================================================================
###-- ADDITIONAL PINS
###=============================================================================
# NET "fpga_oe_o" LOC = R3;
# NET "fpga_oe_o" IOSTANDARD = LVCMOS33;
# NET "fpga_oe_o" DRIVE = 4;
# NET "fpga_oe_o" SLEW = QUIETIO;
#
# NET "fpga_blo_oe_o" LOC = P5;
# NET "fpga_blo_oe_o" IOSTANDARD = LVCMOS33;
# NET "fpga_blo_oe_o" DRIVE = 4;
# NET "fpga_blo_oe_o" SLEW = QUIETIO;
# NET "fpga_trig_ttl_oe_o" LOC = N3;
# NET "fpga_trig_ttl_oe_o" IOSTANDARD = LVCMOS33;
# NET "fpga_trig_ttl_oe_o" DRIVE = 4;
# NET "fpga_trig_ttl_oe_o" SLEW = QUIETIO;
#
# NET "fpga_inv_oe_o" LOC = P6;
# NET "fpga_inv_oe_o" IOSTANDARD = LVCMOS33;
# NET "fpga_inv_oe_o" DRIVE = 4;
# NET "fpga_inv_oe_o" SLEW = QUIETIO;
##-----------------------------------------------------------------------------
##-- Configuration Switches
##-----------------------------------------------------------------------------
# NET "extra_switch_n_i[1]" LOC = F22;
# NET "extra_switch_n_i[1]" IOSTANDARD = "LVCMOS33";
# NET "extra_switch_n_i[2]" LOC = G22;
# NET "extra_switch_n_i[2]" IOSTANDARD = "LVCMOS33";
# NET "extra_switch_n_i[3]" LOC = H21;
# NET "extra_switch_n_i[3]" IOSTANDARD = "LVCMOS33";
# NET "extra_switch_n_i[4]" LOC = H22;
# NET "extra_switch_n_i[4]" IOSTANDARD = "LVCMOS33";
# NET "extra_switch_n_i[5]" LOC = J22;
# NET "extra_switch_n_i[5]" IOSTANDARD = "LVCMOS33";
# NET "extra_switch_n_i[6]" LOC = K21;
# NET "extra_switch_n_i[6]" IOSTANDARD = "LVCMOS33";
# NET "extra_switch_n_i[7]" LOC = K22;
# NET "extra_switch_n_i[7]" IOSTANDARD = "LVCMOS33";
# NET "ttl_switch_n_i" LOC = L22;
# NET "ttl_switch_n_i" IOSTANDARD = LVCMOS33;
##-----------------------------------------------------------------------------
##-- Motherboard and piggyback IDs
##-----------------------------------------------------------------------------
# NET "fpga_rtmm_n_i[0]" LOC = V21;
# NET "fpga_rtmm_n_i[0]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmm_n_i[1]" LOC = V22;
# NET "fpga_rtmm_n_i[1]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmm_n_i[2]" LOC = U22;
# NET "fpga_rtmm_n_i[2]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmp_n_i[0]" LOC = W22;
# NET "fpga_rtmp_n_i[0]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmp_n_i[1]" LOC = Y22;
# NET "fpga_rtmp_n_i[1]" IOSTANDARD = LVCMOS33;
# NET "fpga_rtmp_n_i[2]" LOC = Y21;
# NET "fpga_rtmp_n_i[2]" IOSTANDARD = LVCMOS33;
###-----------------------------------------------------------------------------
###-- General purpose
###-----------------------------------------------------------------------------
# NET "fpga_header_out_n_o[1]" LOC = F15;
# NET "fpga_header_out_n_o[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[2]" LOC = F16;
# NET "fpga_header_out_n_o[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[3]" LOC = F17;
# NET "fpga_header_out_n_o[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[4]" LOC = F14;
# NET "fpga_header_out_n_o[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[5]" LOC = H14;
# NET "fpga_header_out_n_o[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_out_n_o[6]" LOC = H13;
# NET "fpga_header_out_n_o[6]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[1]" LOC = A17;
# NET "fpga_header_in_n_i[1]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[2]" LOC = A18;
# NET "fpga_header_in_n_i[2]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[3]" LOC = B18;
# NET "fpga_header_in_n_i[3]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[4]" LOC = A19;
# NET "fpga_header_in_n_i[4]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[5]" LOC = A20;
# NET "fpga_header_in_n_i[5]" IOSTANDARD = "LVCMOS33";
# NET "fpga_header_in_n_i[6]" LOC = B20;
# NET "fpga_header_in_n_i[6]" IOSTANDARD = "LVCMOS33";
# NET "cmp_i2c_bridge/i2c_addr_i[6]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/i2c_addr_i[5]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/i2c_addr_i[4]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/i2c_addr_i[3]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/i2c_addr_i[2]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/i2c_addr_i[1]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/i2c_addr_i[0]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[7]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[6]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[5]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[4]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[3]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[2]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[1]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/rx_byte[0]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[11]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[10]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[9]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[8]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[7]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[6]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[5]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[4]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[3]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[2]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[1]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/wb_adr[0]" KEEP = "TRUE";
# NET "cmp_i2c_bridge/i2c_done_o" KEEP = "TRUE";
# NET "ram_we" KEEP = "TRUE";
# NET "xbar_master_out[0]_cyc" KEEP = "TRUE";
# NET "xbar_master_out[0]_stb" KEEP = "TRUE";
# NET "xbar_master_out[0]_we" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[11]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[10]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[9]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[8]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[7]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[6]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[5]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[4]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[3]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[2]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[1]" KEEP = "TRUE";
# NET "xbar_master_out[0]_adr[0]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[31]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[30]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[29]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[28]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[27]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[26]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[25]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[24]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[23]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[22]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[21]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[20]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[19]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[18]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[17]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[16]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[15]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[14]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[13]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[12]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[11]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[10]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[9]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[8]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[7]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[6]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[5]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[4]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[3]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[2]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[1]" KEEP = "TRUE";
# NET "xbar_master_out[0]_dat[0]" KEEP = "TRUE";
# NET "ram_ack" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[31]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[30]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[29]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[28]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[27]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[26]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[25]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[24]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[23]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[22]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[21]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[20]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[19]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[18]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[17]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[16]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[15]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[14]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[13]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[12]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[11]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[10]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[9]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[8]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[7]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[6]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[5]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[4]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[3]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[2]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[1]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_dat[0]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[31]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[30]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[29]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[28]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[27]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[26]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[25]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[24]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[23]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[22]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[21]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[20]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[19]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[18]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[17]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[16]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[15]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[14]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[13]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[12]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[11]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[10]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[9]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[8]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[7]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[6]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[5]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[4]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[3]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[2]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[1]" KEEP = "TRUE";
# NET "xbar_slave_in[0]_adr[0]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[31]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[30]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[29]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[28]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[27]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[26]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[25]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[24]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[23]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[22]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[21]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[20]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[19]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[18]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[17]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[16]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[15]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[14]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[13]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[12]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[11]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[10]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[9]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[8]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[7]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[6]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[5]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[4]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[3]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[2]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[1]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_dat[0]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[31]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[30]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[29]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[28]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[27]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[26]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[25]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[24]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[23]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[22]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[21]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[20]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[19]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[18]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[17]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[16]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[15]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[14]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[13]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[12]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[11]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[10]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[9]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[8]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[7]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[6]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[5]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[4]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[3]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[2]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[1]" KEEP = "TRUE";
# NET "xbar_master_in[0]_dat[0]" KEEP = "TRUE";
# NET "xbar_slave_out[0]_ack" KEEP = "TRUE";
# NET "xbar_slave_in[0]_cyc" KEEP = "TRUE";
# NET "xbar_slave_in[0]_we" KEEP = "TRUE";
# NET "xbar_slave_in[0]_stb" KEEP = "TRUE";
# NET "xbar_slave_out[0]_err" KEEP = "TRUE";
top/regtest/regtest.vhd 0 → 100644
View file @ b4f23ad0
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity of CONV-TTL-BLO
-- http://www.ohwr.org/projects/conv-ttl-blo
--------------------------------------------------------------------------------
--
-- unit name: regtest.vhd
--
-- author: Theodor-Adrian Stana (t.stana@cern.ch)
--
-- version: 1.0
--
-- description: Top entity of CONV-TTL-BLO
--
-- dependencies:
--
-- references:
-- [1] ELMA, Access to board data using SNMP and I2C
-- http://www.ohwr.org/documents/227
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use unisim.vcomponents.all;
use work.bicolor_led_ctrl_pkg.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
use work.genram_pkg.all;
entity regtest is
generic
(
g_nr_ttl_chan : natural := 6;
g_nr_inv_chan : natural := 4
);
port
(
-- Clock lines
fpga_clk_p_i : in std_logic; --Using the 125MHz clock
fpga_clk_n_i : in std_logic;
-- LEDs
led_ctrl0_o : out std_logic;
led_ctrl0_oen_o : out std_logic;
led_ctrl1_o : out std_logic;
led_ctrl1_oen_o : out std_logic;
led_multicast_2_0_o : out std_logic;
led_multicast_3_1_o : out std_logic;
led_wr_gmt_ttl_ttln_o : out std_logic;
led_wr_link_syserror_o : out std_logic;
led_wr_ok_syspw_o : out std_logic;
led_wr_ownaddr_i2c_o : out std_logic;
-- Lines for the i2c_slave
scl_i : in std_logic;
scl_o : out std_logic;
scl_oe_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
sda_oe_o : out std_logic;
fpga_ga_i : in std_logic_vector(4 downto 0);
fpga_gap_i : in std_logic;
-- It allows power sequencing of the 24V rail after a security delay
mr_n_o : out std_logic
);
end regtest;
architecture behav of regtest is
--============================================================================
-- Constant declarations
--============================================================================
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 1;
-----------------------------------------
-- Memory map
-- * all registers are word-addressable
-- * all registers are word-aligned
-----------------------------------------
-- MEM [000-FFF]
-----------------------------------------
-- slave order definitions
constant c_slv_mem : natural := 0;
-- base address definitions
constant c_addr_mem : t_wishbone_address := x"00000000";
-- address mask definitions
constant c_mask_mem : t_wishbone_address := x"00000000";
-- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_mem => c_addr_mem
);
-- masks constant for Wishbone crossbar
constant c_masks : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_mem => c_mask_mem
);
--============================================================================
-- Component declarations
--============================================================================
-- Reset generator component
-- (use: global reset generation, output reset generation)
component reset_gen is
generic
(
-- Reset time in number of clk_i cycles
g_reset_time : positive := 5_000_000
);
port
(
clk_i : in std_logic;
rst_i : in std_logic;
rst_n_o : out std_logic
);
end component reset_gen;
-- I2C bridge
-- (use: convert I2C transfers into WB transfers on memmapped registers)
component vbcp_wb is
port
(
-- Clock, reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- I2C lines
sda_en_o : out std_logic;
sda_i : in std_logic;
sda_o : out std_logic;
scl_en_o : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
-- I2C address and status
i2c_addr_i : in std_logic_vector(6 downto 0);
tip_o : out std_logic;
err_o : out std_logic;
-- Wishbone master signals
wbm_stb_o : out std_logic;
wbm_cyc_o : out std_logic;
wbm_sel_o : out std_logic_vector(3 downto 0);
wbm_we_o : out std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_adr_o : out std_logic_vector(31 downto 0);
wbm_ack_i : in std_logic;
wbm_rty_i : in std_logic;
wbm_err_i : in std_logic
);
end component vbcp_wb;
--============================================================================
-- Signal declarations
--============================================================================
-- Clock signals
signal clk125 : std_logic;
-- Reset signals
signal rst_n, rst : std_logic;
-- Wishbone crossbar signals
signal xbar_slave_in : t_wishbone_slave_in_array (c_nr_masters - 1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_nr_masters - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_nr_slaves - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array(c_nr_slaves - 1 downto 0);
-- RAM signals
signal ram_we : std_logic;
signal ram_ack : std_logic;
-- Signal for controlling the bicolor LED matrix
signal bicolor_led_state : std_logic_vector(23 downto 0);
-- I2C bridge signals
signal vbcp_done : std_logic;
signal vbcp_err : std_logic;
signal i2c_err_led : std_logic;
signal i2c_up : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0);
signal led_i2c : std_logic;
signal led_i2c_clkdiv : unsigned(22 downto 0);
signal led_i2c_cnt : unsigned( 2 downto 0);
signal blink_state : std_logic;
begin
--============================================================================
-- Generate 125 MHz global signal from differential lines
--============================================================================
cmp_125_diff_buf : IBUFGDS
generic map
(
DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE
)
port map
(
I => fpga_clk_p_i,
IB => fpga_clk_n_i,
O => clk125
);
--============================================================================
-- Internal and external reset generation
--============================================================================
-- Configure reset generator for 96ms power-on reset
cmp_reset_gen : reset_gen
generic map
(
-- Reset time: 12 * 8ns * (10**6) = 96 ms
g_reset_time => 12*(10**6)
)
port map
(
clk_i => clk125,
rst_i => '0',
rst_n_o => rst_n
);
-- rst <= not rst_n;
mr_n_o <= rst_n;
--============================================================================
-- I2C bridge logic
--============================================================================
-- Set the I2C address signal according to ELMA protocol [1]
i2c_addr <= "10" & fpga_ga_i;
-- Instantiate VBCP bridge component
cmp_i2c_bridge : vbcp_wb
port map
(
-- Clock, reset
clk_i => clk125,
rst_n_i => rst_n,
-- I2C lines
sda_en_o => sda_oe_o,
sda_i => sda_i,
sda_o => sda_o,
scl_en_o => scl_oe_o,
scl_i => scl_i,
scl_o => scl_o,
-- I2C address and status
i2c_addr_i => i2c_addr,
tip_o => vbcp_done,
err_o => vbcp_err,
-- Wishbone master signals
wbm_stb_o => xbar_slave_in(0).stb,
wbm_cyc_o => xbar_slave_in(0).cyc,
wbm_sel_o => xbar_slave_in(0).sel,
wbm_we_o => xbar_slave_in(0).we,
wbm_dat_i => xbar_slave_out(0).dat,
wbm_dat_o => xbar_slave_in(0).dat,
wbm_adr_o => xbar_slave_in(0).adr,
wbm_ack_i => xbar_slave_out(0).ack,
wbm_rty_i => xbar_slave_out(0).rty,
wbm_err_i => xbar_slave_out(0).err
);
-- Process to blink the LED for a finite amount of time when the vbcp_done
-- signal is set.
p_i2c_blink : process(clk125)
begin
if rising_edge(clk125) then
if (rst_n = '0') then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= (others => '0');
led_i2c <= '0';
blink_state <= '0';
else
case blink_state is
when '0' =>
led_i2c <= '0';
if (vbcp_done = '1') then
blink_state <= '1';
end if;
when '1' =>
led_i2c_clkdiv <= led_i2c_clkdiv + 1;
if (led_i2c_clkdiv = 2499999) then
led_i2c_clkdiv <= (others => '0');
led_i2c_cnt <= led_i2c_cnt + 1;
led_i2c <= not led_i2c;
if (led_i2c_cnt = 7) then
led_i2c_cnt <= (others => '0');
blink_state <= '0';
end if;
end if;
when others =>
blink_state <= '0';
end case;
end if;
end if;
end process p_i2c_blink;
-- Process to set the I2C error LED signal for display on the front panel
-- of the front module. The I2C error signal is permanently set once an
-- error is detected from the bridge module.
p_i2c_err_led : process (clk125) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
i2c_err_led <= '0';
elsif (vbcp_err = '1') then
i2c_err_led <= '1';
end if;
end if;
end process p_i2c_err_led;
--============================================================================
-- Instantiation and connection of the main Wishbone crossbar
--============================================================================
xbar_master_in(0).int <= '0';
xbar_master_in(0).err <= '0';
cmp_wb_crossbar : xwb_crossbar
generic map
(
g_num_masters => c_nr_masters,
g_num_slaves => c_nr_slaves,
g_registered => false,
g_address => c_addresses,
g_mask => c_masks
)
port map
(
clk_sys_i => clk125,
rst_n_i => rst_n,
slave_i => xbar_slave_in,
slave_o => xbar_slave_out,
master_i => xbar_master_in,
master_o => xbar_master_out
);
--============================================================================
-- Instantiate single-port RAM
--============================================================================
cmp_memory: generic_spram
generic map (
g_data_width => 32,
g_size => 2**12
)
port map (
rst_n_i => rst_n,
clk_i => clk125,
bwe_i => (others => '0'),
we_i => ram_we,
a_i => xbar_master_out(c_slv_mem).adr(11 downto 0),
d_i => xbar_master_out(c_slv_mem).dat,
q_o => xbar_master_in(c_slv_mem).dat
);
ram_we <= xbar_master_out(c_slv_mem).we and xbar_master_out(c_slv_mem).stb and
xbar_master_out(c_slv_mem).cyc;
xbar_master_in(c_slv_mem).ack <= ram_ack;
xbar_master_in(c_slv_mem).err <= '0';
p_ram_ack : process (clk125) is
begin
if rising_edge(clk125) then
if (rst_n = '0') then
ram_ack <= '0';
else
ram_ack <= '0';
if (xbar_master_out(c_slv_mem).stb = '1') and
(xbar_master_out(c_slv_mem).cyc = '1') then
ram_ack <= '1';
end if;
end if;
end if;
end process p_ram_ack;
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
-- Bicolor LED controls, corresponding to the column orders on the
-- bicolor_led_ctrl unit.
-- WR address
bicolor_led_state( 1 downto 0) <= c_LED_OFF;
-- WR GMT
bicolor_led_state( 3 downto 2) <= c_LED_OFF;
-- WR link
bicolor_led_state( 5 downto 4) <= c_LED_OFF;
-- WR OK
bicolor_led_state( 7 downto 6) <= c_LED_OFF;
-- MULTICAST 0
bicolor_led_state( 9 downto 8) <= c_LED_OFF;
-- MULTICAST 1
bicolor_led_state(11 downto 10) <= c_LED_OFF;
-- I2C
bicolor_led_state(13 downto 12) <= c_LED_GREEN when (led_i2c = '1') else
c_LED_RED when (i2c_err_led = '1') else
c_LED_OFF;
-- State of TTL/TTL_N switch
bicolor_led_state(15 downto 14) <= c_LED_OFF;
-- System error
bicolor_led_state(17 downto 16) <= c_LED_OFF;
-- System power
bicolor_led_state(19 downto 18) <= c_LED_GREEN;
-- MULTICAST 2
bicolor_led_state(21 downto 20) <= c_LED_OFF;
-- MULTICAST 3
bicolor_led_state(23 downto 22) <= c_LED_OFF;
cmp_bicolor_led_ctrl : bicolor_led_ctrl
generic map
(
g_NB_COLUMN => 6,
g_NB_LINE => 2,
g_clk_freq => 125000000,
g_refresh_rate => 250
)
port map
(
clk_i => clk125,
rst_n_i => rst_n,
led_intensity_i => "1111111",
led_state_i => bicolor_led_state,
column_o(0) => led_wr_ownaddr_i2c_o,
column_o(1) => led_wr_gmt_ttl_ttln_o,
column_o(2) => led_wr_link_syserror_o,
column_o(3) => led_wr_ok_syspw_o,
column_o(4) => led_multicast_2_0_o,
column_o(5) => led_multicast_3_1_o,
line_o(0) => led_ctrl0_o,
line_o(1) => led_ctrl1_o,
line_oen_o(0) => led_ctrl0_oen_o,
line_oen_o(1) => led_ctrl1_oen_o
);
end behav;
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment