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Conv TTL Blocking - Gateware
Commit f68e5997 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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work towards new folder structure 

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 2679be0d
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hdl/test_trigleds_wb/test_trigleds.wb deleted 100644 → 0
View file @ 2679be0d
peripheral {
name = "Trigger LEDs thru WB interface";
description = "WB for trigger LEDs";
hdl_entity = "test_trigleds_wb";
prefix = "trigleds";
reg {
name = "LED";
prefix = "reg";
field {
name = "Bits";
prefix = "bits";
type = SLV;
size = 6;
};
};
};
hdl/test_trigleds_wb/test_trigleds.wb~ deleted 100644 → 0
View file @ 2679be0d
peripheral {
name = "Trigger LEDs thru WB interface";
description = "WB for trigger LEDs";
hdl_entity = "test_triggleds_wb";
prefix = "trigleds";
reg {
name = "LED";
prefix = "reg";
field {
name = "Bits";
prefix = "bits";
type = SLV;
size = 6;
};
};
};
hdl/test_trigleds_wb/test_trigleds_wb.vhd deleted 100644 → 0
View file @ 2679be0d
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Trigger LEDs thru WB interface
---------------------------------------------------------------------------------------
-- File : test_trigleds_wb.vhd
-- Author : auto-generated by wbgen2 from test_trigleds.wb
-- Created : Thu Feb 7 13:55:26 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE test_trigleds.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test_trigleds_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'Bits' in reg: 'LED'
trigleds_reg_bits_o : out std_logic_vector(5 downto 0)
);
end test_trigleds_wb;
architecture syn of test_trigleds_wb is
signal trigleds_reg_bits_int : std_logic_vector(5 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(0 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
trigleds_reg_bits_int <= "000000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
if (wb_we_i = '1') then
trigleds_reg_bits_int <= wrdata_reg(5 downto 0);
end if;
rddata_reg(5 downto 0) <= trigleds_reg_bits_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Bits
trigleds_reg_bits_o <= trigleds_reg_bits_int;
rwaddr_reg <= (others => '0');
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/vbcp_wb/rtl/i2c_slave.vhd
View file @ f68e5997
......@@ -274,28 +274,28 @@ begin
--============================================================================
-- Tick generation
--============================================================================
p_tick : process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
tick_cnt <= '0';
tick_p <= '0';
elsif (scl_f_edge_p = '1') then
tick_en <= '1';
else
if (tick_en = '1') then
tick_cnt <= tick_cnt + 1;
tick_p <= '0';
if (tick_cnt = (tick_cnt'range => '1')) then
tick_p <= '1';
tick_en <= '0';
end if;
else
tick_p <= '0';
end if;
end if;
end if;
end process p_tick;
-- p_tick : process (clk_i) is
-- begin
-- if rising_edge(clk_i) then
-- if (rst_n_i = '0') then
-- tick_cnt <= '0';
-- tick_p <= '0';
-- elsif (scl_f_edge_p = '1') then
-- tick_en <= '1';
-- else
-- if (tick_en = '1') then
-- tick_cnt <= tick_cnt + 1;
-- tick_p <= '0';
-- if (tick_cnt = (tick_cnt'range => '1')) then
-- tick_p <= '1';
-- tick_en <= '0';
-- end if;
-- else
-- tick_p <= '0';
-- end if;
-- end if;
-- end if;
-- end process p_tick;
--============================================================================
-- FSM logic
......
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