Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
C
Conv TTL Blocking - Gateware
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
1
Issues
1
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Conv TTL Blocking - Gateware
Commits
a485a730
Commit
a485a730
authored
Sep 27, 2018
by
Denia Bouhired-Ferrag
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
minor stylistic changes. Commits golden and release projects
parent
ccc33882
Expand all
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
138 additions
and
139 deletions
+138
-139
conv_ttl_blo.xise
syn/Release/conv_ttl_blo.xise
+15
-17
conv_ttl_blo.vhd
top/Golden/conv_ttl_blo.vhd
+90
-89
conv_ttl_blo.vhd
top/Release/conv_ttl_blo.vhd
+33
-33
No files found.
syn/Release/conv_ttl_blo.xise
View file @
a485a730
...
...
@@ -115,7 +115,7 @@
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"19"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"19"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/
general-cores/
modules/genrams/common/generic_shiftreg_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
</file>
...
...
@@ -123,11 +123,11 @@
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/
general-cores/
modules/genrams/common/inferred_async_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"9"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"9"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/ip_cores/general-cores/
general-cores/
modules/genrams/common/inferred_sync_fifo.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"0"
/>
</file>
...
...
@@ -513,7 +513,7 @@
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/modules/wf_decr_counter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"22"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
1
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"2
2
"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/top/conv_common_gw.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"36"
/>
...
...
@@ -541,10 +541,7 @@
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"37"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"37"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/modules/fastevent_counter.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"21"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"22"
/>
</file>
<file
xil_pn:name=
"../../ip_cores/conv-common-gw/modules/fastevent_counter.vhd"
xil_pn:type=
"FILE_VHDL"
/>
<file
xil_pn:name=
"../../sim/Release/fastevent_counter_tb.vhd"
xil_pn:type=
"FILE_VHDL"
/>
<file
xil_pn:name=
"chipscope_ila.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"BehavioralSimulation"
xil_pn:seqID=
"0"
/>
...
...
@@ -649,9 +646,9 @@
<property
xil_pn:name=
"FSM Style"
xil_pn:value=
"LUT"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Filter Files From Compile Order"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Flatten Output Netlist"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Functional Model Target Language ArchWiz"
xil_pn:value=
"V
HDL
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Functional Model Target Language Coregen"
xil_pn:value=
"V
HDL
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Functional Model Target Language Schematic"
xil_pn:value=
"V
HDL
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Functional Model Target Language ArchWiz"
xil_pn:value=
"V
erilog
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Functional Model Target Language Coregen"
xil_pn:value=
"V
erilog
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Functional Model Target Language Schematic"
xil_pn:value=
"V
erilog
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"GTS Cycle During Suspend/Wakeup Sequence spartan6"
xil_pn:value=
"4"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"GWE Cycle During Suspend/Wakeup Sequence spartan6"
xil_pn:value=
"5"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Generate Architecture Only (No Entity Declaration)"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
...
...
@@ -692,7 +689,7 @@
<property
xil_pn:name=
"Include sdf_annotate task in Verilog File"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Incremental Compilation"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Insert Buffers to Prevent Pulse Swallowing"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Instantiation Template Target Language Xps"
xil_pn:value=
"V
HDL
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Instantiation Template Target Language Xps"
xil_pn:value=
"V
erilog
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"JTAG Pin TCK"
xil_pn:value=
"Pull Up"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"JTAG Pin TDI"
xil_pn:value=
"Pull Up"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"JTAG Pin TDO"
xil_pn:value=
"Pull Up"
xil_pn:valueState=
"default"
/>
...
...
@@ -779,10 +776,11 @@
<property
xil_pn:name=
"Power Reduction Map spartan6"
xil_pn:value=
"Off"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Power Reduction Par"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Power Reduction Xst"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Preferred Language"
xil_pn:value=
"V
HDL"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Preferred Language"
xil_pn:value=
"V
erilog"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Process window"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Produce Verbose Report"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Project Description"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Project Generator"
xil_pn:value=
"ProjNav"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Property Specification in Project File"
xil_pn:value=
"Store all values"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"RAM Extraction"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"RAM Style"
xil_pn:value=
"Auto"
xil_pn:valueState=
"default"
/>
...
...
@@ -821,8 +819,8 @@
<property
xil_pn:name=
"Run for Specified Time Translate"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Safe Implementation"
xil_pn:value=
"No"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Security"
xil_pn:value=
"Enable Readback and Reconfiguration"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Module Instance Name"
xil_pn:value=
"/
conv_burst_ctrl
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Behavioral"
xil_pn:value=
"work.
conv_burst_ctrl
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Selected Module Instance Name"
xil_pn:value=
"/
testbench
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Behavioral"
xil_pn:value=
"work.
testbench
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Post-Map"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Post-Route"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Selected Simulation Root Source Node Post-Translate"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
...
...
@@ -833,7 +831,7 @@
<property
xil_pn:name=
"Shift Register Minimum Size spartan6"
xil_pn:value=
"2"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Show All Models"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Signal window"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Model Target"
xil_pn:value=
"VHDL"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Model Target"
xil_pn:value=
"VHDL"
xil_pn:valueState=
"
non-
default"
/>
<property
xil_pn:name=
"Simulation Resolution"
xil_pn:value=
"Default (1 ps)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Run Time ISim"
xil_pn:value=
"1000 ns"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Simulation Run Time Map"
xil_pn:value=
"1000 ns"
xil_pn:valueState=
"default"
/>
...
...
@@ -845,7 +843,7 @@
<property
xil_pn:name=
"Source window"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify 'define Macro Name and Value"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Behavioral"
xil_pn:value=
"work.
conv_burst_ctrl
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Behavioral"
xil_pn:value=
"work.
testbench
"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Post-Map"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Post-Route"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Specify Top Level Instance Names Post-Translate"
xil_pn:value=
"Default"
xil_pn:valueState=
"default"
/>
...
...
top/Golden/conv_ttl_blo.vhd
View file @
a485a730
This diff is collapsed.
Click to expand it.
top/Release/conv_ttl_blo.vhd
View file @
a485a730
...
...
@@ -71,10 +71,10 @@ entity conv_ttl_blo is
vme_sysreset_n_i
:
in
std_logic
;
vme_ga_i
:
in
std_logic_vector
(
4
downto
0
);
vme_gap_i
:
in
std_logic
;
-- PCB version recognition
pcbrev_i
:
in
std_logic_vector
(
5
downto
0
);
pcbrev_i
:
in
std_logic_vector
(
5
downto
0
);
-- Channel enable
global_oen_o
:
out
std_logic
;
ttl_oen_o
:
out
std_logic
;
...
...
@@ -174,8 +174,8 @@ architecture arch of conv_ttl_blo is
type
t_ttlbar_nosig_cnt
is
array
(
c_nr_chans
-1
downto
0
)
of
unsigned
(
10
downto
0
);
--Array of constants for temperature model implemented for long long mode
type
t_temp_decre_step_lg
is
array
(
0
to
14
)
of
integer
;
--Array of constants for temperature model implemented for long long mode
type
t_temp_decre_step_lg
is
array
(
0
to
14
)
of
integer
;
--============================================================================
-- Signal declarations
...
...
@@ -186,15 +186,15 @@ architecture arch of conv_ttl_blo is
-- TTL & RS485 signals
signal
rs485_fs
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
signal
pulse_in
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
signal
inv_pulse_in_n
:
std_logic_vector
(
c_nr_inv_chans
-1
downto
0
);
signal
inv_pulse_in_n
:
std_logic_vector
(
c_nr_inv_chans
-1
downto
0
);
signal
pulse_out
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
signal
inv_pulse_out
:
std_logic_vector
(
c_nr_inv_chans
-1
downto
0
);
signal
inv_pulse_out
:
std_logic_vector
(
c_nr_inv_chans
-1
downto
0
);
signal
pulse_ttl
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
signal
pulse_blo
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
signal
inhibit_first_pulse
:
std_logic
;
signal
inhibit_first_pulse_d0
:
std_logic
;
signal
inhibit_cnt
:
unsigned
(
10
downto
0
);
--Temperature model constantstemp_decre_step_lg
signal
temp_decre_step_lg
:
t_temp_decre_step
;
signal
temp_decre_step_sh
:
t_temp_decre_step
;
...
...
@@ -217,7 +217,7 @@ architecture arch of conv_ttl_blo is
-- Channel LED signals
signal
led_pulse
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
signal
led_inv_pulse
:
std_logic_vector
(
c_nr_inv_chans
-1
downto
0
);
signal
led_inv_pulse
:
std_logic_vector
(
c_nr_inv_chans
-1
downto
0
);
signal
led_rear
:
std_logic_vector
(
c_nr_chans
-1
downto
0
);
-- I2C LEDs
...
...
@@ -250,7 +250,7 @@ begin
--
-- The counter is disabled if the switch is set for TTL signals, to avoid
-- unnecessary power consumption by the counter
p_ttlbar_nosig
:
process
(
clk_20_i
)
begin
if
rising_edge
(
clk_20_i
)
then
...
...
@@ -286,7 +286,7 @@ begin
inhibit_first_pulse
<=
'1'
;
elsif
(
inhibit_first_pulse
=
'1'
)
then
inhibit_cnt
<=
inhibit_cnt
+
1
;
if
(
inhibit_cnt
=
1999
)
then
if
(
inhibit_cnt
=
1999
)
then
inhibit_first_pulse
<=
'0'
;
end
if
;
end
if
;
...
...
@@ -305,7 +305,7 @@ begin
end
if
;
end
if
;
end
process
;
-- Pulse input valid only after inhibit period is over
pulse_in
<=
(
pulse_ttl
or
pulse_blo
)
when
(
inhibit_first_pulse_d0
=
'0'
)
else
(
others
=>
'0'
);
...
...
@@ -320,18 +320,18 @@ begin
-- Burst mode functionality is enabled for versions 4 and above
-- when version is below 4 then disable burst functionality
burst_en_n
<=
'0'
when
pcbrev_i
(
5
downto
0
)
>=
"010000"
else
'1'
;
--*******************************************************************************
--*******************************************************************************
-- This change code is only used as a hack for v3 boards, which are physically
-- This change code is only used as a hack for v3 boards, which are physically
-- able to support v4 functionality, but do not have built-in pcb version support
-- burst_en_n <= '0' when sw_gp_n_i(6)= '0'
-- else '1';
-- else '1';
--*******************************************************************************
--*******************************************************************************
--*******************************************************************************
--============================================================================
-- Instantiate common generic gateware for converter boards
--============================================================================
...
...
@@ -343,13 +343,13 @@ begin
g_board_id
=>
c_board_id
,
g_gwvers
=>
c_gwvers
,
g_pgen_fixed_width
=>
true
,
g_pgen_pwidth_lg
=>
24
,
g_pgen_pwidth_lg
=>
24
,
g_pgen_pwidth_sh
=>
5
,
g_pgen_pperiod_cont
=>
4800
,
-- Maximum period supported for 1.2us pulse ~ max freq 104kHz
g_pgen_pperiod_lg
=>
191
,
g_pgen_pperiod_lg
=>
191
,
-- Maximum period supported for 250ns pulse ~ max freq 2MHz
g_pgen_pperiod_sh
=>
9
,
g_pgen_pperiod_sh
=>
9
,
g_pgen_gf_len
=>
1
,
g_temp_decre_step_lg
=>
(
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
2500
,
731
,
220
,
250
,
40
,
85
,
50
,
125
),
g_temp_decre_step_sh
=>
(
0
,
0
,
769
,
31
,
104
,
14
,
82
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
,
0
),
...
...
@@ -357,7 +357,7 @@ begin
g_burstctrl_1_pulse_temp_rise_sh
=>
x"01388"
,
--5000
g_burstctrl_max_temp_lg_sh
=>
x"02540BE400"
,
-- 10^10 --In final release use this value
-- g_burstctrl_max_temp_lg_sh=> x"00000F4240", --10^6 --This value is used to speed up simulation
g_with_pulse_cnt
=>
true
,
g_with_pulse_timetag
=>
true
,
g_with_man_trig
=>
true
,
...
...
@@ -378,17 +378,17 @@ begin
-- Glitch filter active-low enable signal
gf_en_n_i
=>
sw_gp_n_i
(
0
),
-- Burst mode enable signal. Mode disabled for all versions of board
burst_en_n_i
=>
burst_en_n
,
-- Pulse width selection, port low means 250ns, high means 1.2us.
-- Pulse width selection, port low means 250ns, high means 1.2us.
-- Switch to determine short or long pulse mode.
-- ON switch means SHORT 250ns pulse repetition with max frequency 2MHz
-- OFF switch means LONG 1.2us pulse repetition with max freq ~104kHz
pulse_width_sel_n_i
=>
sw_gp_n_i
(
1
),
-- Channel enable
global_ch_oen_o
=>
global_oen_o
,
pulse_front_oen_o
=>
ttl_oen_o
,
...
...
@@ -398,7 +398,7 @@ begin
-- Front panel channels
pulse_i
=>
pulse_in
,
pulse_front_i
=>
pulse_ttl
,
pulse_rear_i
=>
pulse_blo
,
pulse_rear_i
=>
pulse_blo
,
pulse_o
=>
pulse_out
,
-- Inverted pulse I/O
...
...
@@ -407,10 +407,10 @@ begin
-- Channel leds
led_pulse_o
=>
led_pulse
,
-- inverted channel leds
led_inv_pulse_o
=>
led_inv_pulse
,
led_inv_pulse_o
=>
led_inv_pulse
,
-- I2C LED signals -- connect to a bicolor LED of choice
-- led_i2c_o pulses four times on I2C transfer
led_i2c_o
=>
led_i2c
,
...
...
@@ -459,7 +459,7 @@ begin
-- PCB Version information
hwvers_i
=>
pcbrev_i
,
-- RTM lines
rtmm_i
=>
rtmm_i
,
rtmp_i
=>
rtmp_i
,
...
...
@@ -500,9 +500,9 @@ begin
-----------------------------------------
-- LED outputs
led_front_n_o
<=
not
led_pulse
;
led_front_inv_n_o
<=
not
led_inv_pulse
;
led_rear_n_o
<=
not
led_pulse
;
-- INV-TTL outputs
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment