I2C write seems to work fine, read is still a problem. Creating secondary branch…

I2C write seems to work fine, read is still a problem. Creating secondary branch to fix bicolor LEDs and switching to it.

I2C write seems to work fine, read is still a problem. Creating secondary branch…
I2C write seems to work fine, read is still a problem. Creating secondary branch to fix bicolor LEDs and switching to it.
8ec83b57 · Theodor-Adrian Stana · d80c5f82 · 8ec83b57 · 8ec83b57 · 8ec83b57
Commit 8ec83b57 authored Feb 14, 2013 by Theodor-Adrian Stana
12 changed files
--- a/.gitignore
+++ b/.gitignore
+captures/
--- a/hdl/IMAGES/image1/constraints/V2/BloV2.ucf
+++ b/hdl/IMAGES/image1/constraints/V2/BloV2.ucf
@@ -412,174 +412,575 @@ NET "FPGA_RTMP_N[2]" IOSTANDARD = LVCMOS33;
 # NET "FPGA_HEADER_IN_N[5]"     IOSTANDARD = "LVCMOS33";
 # NET "FPGA_HEADER_IN_N[6]"     LOC = B20;
 # NET "FPGA_HEADER_IN_N[6]"     IOSTANDARD = "LVCMOS33";
-NET "inst_image1_core/cmp_test_trigleds/trigleds_reg_bits_int[5]" KEEP = "TRUE";
-NET "inst_image1_core/cmp_test_trigleds/trigleds_reg_bits_int[4]" KEEP = "TRUE";
-NET "inst_image1_core/cmp_test_trigleds/trigleds_reg_bits_int[3]" KEEP = "TRUE";
-NET "inst_image1_core/cmp_test_trigleds/trigleds_reg_bits_int[2]" KEEP = "TRUE";
-NET "inst_image1_core/cmp_test_trigleds/trigleds_reg_bits_int[1]" KEEP = "TRUE";
+#NET "inst_image1_core/cmp_test_trigleds/trigleds_reg_bits_int[5]" KEEP = "TRUE";
-NET "inst_image1_core/cmp_test_trigleds/trigleds_reg_bits_int[0]" KEEP = "TRUE";
+#NET "inst_image1_core/cmp_test_trigleds/trigleds_reg_bits_int[4]" KEEP = "TRUE";
-NET "inst_image1_core/cmp_test_trigleds/wb_dat_i[5]" KEEP = "TRUE";
+#NET "inst_image1_core/cmp_test_trigleds/trigleds_reg_bits_int[3]" KEEP = "TRUE";
-NET "inst_image1_core/cmp_test_trigleds/wb_dat_i[4]" KEEP = "TRUE";
+#NET "inst_image1_core/cmp_test_trigleds/trigleds_reg_bits_int[2]" KEEP = "TRUE";
-NET "inst_image1_core/cmp_test_trigleds/wb_dat_i[3]" KEEP = "TRUE";
+#NET "inst_image1_core/cmp_test_trigleds/trigleds_reg_bits_int[1]" KEEP = "TRUE";
-NET "inst_image1_core/cmp_test_trigleds/wb_dat_i[2]" KEEP = "TRUE";
+#NET "inst_image1_core/cmp_test_trigleds/trigleds_reg_bits_int[0]" KEEP = "TRUE";
-NET "inst_image1_core/cmp_test_trigleds/wb_dat_i[1]" KEEP = "TRUE";
+#NET "inst_image1_core/cmp_test_trigleds/wb_dat_i[5]" KEEP = "TRUE";
-NET "inst_image1_core/cmp_test_trigleds/wb_dat_i[0]" KEEP = "TRUE";
+#NET "inst_image1_core/cmp_test_trigleds/wb_dat_i[4]" KEEP = "TRUE";
-NET "inst_image1_core/cmp_test_trigleds/wb_cyc_i" KEEP = "TRUE";
+#NET "inst_image1_core/cmp_test_trigleds/wb_dat_i[3]" KEEP = "TRUE";
-NET "inst_image1_core/cmp_test_trigleds/wb_stb_i" KEEP = "TRUE";
+#NET "inst_image1_core/cmp_test_trigleds/wb_dat_i[2]" KEEP = "TRUE";
-NET "inst_image1_core/cmp_test_trigleds/wb_we_i" KEEP = "TRUE";
+#NET "inst_image1_core/cmp_test_trigleds/wb_dat_i[1]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[31]" KEEP = "TRUE";
+#NET "inst_image1_core/cmp_test_trigleds/wb_dat_i[0]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[30]" KEEP = "TRUE";
+#NET "inst_image1_core/cmp_test_trigleds/wb_cyc_i" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[29]" KEEP = "TRUE";
+#NET "inst_image1_core/cmp_test_trigleds/wb_stb_i" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[28]" KEEP = "TRUE";
+#NET "inst_image1_core/cmp_test_trigleds/wb_we_i" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[27]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[31]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[26]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[30]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[25]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[29]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[24]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[28]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[23]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[27]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[22]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[26]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[21]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[25]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[20]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[24]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[19]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[23]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[18]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[22]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[17]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[21]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[16]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[20]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[15]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[19]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[14]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[18]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[13]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[17]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[12]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[16]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[11]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[15]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[10]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[14]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[9]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[13]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[8]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[12]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[7]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[11]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[6]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[10]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[5]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[9]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[4]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[8]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[7]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[6]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[1]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[5]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[0]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[4]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[31]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[3]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[30]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[2]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[29]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[1]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[28]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_i[0]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[27]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[31]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[26]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[30]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[25]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[29]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[24]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[28]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[23]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[27]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[22]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[26]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[21]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[25]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[20]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[24]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[19]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[23]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[18]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[22]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[17]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[21]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[16]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[20]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[15]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[19]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[14]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[18]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[13]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[17]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[12]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[16]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[11]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[15]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[10]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[14]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[9]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[13]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[8]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[12]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[7]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[11]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[6]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[10]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[5]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[9]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[4]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[8]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[7]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[6]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[1]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[5]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[0]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[4]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_addr_i[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[3]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_addr_i[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[2]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_addr_i[1]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[1]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_addr_i[0]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_i[0]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[31]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_addr_i[3]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[30]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_addr_i[2]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[29]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_addr_i[1]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[28]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_addr_i[0]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[27]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[31]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[26]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[30]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[25]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[29]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[24]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[28]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[23]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[27]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[22]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[26]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[21]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[25]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[20]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[24]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[19]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[23]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[18]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[22]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[17]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[21]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[16]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[20]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[15]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[19]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[14]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[18]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[13]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[17]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[12]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[16]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[11]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[15]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[10]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[14]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[9]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[13]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[8]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[12]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[7]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[11]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[6]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[10]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[5]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[9]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[4]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[8]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[7]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[6]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[1]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[5]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[0]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[4]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[15]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[3]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[14]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[2]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[13]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[1]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[12]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_data_o[0]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[11]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[15]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[10]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[14]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[9]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[13]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[8]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[12]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[7]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[11]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[6]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[10]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[5]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[9]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[4]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[8]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[7]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[6]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[1]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[5]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[0]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[4]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[31]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[3]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[30]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[2]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[29]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[1]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[28]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_addr_o[0]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[27]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[31]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[26]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[30]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[25]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[29]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[24]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[28]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[23]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[27]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[22]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[26]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[21]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[25]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[20]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[24]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[19]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[23]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[18]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[22]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[17]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[21]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[16]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[20]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[15]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[19]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[14]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[18]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[13]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[17]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[12]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[16]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[11]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[15]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[10]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[14]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[9]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[13]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[8]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[12]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[7]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[11]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[6]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[10]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[5]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[9]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[4]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[8]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[7]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[6]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[1]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[5]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[0]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[4]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_ack_i" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[3]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_cyc_o" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[2]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_stb_o" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[1]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_master_we_o" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_data_o[0]" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_ack_o" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_ack_i" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_cyc_i" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_cyc_o" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_stb_i" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_stb_o" KEEP = "TRUE";
-NET "inst_image1_core/inst_i2c_slave/wb_slave_we_i" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_master_we_o" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_ack_o" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_cyc_i" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_stb_i" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/wb_slave_we_i" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[31]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[30]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[29]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[28]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[27]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[26]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[25]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[24]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[23]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[22]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[21]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[20]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[19]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[18]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[17]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[16]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[15]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[14]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[13]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[12]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[11]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[10]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[9]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[8]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[7]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[6]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[5]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[4]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[1]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[0]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[63]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[62]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[61]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[60]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[59]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[58]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[57]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[56]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[55]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[54]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[53]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[52]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[51]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[50]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[49]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[48]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[47]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[46]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[45]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[44]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[43]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[42]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[41]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[40]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[39]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[38]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[37]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[36]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[35]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[34]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[33]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRX_slv[32]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[15]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[14]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[13]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[12]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[11]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[10]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[9]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[8]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[7]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[6]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[5]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[4]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[1]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[0]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[31]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[30]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[29]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[28]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[27]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[26]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[25]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[24]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[23]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[22]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[21]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[20]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[19]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[18]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[17]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXA_i[16]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[15]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[14]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[13]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[12]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[11]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[10]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[9]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[8]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[7]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[6]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[5]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[4]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[1]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[0]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[31]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[30]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[29]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[28]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[27]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[26]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[25]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[24]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[23]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[22]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[21]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[20]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[19]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[18]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[17]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/DRXB_i[16]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_adr[15]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_adr[14]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_adr[13]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_adr[12]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_adr[11]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_adr[10]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_adr[9]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_adr[8]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_adr[7]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_adr[6]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_adr[5]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_adr[4]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_adr[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_adr[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_dat[5]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_dat[4]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_dat[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_dat[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_dat[1]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_dat[0]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[1]_dat[5]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[1]_dat[4]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[1]_dat[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[1]_dat[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[1]_dat[1]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[1]_dat[0]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[31]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[30]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[29]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[28]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[27]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[26]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[25]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[24]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[23]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[22]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[21]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[20]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[19]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[18]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[17]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[16]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[15]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[14]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[13]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[12]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[11]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[10]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[9]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[8]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[7]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[6]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[5]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[4]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[1]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_i[0]_dat[0]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_o[0]_adr[5]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_o[0]_adr[4]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_o[0]_adr[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_o[0]_adr[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_o[1]_dat[5]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_o[1]_dat[4]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_o[1]_dat[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_o[1]_dat[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_o[1]_dat[1]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_o[1]_dat[0]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[31]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[30]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[29]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[28]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[27]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[26]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[25]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[24]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[23]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[22]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[21]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[20]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[19]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[18]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[17]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[16]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[15]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[14]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[13]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[12]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[11]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[10]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[9]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[8]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[7]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[6]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[5]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[4]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[1]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_o[0]_dat[0]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_o[0]_cyc" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_o[0]_stb" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_o[0]_we" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_o[1]_cyc" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_o[1]_stb" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/master_o[1]_we" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_cyc" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_we" KEEP = "TRUE";
+#NET "inst_image1_core/inst_wb_crossbar/slave_i[0]_stb" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[7]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[6]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[5]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[4]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[1]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[0]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[15]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[14]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[13]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[12]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[11]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[10]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[9]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[8]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[23]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[22]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[21]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[20]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[19]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[18]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[17]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[16]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[31]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[30]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[29]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[28]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[27]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[26]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[25]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_i[24]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_addr_i[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_addr_i[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_addr_i[1]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_addr_i[0]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[31]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[30]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[29]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[28]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[27]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[26]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[25]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[24]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[23]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[22]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[21]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[20]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[19]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[18]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[17]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[16]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[15]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[14]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[13]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[12]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[11]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[10]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[9]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[8]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[7]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[6]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[5]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[4]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[1]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_slave_data_o[0]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_o[5]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_o[4]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_o[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_o[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_o[1]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_data_o[0]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_addr_o[15]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_addr_o[14]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_addr_o[13]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_addr_o[12]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_addr_o[11]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_addr_o[10]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_addr_o[9]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_addr_o[8]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_addr_o[7]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_addr_o[6]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_addr_o[5]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_addr_o[4]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_addr_o[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_regs/wb_master_addr_o[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[31]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[30]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[29]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[28]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[27]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[26]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[25]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[24]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[23]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[22]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[21]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[20]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[19]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[18]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[17]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[16]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[15]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[14]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[13]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[12]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[11]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[10]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[9]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[8]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[7]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[6]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[5]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[4]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[1]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[0]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[31]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[30]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[29]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[28]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[27]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[26]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[25]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[24]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[23]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[22]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[21]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[20]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[19]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[18]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[17]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[16]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[15]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[14]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[13]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[12]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[11]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[10]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[9]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[8]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[7]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[6]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[5]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[4]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[1]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/s_pf_wb_data[0]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/scl_i" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/sda_i" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/sda_o" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm[4]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm[3]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm[2]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm[1]" KEEP = "TRUE";
+#NET "inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/i2c_SLA_fsm[0]" KEEP = "TRUE";
--- a/hdl/IMAGES/image1/project/image1.gise
+++ b/hdl/IMAGES/image1/project/image1.gise
@@ -22,9 +22,303 @@
  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="image1.xise"/>
  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="i2c_slave_core.fdo"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="image1_top.bgn" xil_pn:subbranch="FPGAConfiguration"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="image1_top.bit" xil_pn:subbranch="FPGAConfiguration"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="image1_top.bld"/>
+    <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="image1_top.cmd_log"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="image1_top.drc" xil_pn:subbranch="FPGAConfiguration"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="image1_top.lso"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="image1_top.ncd" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="image1_top.ngc"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="image1_top.ngd"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="image1_top.ngr"/>
+    <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="image1_top.pad"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="image1_top.par" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="image1_top.pcf" xil_pn:subbranch="Map"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="image1_top.prj"/>
+    <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="image1_top.ptwx"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="image1_top.stx"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="image1_top.syr"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="image1_top.twr" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="image1_top.twx" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="image1_top.unroutes" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="image1_top.ut" xil_pn:subbranch="FPGAConfiguration"/>
+    <file xil_pn:fileType="FILE_XPI" xil_pn:name="image1_top.xpi"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="image1_top.xst"/>
    <file xil_pn:fileType="FILE_NCD" xil_pn:name="image1_top_guide.ncd" xil_pn:origination="imported"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="image1_top_map.map" xil_pn:subbranch="Map"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="image1_top_map.mrp" xil_pn:subbranch="Map"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="image1_top_map.ncd" xil_pn:subbranch="Map"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="image1_top_map.ngm" xil_pn:subbranch="Map"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_map.xrpt"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_ngdbuild.xrpt"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="image1_top_pad.csv" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="image1_top_pad.txt" xil_pn:subbranch="Par"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_par.xrpt"/>
+    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="image1_top_summary.xml"/>
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="image1_top_tb.fdo"/>
+    <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="image1_top_usage.xml"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_xst.xrpt"/>
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_LOG" xil_pn:name="vsim.wlf"/>
+    <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
+    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="work"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
  </files>
-  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+  <transforms xmlns="http://www.xilinx.com/XMLSchema">
+    <transform xil_pn:end_ts="1360685369" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1360685369">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1360833881" xil_pn:in_ck="-7743529667590320445" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1360833881">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="InputChanged"/>
+      <status xil_pn:value="OutputChanged"/>
+      <outfile xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"/>
+      <outfile xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"/>
+      <outfile xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"/>
+      <outfile xil_pn:name="../../../basic_trigger/rtl/basic_trigger_core.vhd"/>
+      <outfile xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd"/>
+      <outfile xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl.vhd"/>
+      <outfile xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd"/>
+      <outfile xil_pn:name="../../../ctdah_lib/rtl/FIFO_dispatcher.vhd"/>
+      <outfile xil_pn:name="../../../ctdah_lib/rtl/ctdah_pkg.vhd"/>
+      <outfile xil_pn:name="../../../ctdah_lib/rtl/gc_clk_divider.vhd"/>
+      <outfile xil_pn:name="../../../ctdah_lib/rtl/gc_counter.vhd"/>
+      <outfile xil_pn:name="../../../ctdah_lib/rtl/gc_debouncer.vhd"/>
+      <outfile xil_pn:name="../../../ctdah_lib/rtl/gc_ff.vhd"/>
+      <outfile xil_pn:name="../../../ctdah_lib/rtl/gc_simple_monostable.vhd"/>
+      <outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_bit.vhd"/>
+      <outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_debounce.vhd"/>
+      <outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_regs.vhd"/>
+      <outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_core.vhd"/>
+      <outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd"/>
+      <outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_top.vhd"/>
+      <outfile xil_pn:name="../../../i2c_slave_wb_master/test/i2c_master_driver.vhd"/>
+      <outfile xil_pn:name="../../../i2c_slave_wb_master/test/i2c_tb_pkg.vhd"/>
+      <outfile xil_pn:name="../../../m25p32/rtl/m25p32_core.vhd"/>
+      <outfile xil_pn:name="../../../m25p32/rtl/m25p32_pkg.vhd"/>
+      <outfile xil_pn:name="../../../m25p32/rtl/m25p32_regs.vhd"/>
+      <outfile xil_pn:name="../../../m25p32/rtl/m25p32_top.vhd"/>
+      <outfile xil_pn:name="../../../multiboot/rtl/multiboot_core.vhd"/>
+      <outfile xil_pn:name="../../../multiboot/rtl/multiboot_pkg.vhd"/>
+      <outfile xil_pn:name="../../../multiboot/rtl/multiboot_regs.vhd"/>
+      <outfile xil_pn:name="../../../multiboot/rtl/multiboot_top.vhd"/>
+      <outfile xil_pn:name="../../../rtm_detector/rtl/rtm_detector.vhd"/>
+      <outfile xil_pn:name="../../../rtm_detector/rtl/rtm_detector_pkg.vhd"/>
+      <outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_core.vhd"/>
+      <outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_pkg.vhd"/>
+      <outfile xil_pn:name="../../../test_trigleds_wb/test_trigleds_wb.vhd"/>
+      <outfile xil_pn:name="../rtl/image1_core.vhd"/>
+      <outfile xil_pn:name="../rtl/image1_led_pkg.vhd"/>
+      <outfile xil_pn:name="../rtl/image1_pkg.vhd"/>
+      <outfile xil_pn:name="../rtl/image1_wrappers_pkg.vhd"/>
+      <outfile xil_pn:name="../test/image1_top_tb.vhd"/>
+      <outfile xil_pn:name="../test/image1_top_tb_pkg.vhd"/>
+      <outfile xil_pn:name="../top/image1_top.vhd"/>
+    </transform>
+    <transform xil_pn:end_ts="1360832192" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="239257099518693425" xil_pn:start_ts="1360832192">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1360832192" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-3020523367752079697" xil_pn:start_ts="1360832192">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1360685369" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-4541880911014479478" xil_pn:start_ts="1360685369">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1360833881" xil_pn:in_ck="-7743529667590320445" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1360833881">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="InputChanged"/>
+      <status xil_pn:value="OutputChanged"/>
+      <outfile xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"/>
+      <outfile xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"/>
+      <outfile xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"/>
+      <outfile xil_pn:name="../../../basic_trigger/rtl/basic_trigger_core.vhd"/>
+      <outfile xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd"/>
+      <outfile xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl.vhd"/>
+      <outfile xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd"/>
+      <outfile xil_pn:name="../../../ctdah_lib/rtl/FIFO_dispatcher.vhd"/>
+      <outfile xil_pn:name="../../../ctdah_lib/rtl/ctdah_pkg.vhd"/>
+      <outfile xil_pn:name="../../../ctdah_lib/rtl/gc_clk_divider.vhd"/>
+      <outfile xil_pn:name="../../../ctdah_lib/rtl/gc_counter.vhd"/>
+      <outfile xil_pn:name="../../../ctdah_lib/rtl/gc_debouncer.vhd"/>
+      <outfile xil_pn:name="../../../ctdah_lib/rtl/gc_ff.vhd"/>
+      <outfile xil_pn:name="../../../ctdah_lib/rtl/gc_simple_monostable.vhd"/>
+      <outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_bit.vhd"/>
+      <outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_debounce.vhd"/>
+      <outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_regs.vhd"/>
+      <outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_core.vhd"/>
+      <outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd"/>
+      <outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_top.vhd"/>
+      <outfile xil_pn:name="../../../i2c_slave_wb_master/test/i2c_master_driver.vhd"/>
+      <outfile xil_pn:name="../../../i2c_slave_wb_master/test/i2c_tb_pkg.vhd"/>
+      <outfile xil_pn:name="../../../m25p32/rtl/m25p32_core.vhd"/>
+      <outfile xil_pn:name="../../../m25p32/rtl/m25p32_pkg.vhd"/>
+      <outfile xil_pn:name="../../../m25p32/rtl/m25p32_regs.vhd"/>
+      <outfile xil_pn:name="../../../m25p32/rtl/m25p32_top.vhd"/>
+      <outfile xil_pn:name="../../../multiboot/rtl/multiboot_core.vhd"/>
+      <outfile xil_pn:name="../../../multiboot/rtl/multiboot_pkg.vhd"/>
+      <outfile xil_pn:name="../../../multiboot/rtl/multiboot_regs.vhd"/>
+      <outfile xil_pn:name="../../../multiboot/rtl/multiboot_top.vhd"/>
+      <outfile xil_pn:name="../../../rtm_detector/rtl/rtm_detector.vhd"/>
+      <outfile xil_pn:name="../../../rtm_detector/rtl/rtm_detector_pkg.vhd"/>
+      <outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_core.vhd"/>
+      <outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_pkg.vhd"/>
+      <outfile xil_pn:name="../../../test_trigleds_wb/test_trigleds_wb.vhd"/>
+      <outfile xil_pn:name="../rtl/image1_core.vhd"/>
+      <outfile xil_pn:name="../rtl/image1_led_pkg.vhd"/>
+      <outfile xil_pn:name="../rtl/image1_pkg.vhd"/>
+      <outfile xil_pn:name="../rtl/image1_wrappers_pkg.vhd"/>
+      <outfile xil_pn:name="../test/image1_top_tb.vhd"/>
+      <outfile xil_pn:name="../test/image1_top_tb_pkg.vhd"/>
+      <outfile xil_pn:name="../top/image1_top.vhd"/>
+    </transform>
+    <transform xil_pn:end_ts="1360833882" xil_pn:in_ck="-7743529667590320445" xil_pn:name="TRAN_MSimulateBehavioralModel" xil_pn:prop_ck="6397677621741819996" xil_pn:start_ts="1360833881">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForPredecessor"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="InputChanged"/>
+      <status xil_pn:value="OutputChanged"/>
+      <outfile xil_pn:name="image1_top_tb.fdo"/>
+      <outfile xil_pn:name="vsim.wlf"/>
+      <outfile xil_pn:name="work"/>
+    </transform>
+    <transform xil_pn:end_ts="1360752486" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1360752486">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1360752486" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1112065682908869959" xil_pn:start_ts="1360752486">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1360752486" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4541880911014479478" xil_pn:start_ts="1360752486">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1360752486" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1360752486">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1360752486" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6110598410798097591" xil_pn:start_ts="1360752486">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1360752486" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1360752486">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1360752486" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="8460592660931398612" xil_pn:start_ts="1360752486">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1360839167" xil_pn:in_ck="2481835375757340990" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2283666785813565085" xil_pn:start_ts="1360839148">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="OutputChanged"/>
+      <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
+      <outfile xil_pn:name="image1_top.lso"/>
+      <outfile xil_pn:name="image1_top.ngc"/>
+      <outfile xil_pn:name="image1_top.ngr"/>
+      <outfile xil_pn:name="image1_top.prj"/>
+      <outfile xil_pn:name="image1_top.stx"/>
+      <outfile xil_pn:name="image1_top.syr"/>
+      <outfile xil_pn:name="image1_top.xst"/>
+      <outfile xil_pn:name="image1_top_xst.xrpt"/>
+      <outfile xil_pn:name="webtalk_pn.xml"/>
+      <outfile xil_pn:name="xst"/>
+    </transform>
+    <transform xil_pn:end_ts="1360839167" xil_pn:in_ck="-6700002251458007206" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5283660913978915678" xil_pn:start_ts="1360839167">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1360839174" xil_pn:in_ck="-662876564851204570" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-883419811469213931" xil_pn:start_ts="1360839167">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="_ngo"/>
+      <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
+      <outfile xil_pn:name="image1_top.bld"/>
+      <outfile xil_pn:name="image1_top.ngd"/>
+      <outfile xil_pn:name="image1_top_ngdbuild.xrpt"/>
+    </transform>
+    <transform xil_pn:end_ts="1360839209" xil_pn:in_ck="-662876564851204569" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="4807565132092422995" xil_pn:start_ts="1360839174">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="OutputChanged"/>
+      <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
+      <outfile xil_pn:name="image1_top.pcf"/>
+      <outfile xil_pn:name="image1_top_map.map"/>
+      <outfile xil_pn:name="image1_top_map.mrp"/>
+      <outfile xil_pn:name="image1_top_map.ncd"/>
+      <outfile xil_pn:name="image1_top_map.ngm"/>
+      <outfile xil_pn:name="image1_top_map.xrpt"/>
+      <outfile xil_pn:name="image1_top_summary.xml"/>
+      <outfile xil_pn:name="image1_top_usage.xml"/>
+    </transform>
+    <transform xil_pn:end_ts="1360839243" xil_pn:in_ck="7206782387671427264" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1360839209">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
+      <outfile xil_pn:name="image1_top.ncd"/>
+      <outfile xil_pn:name="image1_top.pad"/>
+      <outfile xil_pn:name="image1_top.par"/>
+      <outfile xil_pn:name="image1_top.ptwx"/>
+      <outfile xil_pn:name="image1_top.unroutes"/>
+      <outfile xil_pn:name="image1_top.xpi"/>
+      <outfile xil_pn:name="image1_top_pad.csv"/>
+      <outfile xil_pn:name="image1_top_pad.txt"/>
+      <outfile xil_pn:name="image1_top_par.xrpt"/>
+    </transform>
+    <transform xil_pn:end_ts="1360839263" xil_pn:in_ck="7803888278084704457" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1360839243">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
+      <outfile xil_pn:name="image1_top.bgn"/>
+      <outfile xil_pn:name="image1_top.bit"/>
+      <outfile xil_pn:name="image1_top.drc"/>
+      <outfile xil_pn:name="image1_top.ut"/>
+      <outfile xil_pn:name="webtalk.log"/>
+      <outfile xil_pn:name="webtalk_pn.xml"/>
+    </transform>
+    <transform xil_pn:end_ts="1360833662" xil_pn:in_ck="7803888278084691603" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1360833660">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="InputChanged"/>
+    </transform>
+    <transform xil_pn:end_ts="1360839243" xil_pn:in_ck="-662876564851204701" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1360839235">
+      <status xil_pn:value="FailedRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
+      <outfile xil_pn:name="image1_top.twr"/>
+      <outfile xil_pn:name="image1_top.twx"/>
+    </transform>
+  </transforms>
 </generated_project>
--- a/hdl/IMAGES/image1/project/image1.xise
+++ b/hdl/IMAGES/image1/project/image1.xise
@@ -445,8 +445,8 @@
    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/image1_top_tb/uut/inst_image1_core/inst_i2c_slave/inst_i2c_slave_core" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/image1_top_tb/uut/inst_image1_core/inst_i2c_slave/inst_i2c_regs" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.i2c_slave_core" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.i2c_regs" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -469,7 +469,7 @@
    <property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.i2c_slave_core" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.i2c_regs" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>

--- a/hdl/IMAGES/image1/rtl/image1_core.vhd
+++ b/hdl/IMAGES/image1/rtl/image1_core.vhd
@@ -265,7 +265,7 @@ begin
  -- !!!!!
-  led_front_n <= leds_from_trig or (not trigleds);
+  led_front_n <= not trigleds;
@@ -334,7 +334,7 @@ begin
            scl_oen           => i2c_slave_o.SCL_OE,
            scl_i             => i2c_slave_i.SCL_I,
            scl_o             => i2c_slave_o.SCL_O,
-            wb_clk            => s_clk.SYS_A,
+            wb_clk_i          => s_clk.SYS_A,
            wb_rst_i          => s_rst.SYS_A(c_RST_A_CLKS - 1),
            wb_master_stb_o   => s_slave_i(c_MASTER_I2C_SLAVE).stb,
            wb_master_cyc_o   => s_slave_i(c_MASTER_I2C_SLAVE).cyc,

--- a/hdl/IMAGES/image1/rtl/image1_pkg.vhd
+++ b/hdl/IMAGES/image1/rtl/image1_pkg.vhd
@@ -170,7 +170,7 @@ package image1_pkg is
        scl_i            : in  STD_LOGIC;
        scl_o            : out STD_LOGIC;
-        wb_clk           : in  STD_LOGIC;
+        wb_clk_i         : in  STD_LOGIC;
        wb_rst_i         : in  STD_LOGIC;
        wb_master_stb_o  : out STD_LOGIC;
@@ -205,7 +205,7 @@ package image1_pkg is
   component m25p32_top
   generic(g_WB_ADDR_LENGTH : NATURAL := c_WORDS_PER_PAGE_BITS + 1);
   port(wb_rst_i       : in  STD_LOGIC;
-        wb_clk         : in  STD_LOGIC;
+        wb_clk_i       : in  STD_LOGIC;
        wb_we_i        : in  STD_LOGIC;
        wb_stb_i       : in  STD_LOGIC;
@@ -237,7 +237,7 @@ package image1_pkg is
           --! Set it up accordingly.
           g_READ_SPI_OPCODE : STD_LOGIC_VECTOR(7 downto 0) := X"03");
   port(wb_rst_i   : in   STD_LOGIC;
-        wb_clk     : in   STD_LOGIC;
+        wb_clk_i   : in   STD_LOGIC;
        wb_we_i    : in   STD_LOGIC;
        wb_stb_i   : in   STD_LOGIC;
        wb_cyc_i   : in   STD_LOGIC;

--- a/hdl/IMAGES/image1/test/image1_top_tb.vhd
+++ b/hdl/IMAGES/image1/test/image1_top_tb.vhd
@@ -20,7 +20,7 @@ end image1_top_tb;
 architecture behavior of image1_top_tb is
-  type t_tb_state is (ST_INIT, ST_READ_CTR0, ST_WRITE_LED);
+  type t_tb_state is (ST_INIT, ST_READ_CTR0, ST_WRITE_LED, ST_READ_LED);
   constant c_CLK20M        : TIME := 50 ns;
@@ -324,17 +324,24 @@ begin
                                               severity Error;
      wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
-      tb_state <= ST_WRITE_LED;
+--      tb_state <= ST_WRITE_LED;
+--      
+--      start_i2c;
+--      assert false report "-------writing" severity note;
+--      write_i2c(s_fpga_ga, x"0080", x"00000055");
+--      assert false report "-------done!" severity note;
+--      
+--      wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
+      tb_state <= ST_READ_LED;
      start_i2c;
-      assert false report "-------writing" severity note;
+      assert false report "-------reading" severity note;
-      write_i2c(s_fpga_ga, x"0080", x"00000055");
+      read_i2c(s_fpga_ga, x"0080");
      assert false report "-------done!" severity note;
      wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
--
 --      start_I2C;
 --      read_I2C(UNSIGNED(s_FPGA_GA), c_I2C_DTX_addr);
 --          assert False report "Reading I2C DTX" severity Warning;

--- a/hdl/IMAGES/image1/test/log/i2c_master_driver.txt
+++ b/hdl/IMAGES/image1/test/log/i2c_master_driver.txt
@@ -2,10 +2,7 @@
 1	  OK	 READ	   WISHBONE HIGH
 1	  OK	 READ	    WISHBONE LOW
 1	  OK	 READ	     [ADDRESS|0]
-2	  OK	WRITE	     [ADDRESS|0]
+2	  OK	 READ	     [ADDRESS|0]
-2	  OK	WRITE	   WISHBONE HIGH
+2	  OK	 READ	   WISHBONE HIGH
-2	  OK	WRITE	    WISHBONE LOW
+2	  OK	 READ	    WISHBONE LOW
-2	  OK	WRITE	     READ DATA 0
+2	  OK	 READ	     [ADDRESS|0]
-2	  OK	WRITE	     READ DATA 1
-2	  OK	WRITE	     READ DATA 2
-2	  OK	WRITE	     READ DATA 3
--- a/hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd
+++ b/hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd
@@ -29,7 +29,7 @@ use IEEE.NUMERIC_STD.ALL;
 use work.i2c_slave_pkg.ALL;
 entity i2c_regs is
-   port (wb_clk           : in   STD_LOGIC;
+   port (wb_clk_i           : in   STD_LOGIC;
         wb_rst_i         : in   STD_LOGIC;
         wb_master_we_o   : out STD_LOGIC;
@@ -117,10 +117,10 @@ begin
   pf_wb_data_o    <= s_DTX;
   --! @brief          Process that controls the retries of the wishbone interface
-   --! @param wb_clk   Main clock
+   --! @param wb_clk_i   Main clock
-   p_wb_master_retries: process (wb_clk)
+   p_wb_master_retries: process (wb_clk_i)
   begin
-      if rising_edge(wb_clk) then
+      if rising_edge(wb_clk_i) then
         if i2c_master_WB_BASIC_fsm = S3_WB_ACK then
            s_wb_master_ack_retries(0) <= '1';
            for i in 1 to c_RETRY_LENGTH - 1 loop
@@ -139,63 +139,86 @@ begin
   --!                                 read/written when repetitions of the
   --!                                 wishbone master interface happen.
   --! @param i2c_master_WB_BASIC_fsm  fsm of the wishone master interface
-   wbmaster_comb_proc: process(i2c_master_WB_BASIC_fsm)
+   wbmaster_comb_proc : process(wb_clk_i)
+--     function f_le2be(val : std_logic_vector(31 downto 0))
+--     return std_logic_vector(31 downto 0) is
+--       variable retval;
+--     begin
+--       retval( 7 downto  0) <= val(31 downto 24);
+--       retval(15 downto  8) <= val(23 downto 16);
+--       retval(23 downto 16) <= val(15 downto  8);
+--       retval(31 downto 24) <= val(7 downto 0);
+--
+--       return retval;
+--     end function;
   begin
-      s_wb_master_we_o  <= '0';
+     if rising_edge(wb_clk_i) then
-      wb_master_stb_o   <= '0';
+       if (wb_rst_i = '1') then
-      wb_master_cyc_o   <= '0';
+         s_wb_master_we_o  <= '0';
-      wb_master_sel_o   <= (others => '0');
+         wb_master_stb_o   <= '0';
-      wb_master_data_o  <= (others => '0');
+         wb_master_cyc_o   <= '0';
-      wb_master_addr_o  <= (others => '0');
+         wb_master_sel_o   <= (others => '0');
-      case i2c_master_WB_BASIC_fsm is
+         wb_master_data_o  <= (others => '0');
-         when R0_RESET       =>
+         wb_master_addr_o  <= (others => '0');
-            null;
+         s_dtx             <= (others => '0');
-         when S0_IDLE        =>
+       else
-            null;
+         case i2c_master_WB_BASIC_fsm is
-         when S1P_WB_RD_RQT  =>
+           when R0_RESET =>
-            s_wb_addr_rd(15 downto 0)  <= DRXA_i(23 downto 8);
+             null;
-         when S1_WB_RD_RQT   =>
+           when S0_IDLE =>
-            wb_master_cyc_o       <= '1';
+             null;
-            wb_master_stb_o       <= '1';
+           when S1P_WB_RD_RQT =>
-            wb_master_sel_o       <= X"F";
+             s_wb_addr_rd     <= DRXA_i(23 downto 8);
-            wb_master_addr_o      <= s_wb_addr_rd;
+           when S1_WB_RD_RQT =>
-         when S1N_WB_NOOP   =>
+             wb_master_cyc_o  <= '1';
-            wb_master_cyc_o       <= '1';
+             wb_master_stb_o  <= '1';
-            wb_master_stb_o       <= '1';
+             wb_master_sel_o  <= X"F";
-            wb_master_sel_o       <= X"F";
+             wb_master_addr_o <= s_wb_addr_rd;
-            wb_master_addr_o      <= s_wb_addr_rd;
+           when S1N_WB_NOOP =>
-         when S1_PF_WB_DATA_OUT =>
+             wb_master_cyc_o  <= '1';
-            s_DTX                 <= wb_master_data_i;
+             wb_master_stb_o  <= '1';
-         when S2P_WB_WR_RQT  =>
+             wb_master_sel_o  <= X"F";
-            null;
+             wb_master_addr_o <= s_wb_addr_rd;
-         when S2_WB_WR_RQT   =>
+           when S1_PF_WB_DATA_OUT =>
-            wb_master_cyc_o       <= '1';
+             s_DTX            <= wb_master_data_i;
-            wb_master_stb_o       <= '1';
+           when S2P_WB_WR_RQT =>
-            s_wb_master_we_o      <= '1';
+             null;
-            wb_master_sel_o       <= X"F";
+           when S2_WB_WR_RQT   =>
-            wb_master_data_o      <= DRXA_i;
+             wb_master_cyc_o  <= '1';
-            wb_master_addr_o(15 downto  0)  <= DRXB_i(15 downto 0);
+             wb_master_stb_o  <= '1';
-         when S2N_WB_NOOP     =>
+             s_wb_master_we_o <= '1';
-            wb_master_cyc_o       <= '1';
+             wb_master_sel_o  <= X"F";
-            wb_master_stb_o       <= '1';
+             wb_master_data_o <= f_ch_endian(DRXA_i);
-            s_wb_master_we_o      <= '1';
+             wb_master_addr_o <= DRXB_i(15 downto 0);
-            wb_master_sel_o       <= X"F";
+           when S2N_WB_NOOP =>
-            wb_master_data_o      <= DRXA_i;
+             wb_master_cyc_o  <= '1';
-            wb_master_addr_o(15 downto  0)  <= DRXB_i(15 downto 0);
+             wb_master_stb_o  <= '1';
-         when S3_WB_ACK      =>
+             s_wb_master_we_o <= '1';
-            null;
+             wb_master_sel_o  <= X"F";
-         when others         =>
+             wb_master_data_o <= f_ch_endian(DRXA_i);
-            null;
+             wb_master_addr_o <= DRXB_i(15 downto 0);
-      end case;
+           when S3_WB_ACK =>
+             -- null;
+             wb_master_cyc_o  <= '0';
+             wb_master_stb_o  <= '0';
+             s_wb_master_we_o <= '0';
+           when others =>
+             null;
+         end case;
+       end if;
+     end if;
   end process;
   --! @brief          Process to rule slave wishbone outputs
-   --! @param wb_clk   Main clock
+   --! @param wb_clk_i   Main clock
-   p_wb_slave: process (wb_clk)
+   p_wb_slave: process (wb_clk_i)
   begin
-      if rising_edge(wb_clk) then
+      if rising_edge(wb_clk_i) then
         if i2c_master_WB_BASIC_fsm = R0_RESET then
            s_CTR0           <= c_CTR0_default;
            s_CTR0.I2C_ADDR  <= UNSIGNED(i2c_addr_i);
@@ -233,7 +256,7 @@ begin
                            wb_slave_data_o <= DRXA_i;
                         when c_DRXB_addr     =>
                            wb_slave_data_o <= DRXB_i;
-                         when others        =>
+                         when others          =>
                            s_wb_slave_ack           <= '0';
                            s_wb_slave_err           <= '1';
                      end case;
@@ -246,10 +269,10 @@ begin
   --! @brief This is the process that controls the wishbone master interface
   --!        which bridges the i2c interface with the wishbone interface.
-   --! @param wb_clk Main clock
+   --! @param wb_clk_i Main clock
-   p_master_fsm: process(wb_clk)
+   p_master_fsm: process(wb_clk_i)
   begin
-      if rising_edge(wb_clk) then
+      if rising_edge(wb_clk_i) then
         if wb_rst_i = '1' then
            --! Here is the part in which we propagate the reset, let one-clock
            --! for it.

--- a/hdl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd
+++ b/hdl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd
@@ -60,7 +60,7 @@ use work.ctdah_pkg.ALL;
 entity i2c_slave_core is
   generic(g_WB_CLK_PERIOD : TIME := 50 ns);
   port (
-      clk           : in  STD_LOGIC;
+      clk_i         : in  STD_LOGIC;
      rst_i         : in  STD_LOGIC;
      -- I2C pins
      sda_oen       : out  STD_LOGIC;
@@ -170,15 +170,22 @@ signal s_watchdog_cnt_rst : STD_LOGIC;
 signal s_watchdog_cnt_slv : STD_LOGIC_VECTOR(c_WATCHDOG_WIDTH - 1 downto 0);
 signal s_watchdog_cnt     : NATURAL;
+attribute keep : string;
+signal s_dummy : std_logic_vector(0 to 31);
+attribute keep of s_dummy : signal is "true";
 begin
+   s_dummy(0 to 31) <= f_ch_endian(s_pf_wb_data(31 downto 0));
   s_CTR0       <= f_CTR0(CTR0_i);
   LT_o         <= f_STD_LOGIC_VECTOR(s_LT);
   s_pf_wb_data <= pf_wb_data_i;
   inst_i2c_bit  : i2c_bit
   port map(rst_i     => rst_i,
-            wb_clk_i  => clk,
+            wb_clk_i  => clk_i,
            sda_i     => sda_i,
            scl_i     => scl_i,
            start_o   => s_start_o,
@@ -189,7 +196,7 @@ begin
   bit_counter_8: gc_counter
   generic map (g_data_width => c_DATA_WIDTH)
-   port map (clk_i  => clk,
+   port map (clk_i  => clk_i,
             rst_i  => s_bit_cnt_rst,
             en_i   => s_bit_done,
             cnt_o  => s_bit_cnt_slv);
@@ -198,7 +205,7 @@ begin
   byte_counter_8: gc_counter
   generic map (g_data_width => c_DATA_WIDTH)
-   port map (clk_i  => clk,
+   port map (clk_i  => clk_i,
             rst_i  => s_byte_cnt_rst,
             en_i   => s_byte_cnt_en,
             cnt_o  => s_byte_cnt_slv);
@@ -207,7 +214,7 @@ begin
   watchdog_counter_8: gc_counter
   generic map (g_data_width => c_WATCHDOG_WIDTH)
-   port map (clk_i  => clk,
+   port map (clk_i  => clk_i,
             rst_i  => s_watchdog_cnt_rst,
             en_i   => c_WATCHDOG_ENABLE,
             cnt_o  => s_watchdog_cnt_slv);
@@ -227,6 +234,8 @@ begin
 --      variable v_bit_order   : NATURAL;
        variable v_bit_un      : UNSIGNED(2 downto 0);
      variable v_pf_wb_data    : STD_LOGIC_VECTOR(0 to 31);
+--     variable v_pf_wb_data : std_logic_vector(31 downto 0);
   begin
         case i2c_SLA_fsm is
            when S2A_I2C_ADDR_ACK      =>
@@ -241,9 +250,13 @@ begin
 --               v_bit_inv   := UNSIGNED(not(s_bit_cnt_slv(2 downto 0)));
 --               v_bit_order := to_integer(v_bit_inv);
 --               s_sda_o <= s_pf_wb_data(s_byte_cnt*8 + v_bit_order);
-               v_pf_wb_data(0 to 31) := s_pf_wb_data(31 downto 0);
-               s_sda_o <= v_pf_wb_data(s_byte_cnt*8 + (s_bit_cnt mod 8));
-            when others           =>
+               v_pf_wb_data(0 to 31) := s_pf_wb_data(31 downto 0); -- f_ch_endian(s_pf_wb_data(31 downto 0));
+               -- v_pf_wb_data := s_pf_wb_data; -- f_ch_endian(s_pf_wb_data);
+               s_sda_o      <= v_pf_wb_data(s_byte_cnt*8 + (s_bit_cnt mod 8));
+            when others =>
               s_sda_o <= '1';
         end case;
   end process;
@@ -273,8 +286,8 @@ begin
   s_DRXB_slv <= s_DRX_slv(r_DRX'a_length*2 - 1 downto r_DRX'a_length);
   --! @brief      Process to store the incoming data
-   --! @param clk  Clock that samples the data
+   --! @param clk_i  Clock that samples the data
-   p_store_FIFO: process(clk)
+   p_store_FIFO: process(clk_i)
      procedure shift_DRX is
      begin
@@ -285,7 +298,7 @@ begin
      end procedure;
   begin
-      if rising_edge(clk) then
+      if rising_edge(clk_i) then
         if s_bit_done = '1' then
            case i2c_SLA_fsm is
               when S2_I2C_ADDR      =>
@@ -317,19 +330,19 @@ begin
   end generate gen_i2c;
-   p_delays : process(clk)
+   p_delays : process(clk_i)
   begin
-      if rising_edge(clk) then
+      if rising_edge(clk_i) then
         i2c_SLA_fsm_d0   <= i2c_SLA_fsm;
      end if;
   end process;
   --! @brief     Process to generate the pf_wb_addr_o signal.
-   --! @param clk Main clock
+   --! @param clk_i Main clock
-   p_pf_wb_addr: process(clk)
+   p_pf_wb_addr: process(clk_i)
   begin
-      if rising_edge(clk) then
+      if rising_edge(clk_i) then
         pf_wb_addr_o <= '0';
         if     i2c_SLA_fsm    = S5W1A_I2C_ADDR_ACK
            and i2c_SLA_fsm_d0 = S5W1_I2C_ADDR      then
@@ -339,10 +352,10 @@ begin
   end process;
   --! @brief     Process to generate the rd_done_o signal.
-   --! @param clk Main clock
+   --! @param clk_i Main clock
-   p_rd_done: process(clk)
+   p_rd_done: process(clk_i)
   begin
-      if rising_edge(clk) then
+      if rising_edge(clk_i) then
         rd_done_o <= '0';
         if     i2c_SLA_fsm = S6_WAIT_START_PAUSE
            and i2c_SLA_fsm_d0 = S5RA_READ_SDA_ACK     then
@@ -352,10 +365,10 @@ begin
   end process;
   --! @brief     Process to generate the wr_done_o signal.
-   --! @param clk Main clock
+   --! @param clk_i Main clock
-   p_wr_done: process(clk)
+   p_wr_done: process(clk_i)
   begin
-      if rising_edge(clk) then
+      if rising_edge(clk_i) then
         wr_done_o <= '0';
         if     i2c_SLA_fsm    = S6_WAIT_START_PAUSE
            and i2c_SLA_fsm_d0 = S5W3_NACK           then
@@ -364,8 +377,8 @@ begin
      end if;
   end process;
-   DRXA_o    <= s_DRXA_slv;
+   DRXA_o <= s_DRXA_slv;
-   DRXB_o    <= s_DRXB_slv;
+   DRXB_o <= s_DRXB_slv;
   --! @brief process to update the signals that drive bit_counter_8
   --! @param i2c_SLA_fsm    Current value of the i2c fsm
@@ -483,10 +496,10 @@ begin
   end process;
   --! @brief       Watchdog reset process
-   --! @param clk   Main clock
+   --! @param clk_i   Main clock
-   p_watchdog_rst: process(clk)
+   p_watchdog_rst: process(clk_i)
   begin
-      if rising_edge(clk) then
+      if rising_edge(clk_i) then
         s_watchdog_cnt_rst <= '0';
         if rst_i = '1' then
            s_watchdog_cnt_rst <= '1';
@@ -503,11 +516,11 @@ begin
   --! @brief      Small process that records the length of a
   --!             bit over the I2C interface.
-   --! @param clk  Main clock
+   --! @param clk_i  Main clock
-   p_LT_SCLP: process(clk)
+   p_LT_SCLP: process(clk_i)
      variable v_count  : STD_LOGIC_VECTOR(23 downto 0);
   begin
-      if rising_edge(clk) then
+      if rising_edge(clk_i) then
         if i2c_SLA_fsm = R0_RESET then
            s_LT.SCLP <= c_LT_default.SCLP;
         else
@@ -523,8 +536,8 @@ begin
   end process;
   --! @brief      Process to set the next fsm
-   --! @param clk  Clock that rules the fsm transitions
+   --! @param clk_i  Clock that rules the fsm transitions
-   fsm_proc: process(clk)
+   fsm_proc: process(clk_i)
      procedure check_start_stop is
      begin
@@ -536,7 +549,7 @@ begin
      end procedure;
   begin
-      if rising_edge(clk) then
+      if rising_edge(clk_i) then
         if    rst_i = '1'
            or s_watchdog_cnt >= c_WATCHDOG_END_VALUE  then
            i2c_SLA_fsm <= R0_RESET;

--- a/hdl/i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd
+++ b/hdl/i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd
@@ -2,6 +2,7 @@
 --
 -- Company:        CERN, BE-CO-HT
 -- Engineer:       Carlos Gil Soriano
+--                 Theodor-Adrian Stana
 --
 -- Create Date:    11:03:11 06/19/2012
 -- Design Name:
@@ -159,7 +160,7 @@ package i2c_slave_pkg is
   component i2c_slave_core
   generic(g_WB_CLK_PERIOD : TIME := 50 ns);
   port (
-      clk          : in   STD_LOGIC;
+      clk_i        : in   STD_LOGIC;
      rst_i        : in   STD_LOGIC;
      sda_oen      : out  STD_LOGIC;
@@ -181,7 +182,7 @@ package i2c_slave_pkg is
   end component;
   component i2c_regs
-      port (wb_clk           : in  STD_LOGIC;
+      port (wb_clk_i         : in  STD_LOGIC;
            wb_rst_i         : in  STD_LOGIC;
            wb_master_we_o   : out STD_LOGIC;
@@ -243,6 +244,7 @@ package i2c_slave_pkg is
   function f_LT    (signal r_register : in STD_LOGIC_VECTOR(31 downto 0))
                                                                 return r_LT;
+   function f_ch_endian(val : std_logic_vector) return std_logic_vector;
   function f_STD_LOGIC_VECTOR(r_register : in r_CTR0) return STD_LOGIC_VECTOR;
   function f_STD_LOGIC_VECTOR(r_register : in r_LT)   return STD_LOGIC_VECTOR;
@@ -296,4 +298,15 @@ package body i2c_slave_pkg is
   end function;
+   function f_ch_endian(val : std_logic_vector)
+   return std_logic_vector is
+     variable retval : std_logic_vector(31 downto 0);
+   begin
+     retval( 7 downto  0) := val(31 downto 24);
+     retval(15 downto  8) := val(23 downto 16);
+     retval(23 downto 16) := val(15 downto  8);
+     retval(31 downto 24) := val( 7 downto  0);
+     return retval;
+   end function;
 end i2c_slave_pkg;
--- a/hdl/i2c_slave_wb_master/rtl/i2c_slave_top.vhd
+++ b/hdl/i2c_slave_wb_master/rtl/i2c_slave_top.vhd
@@ -36,7 +36,7 @@ entity i2c_slave_top is
      scl_i            : in  STD_LOGIC;
      scl_o            : out STD_LOGIC;
-      wb_clk           : in  STD_LOGIC;
+      wb_clk_i         : in  STD_LOGIC;
      wb_rst_i         : in  STD_LOGIC;
      wb_master_stb_o  : out STD_LOGIC;
@@ -95,7 +95,7 @@ begin
   s_CTR0         <= f_CTR0(s_CTR0_slv);
   inst_i2c_slave_core: i2c_slave_core
-   port map(clk          => wb_clk,
+   port map(clk_i        => wb_clk_i,
            rst_i        => wb_rst_i,
            sda_oen      => sda_oen,
@@ -122,7 +122,7 @@ begin
            wr_done_i    => s_wr_done,
            wb_rst_i     => wb_rst_i,
-            wb_clk       => wb_clk,
+            wb_clk_i     => wb_clk_i,
            wb_master_we_o   => wb_master_we_o,
            wb_master_stb_o  => wb_master_stb_o,
@@ -156,9 +156,9 @@ begin
   s_rst_i2c <= s_reset_extensor(2**c_RST_EXTENSOR - 1);
   --! A shift with reset, consumes just a few SLICEX in Spartan6.
-   p_rst_extender : process(wb_clk)
+   p_rst_extender : process(wb_clk_i)
   begin
-      if rising_edge(wb_clk) then
+      if rising_edge(wb_clk_i) then
         if wb_rst_i = '1' then
            s_reset_extensor <= (others => '1');
         else