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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
Commits
8c3522c1
Commit
8c3522c1
authored
Jan 07, 2014
by
Theodor-Adrian Stana
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regtest: updated project to generate bin file
Signed-off-by:
Theodor Stana
<
t.stana@cern.ch
>
parent
4e30de88
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regtest.xise
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syn/regtest/regtest.xise
View file @
8c3522c1
...
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@@ -56,7 +56,7 @@
<property
xil_pn:name=
"Configuration Rate spartan6"
xil_pn:value=
"2"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Correlate Output to Input Design"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create ASCII Configuration File"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create Binary Configuration File"
xil_pn:value=
"
false"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Create Binary Configuration File"
xil_pn:value=
"
true"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Create Bit File"
xil_pn:value=
"true"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create I/O Pads from Ports"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Create IEEE 1532 Configuration File spartan6"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
...
...
@@ -175,7 +175,7 @@
<property
xil_pn:name=
"Optimization Effort spartan6"
xil_pn:value=
"Normal"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Optimization Goal"
xil_pn:value=
"Speed"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Optimize Instantiated Primitives"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Bitgen Command Line Options spartan6"
xil_pn:value=
"
-g next_config_register_write:Disable"
xil_pn:valueState=
"non-
default"
/>
<property
xil_pn:name=
"Other Bitgen Command Line Options spartan6"
xil_pn:value=
"
"
xil_pn:valueState=
"
default"
/>
<property
xil_pn:name=
"Other Compiler Options"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Compiler Options Map"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Other Compiler Options Par"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
...
...
@@ -313,7 +313,7 @@
<property
xil_pn:name=
"Verilog Macros"
xil_pn:value=
""
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Wait for DCM and PLL Lock (Output Events) spartan6"
xil_pn:value=
"Default (NoWait)"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Wakeup Clock spartan6"
xil_pn:value=
"Startup Clock"
xil_pn:valueState=
"default"
/>
<property
xil_pn:name=
"Watchdog Timer Value spartan6"
xil_pn:value=
"0x1f
FF
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Watchdog Timer Value spartan6"
xil_pn:value=
"0x1f
ff
"
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Working Directory"
xil_pn:value=
"."
xil_pn:valueState=
"non-default"
/>
<property
xil_pn:name=
"Write Timing Constraints"
xil_pn:value=
"false"
xil_pn:valueState=
"default"
/>
<!-- -->
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