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Conv TTL Blocking - Gateware
Commit 8aaf2d8f authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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second draft of hdlguide and hwguide, additional info in userguide

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doc/hdlguide/hdlguide-conv-ttl-blo.bib
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......@@ -35,6 +35,14 @@
howpublished = {\url{http://www.ohwr.org/documents/263}}
}
@misc{ctb-hwguide,
author = "Theodor-Adrian Stana",
title = {{CONV-TTL-BLO Hardware Guide}},
month = 07,
year = 2013,
howpublished = {\url{http://www.ohwr.org/documents/282}}
}
@misc{sysmon-i2c,
author = "{ELMA}",
title = {{Access to board data using SNMP and I2C}},
......
doc/hdlguide/hdlguide-conv-ttl-blo.tex
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......@@ -41,6 +41,7 @@
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
04-07-2013 & 0.1 & First draft \\
26-07-2013 & 0.2 & Second draft \\
\hline
\end{tabular}
}
......@@ -103,10 +104,11 @@ blocks in the figure is presented in following sections.
%------------------------------------------------------------------------------
\subsection*{Additional documentation}
\textcolor{red}{\textbf{!!!}}
%\textcolor{red}{\textbf{!!!}}
\begin{itemize}
\item CONV-TTL-BLO User Guide \cite{ctb-ug}
\item CONV-TTL-BLO Hardware Guide \cite{ctb-hwguide}
\end{itemize}
%==============================================================================
......@@ -374,7 +376,7 @@ multiplexers are set throughout the logic.
\textbf{Ports} & \textit{clk\_i} & Clock signal \\
& \textit{rst\_n\_i} & Active-low reset signal \\
& \textit{en\_i} & Pulse generator enable \\
& \textcolor{red}{\textit{glitch\_filt\_en\_n}} & \textcolor{red}{Active-low glitch filter enable} \\
& \textit{glitch\_filt\_en\_n} & Active-low glitch filter enable \\
& \textit{trig\_i} & Pulse trigger \\
& \textit{pulse\_o} & Pulse output \\
\textbf{Usage} & Output pulse & 1.2~${\mu}s$ pulses \\
......@@ -504,12 +506,12 @@ The complete memory map of the firmware can be found in Appendix~\ref{app:memmap
\subsection{I$^2$C to Wishbone bridge}
\label{sec:elma-i2c}
The \textit{elma\_i2c} module \textcolor{red}{\textbf{REFERENCE}} implements a bridge between the serial lines on the
The \textit{elma\_i2c} module implements a bridge between the serial lines on the
VME P1 connector using the ELMA I$^2$C-based protocol~\cite{sysmon-i2c}, and the
Wishbone interconnect. The module provides one I$^2$C slave interface for connecting
to an ELMA SysMon and one Wishbone master interface.
Details about the module's implementation can be found in its documentation \textcolor{red}{\textbf{REFERENCE}}.
Details about the module's implementation can be found in its documentation.
%------------------------------------------------------------------------------
% SUBSEC: CSR
......@@ -606,7 +608,7 @@ part of the CONV-TTL-BLO project are present in their own folders as sub-nodes o
\textit{conv-ttl-blo/hdl/} folder. In general, the module files are present under an
\textit{rtl/} sub-folder; documentation files (if any) for the modules appear under a
\textit{doc/} sub-folder. The I$^2$C bridge module folder also contains the instantiated
\textit{i2c\_slave.vhd} file (see \textcolor{red}{\textbf{REFERENCE TO ELMA\_I2C}}) and the documentation for it.
\textit{i2c\_slave} module and its documentation.
The \textit{release/} folder is the main folder in the firmware package, as can be seen from the
fact that it is bolded in the folder structure above. It contains top-level files in the
......@@ -629,7 +631,7 @@ VHDL, or net names that have been made clearer in VHDL code. Input ports are ass
signals and signals are assigned to output ports in each code section.
\begin{figure}[h]
\centerline{\includegraphics[scale=.8]{fig/declarative}}
\centerline{\includegraphics[scale=1]{fig/declarative}}
\caption{Declarative part of VHDL architecture}
\label{fig:declarative}
\end{figure}
......@@ -640,7 +642,7 @@ stant declarations, followed by component declarations, after which the var-
ious signals are declared.
\begin{figure}[h]
\centerline{\includegraphics[scale=.6]{fig/body}}
\centerline{\includegraphics[scale=1]{fig/body}}
\caption{Body of VHDL architecture}
\label{fig:body}
\end{figure}
......@@ -649,8 +651,10 @@ The body of the architecture is organised as shown in in Figure~\ref{fig:body}.
by instantiating a differential buffer for the 125~MHz system clock and instantiating the
\textit{reset\_gen} component. Then, the \textit{elma\_i2c} bridge module is instantiated
along with the Wishbone crossbar that offers access to the rest of the Wishbone modules in
the design. Next, the CONV board CSR module is instantiated, followed by logic necessary
for each of the tests comprising PTS.
the design. Next, the CONV board CSR module is instantiated, followed by the instantiation
of twelve pulse generator modules, six for pulse repetition and six for the pulse LEDs.
This is followed by the logic for the status LEDs and the file ends with the RTM detection
modules.
%==============================================================================
......
doc/hwguide/hwguide-conv-ttl-blo.bib
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......@@ -7,6 +7,14 @@
howpublished = {\url{http://www.ohwr.org/documents/263}}
}
@misc{ctb-hdlguide,
author = "Theodor-Adrian Stana",
title = {{CONV-TTL-BLO HDL Guide}},
month = 07,
year = 2013,
howpublished = {\url{http://www.ohwr.org/documents/283}}
}
@misc{sysmon-i2c,
author = "{ELMA}",
title = {{Access to board data using SNMP and I2C}},
......@@ -67,3 +75,12 @@
title = {{High CMR, High Speed TTL Compatible Optocouplers}},
note = {\url{http://www.avagotech.com/docs/AV02-0940EN}}
}
@misc{nxp-an11158,
author = {{NXP Semiconductor}},
title = {{Understanding power MOSFET datasheet parameters}},
day = 7,
month = January,
year = 2013,
note = {\url{http://www.nxp.com/documents/application_note/AN11158.pdf}}
}
doc/hwguide/hwguide-conv-ttl-blo.tex
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......@@ -5,6 +5,7 @@
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage{multirow}
\usepackage{amsmath}
\usepackage{color}
......@@ -40,7 +41,8 @@
\hline
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
date & 0.1 & First draft \\
04-07-2013 & 0.1 & First draft \\
26-07-2013 & 0.2 & Second draft \\
\hline
\end{tabular}
}
......@@ -101,17 +103,17 @@ time-tagging via White Rabbit \cite{white-rabbit}.
An RTM system usually consists of both motherboard and piggyback and provide the
connections to input blocking pulses to the CONV-TTL-BLO.
\textcolor{red}{\textbf{board pics}}
%------------------------------------------------------------------------------
% SUBSEC: Additional doc
%------------------------------------------------------------------------------
\pagebreak
\subsection*{Additional documentation}
\textcolor{red}{\textbf{!!!}}
%\textcolor{red}{\textbf{!!!}}
\begin{itemize}
\item CONV-TTL-BLO User Guide \cite{ctb-ug}
\item CONV-TTL-BLO HDL Guide \cite{ctb-hdlguide}
\end{itemize}
%==============================================================================
......@@ -120,14 +122,14 @@ connections to input blocking pulses to the CONV-TTL-BLO.
\section{Front module}
\label{sec:ctb}
A block diagram of the CONV-TTL-BLO board is shown in Figure~\ref{fig:conv-ttl-blo-bd}.
The board contains all active circuitry needed within a converter system. The various
blocks in Figure~\ref{fig:conv-ttl-blo-bd} are presented in subsections that follow.
A block diagram of the CONV-TTL-BLO front module is shown in Figure~\ref{fig:conv-ttl-blo-bd}.
The board contains all active circuitry needed within a converter system. The various blocks in
Figure~\ref{fig:conv-ttl-blo-bd} are presented in subsections that follow.
The schematics of the CONV-TTL-BLO board can be found at \cite{conv-ttl-blo-sch}.
\begin{figure}[h]
\centerline{\includegraphics[width=.75\textwidth]{fig/conv-ttl-blo-bd}}
\centerline{\includegraphics[width=.65\textwidth]{fig/conv-ttl-blo-bd}}
\caption{Block diagram of CONV-TTL-BLO board}
\label{fig:conv-ttl-blo-bd}
\end{figure}
......@@ -299,7 +301,7 @@ The intended functionality of the FPGA is:
\end{itemize}
For more details on the FPGA firmware and functionality, refer to the CONV-TTL-BLO
HDL Guide \textcolor{red}{\textbf{REFER}}.
HDL Guide~\cite{ctb-hdlguide}.
%------------------------------------------------------------------------------
% SUBSEC: TTL pulse rep
......@@ -463,10 +465,10 @@ the pull-up resistor.
%14~$\mu$s with a recommended minimum period of 140~$\mu$s (see Appendix~\ref{app:blo-max-pw}).
The maximum pulse frequency that can be sustained without damaging the MOSFET
is 210~kHz, with nominal blocking pulse widths of 1.2~$\mu$s \cite{blo-std}
(see Appendix~\ref{app:blo-max-freq}).
is 210~kHz, with nominal blocking pulse widths of 1.2~$\mu$s \cite{blo-std}.
%(see Appendix~\ref{app:blo-max-freq}).
%\vspace*{11pt}
\vspace*{11pt}
\noindent \textbf{\textit{Note that if the FPGA is improperly configured, a DC high-level signal
on the power MOSFET's grid pin will yield a too high current passing through the MOSFET,
......@@ -475,13 +477,13 @@ are properly configured to drive time-limited pulses or a DC low-level at the po
MOSFET's grid, or that the blocking output enable signal from the FPGA is low, so as to
keep the outputs of the tri-state buffers in high-impedance.}}
\textcolor{red}{\textbf{details about output circuit}}
\textcolor{red}{\textbf{galvanic isolation}}
\textcolor{red}{\textbf{max outp. PW calculation}}
\textcolor{red}{\textbf{danger in case of no firmware}}
%\textcolor{red}{\textbf{details about output circuit}}
%
%\textcolor{red}{\textbf{galvanic isolation}}
%
%\textcolor{red}{\textbf{max outp. PW calculation}}
%
%\textcolor{red}{\textbf{danger in case of no firmware}}
%------------------------------------------------------------------------------
% SEC: Blocking pulse rep
......@@ -572,7 +574,7 @@ The circuit for driving the bicolor status LEDs is based on the SVEC design \cit
It consists of the same Texas Instruments SN74VMEH22501DGGR bus buffer chip used
for buffering the VME signals. The control and data lines of the chip are driven
by logic within the FPGA, which controls lighting of each of the LEDs. An example
of how the LEDs can be driven using the FPGA is given in Section~5 of \textcolor{red}{CITE HDL GUIDE}.
of how the LEDs can be driven using the FPGA is given in Section~5 of~\cite{ctb-hdlguide}.
TTL (front panel) and blocking (rear panel) pulse LEDs are driven by the FPGA
via a SN7414 Schmitt trigger. In the case of the blocking LEDs, the output of
......@@ -595,12 +597,10 @@ are detailed in the next subsections.
%------------------------------------------------------------------------------
\subsection{RTM Motherboard}
The RTM motherboard~\cite{rtmm-sch} is the interface between the VME P2 connector and the
RTM piggyback board. It provides a female connector to the VME backplane P2
connector and links the blocking and pulse LED signals from the CONV-TTL-BLO
to the piggyback via a 100-pin connector.
\textcolor{red}{\textbf{board pic}}
The CONV-TTL-RTM motherboard~\cite{rtmm-sch} is the interface between the VME P2
connector and the RTM piggyback board. It provides a female connector to the VME
backplane P2 connector and links the blocking and pulse LED signals from the
CONV-TTL-BLO to the piggyback via a 100-pin connector.
RTM motherboards are used in both CONV-TTL-BLO and CONV-TTL-RS485 systems, with
different piggybacks.
......@@ -613,14 +613,13 @@ high-voltage pulses arriving on piggyback LEMO connectors.
%------------------------------------------------------------------------------
\subsection{RTM Piggyback}
The RTM piggyback~\cite{rtmp-sch} provides the actual connectors on rear panels of
TTL to blocking converter systems. On each of the six blocking channels, there are
four LEMO connectors (one input and three outputs) and one LED together with its
corresponding current-limiting resistor. The connections for each of the LEMOs and
LEDs are made via the 100-pin male connector, through the RTM motherboard, to the
CONV-TTL-BLO.
The CONV-TTL-RTM-BLO piggyback~\cite{rtmp-sch}, provides the
actual connectors on rear panels of TTL to blocking converter systems. On each of the
six blocking channels, there are four LEMO connectors (one input and three outputs)
and one LED together with its corresponding current-limiting resistor. The connections
for each of the LEMOs and LEDs are made via the 100-pin male connector, through the RTM
motherboard, to the CONV-TTL-BLO.
\textcolor{red}{\textbf{board pic}}
%==============================================================================
% Appendices
......@@ -653,7 +652,7 @@ calculations below.
The optocoupler LED has a forward voltage of 1.5~V and therefore when the LED is on,
the voltage in point 2 of Figure~\ref{fig:blo-inp} is
\begin{equation}
\begin{equation}
V_2 = 1.5V
\end{equation}
......@@ -749,39 +748,94 @@ t_{p,max} \cong 3.9 {\mu}s
%==============================================================================
% APP: Block inp stage calc
%==============================================================================
\section{Blocking output stage calculations}
\label{app:blo-outp}
Figure~\ref{fig:blo-outp} shows the blocking output stage, as a reference for the
calculations below.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/blo-outp}}
\caption{Blocking output stage}
\label{fig:blo-outp}
\end{figure}
%\pagebreak
%\section{Blocking output stage calculations}
%\label{app:blo-outp}
%
%Figure~\ref{fig:blo-outp} shows the blocking output stage, as a reference for the
%calculations below.
%
%\begin{figure}[h]
% \centerline{\includegraphics[width=\textwidth]{fig/blo-outp}}
% \caption{Blocking output stage}
% \label{fig:blo-outp}
%\end{figure}
%
%%%------------------------------------------------------------------------------
%%% SUBSEC: max. pulse width
%%%------------------------------------------------------------------------------
%%\subsection{Maximum pulse width}
%%\label{app:blo-max-pw}
%%
%%The maximum current through the inductor is
%%
%%\begin{equation}
%%I_L = I_{max} \times (1 - e^{\frac{t}{\tau}})
%%\end{equation}
%
%%------------------------------------------------------------------------------
%% SUBSEC: max. pulse width
%% SUBSEC: max. pulse freq
%%------------------------------------------------------------------------------
%\subsection{Maximum pulse width}
%\label{app:blo-max-pw}
%\subsection{Maximum blocking pulse frequency}
%\label{app:blo-max-freq}
%
%The maximum blocking pulse frequency will be calculated in this section, considering
%the nominal (1.2~$\mu$s) and maximum (2~$\mu$s) blocking pulse widths \cite{blo-std}.
%All calculations made here are for operation at 25~$^\circ$C.
%
%The maximum current through the inductor is
%Power MOSFETs can withstand high currents on their inputs as long as these currents
%arrive as short pulses. What is important is for the MOSFET's temperature to not
%increase above 175~$^\circ$C. The MOSFET temperature rise is \cite{nxp-an11158}
%
%\begin{equation}
%I_L = I_{max} \times (1 - e^{\frac{t}{\tau}})
%T_{j(rise)max} = P_{av} * Z_{th}
%\end{equation}
%------------------------------------------------------------------------------
% SUBSEC: max. pulse freq
%------------------------------------------------------------------------------
\subsection{Maximum blocking pulse frequency}
\label{app:blo-max-freq}
The maximum blocking pulse frequency will be calculated in this section, considering
the nominal and maximum blocking pulse width as per \cite{blo-std}.
%
%\noindent where $Z_{th}$ is the thermal impedance of the MOSFET. The thermal impedance
%varies depending on duty cycle, with a maximum of 140~K/W in the case of the BSH103
%present on the CONV-TTL-BLO. The thermal impedance curve based on duty cycle can be found
%in the BSH103 datasheet \textcolor{red}{\textbf{cite datasheet}}.
%
%When the MOSFET is turned on, it introduces its R$_{DS(on)}$ resistance into the
%circuit. Together with the transformer primary, this forms an RL circuit through which
%after 1.2~$\mu$s will pass a current of
%
%\begin{align}
%I_D & = \frac{V_{BLO}}{R_{DS(on)}} \left(( 1 - e^{-t\frac{R}{L}} \right) \nonumber \\
% & = \frac{24}{0.5} \left( 1 - e^{-1.2{\mu} \frac{0.5}{100{\mu}}} \right) \nonumber \\
% & \cong 0.3 A
%\end{align}
%
%%\begin{equation}
%%I_D =
%%\end{equation}
%
%After the same time, the voltage across the inductor will be
%
%\begin{align}
%V_L &= V_{BLO} \times e^{-\frac{R}{L}} \nonumber \\
% &= 24 \times e^{-\frac{0.5}{100{\mu}}} \nonumber \\
% &= 23.85 V
%\end{align}
%
%\noindent and so, the drain-to-source voltage of the MOSFET
%
%\begin{equation}
%V_{DS} = V_{BLO} - V_L = 0.15 V
%\end{equation}
%
%With this, the power of the pulse can be calculated
%
%\begin{equation}
%P = I_D \times V_{DS} = 0.045 W
%\end{equation}
%
%In order for the MOSFET to function properly, its temperature must not be more
%than 175~$^\circ$C. The temperature rise on the MOSFET is
%
%\noindent which in our case, starting from 25~$^\circ$C, is 150~$^\circ$C.
%
%To calculate the maximum pulse frequency, the pulse duty cycle which corresponds
%==============================================================================
......
doc/userguide/userguide-conv-ttl-blo.bib
View file @ 8aaf2d8f
......@@ -46,3 +46,18 @@
howpublished = {\url{https://edms.cern.ch/file/1278535/1/EDA-02446-V2-1_sch.pdf}}
}
@misc{ctb-hwguide,
author = "Theodor-Adrian Stana",
title = {{CONV-TTL-BLO Hardware Guide}},
month = 07,
year = 2013,
howpublished = {\url{http://www.ohwr.org/documents/282}}
}
@misc{ctb-hdlguide,
author = "Theodor-Adrian Stana",
title = {{CONV-TTL-BLO HDL Guide}},
month = 07,
year = 2013,
howpublished = {\url{http://www.ohwr.org/documents/283}}
}
doc/userguide/userguide-conv-ttl-blo.tex
View file @ 8aaf2d8f
......@@ -42,6 +42,7 @@
19-06-2013 & 1.00 & First version \\
21-06-2013 & 1.01 & Added termination resistors to Fig.~\ref{fig:ttl-chan},~\ref{fig:invttl-chan} \\
22-07-2013 & 1.02 & New title page and page layout \\
26-07-2013 & 1.03 & Added additional documentation subsection \\
\hline
\end{tabular}
}
......@@ -128,6 +129,16 @@ pulse generation and conversion from/to blocking, as well as galvanic isolation
blocking outputs. CONV-TTL-RTM is a passive module used as an interface from the rear
part of the VME crate to the front module.
%------------------------------------------------------------------------------
% SUBSEC: Additional doc
%------------------------------------------------------------------------------
\subsection*{Additional documentation}
\begin{itemize}
\item CONV-TTL-BLO Hardware Guide \cite{ctb-hwguide}
\item CONV-TTL-BLO HDL Guide \cite{ctb-hdlguide}
\end{itemize}
%======================================================================================
% SEC: Panels
%======================================================================================
......
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