working on write to flash chip, reading works

78ca5d50 · Theodor-Adrian Stana · c5f49592 · 78ca5d50 · 78ca5d50 · 78ca5d50
Commit 78ca5d50 authored Aug 23, 2013 by Theodor-Adrian Stana
18 changed files
--- a/hdl/multiboot/rtl/Manifest.py
+++ b/hdl/multiboot/rtl/Manifest.py
 files = [
    "multiboot_regs.vhd",
    "multiboot_fsm.vhd",
+    "spi_master.vhd",
+    "m25p_flash.vhd",
    "xil_multiboot.vhd"
    ]
--- a/hdl/multiboot/rtl/m25p_flash.vhd
+++ b/hdl/multiboot/rtl/m25p_flash.vhd
+-----------------------------------------------------------------------------
+-- Title      : M25Pxxx Flash Controller
+-- Project    : TTL to blocking/RS-485 converter
+-------------------------------------------------------------------------------
+-- File       : m25p_flash.vhd
+-- Authors    : Tomasz Wlostowski
+--              Theodor-Adrian Stana
+-- Company    : CERN
+-- Created    : 2013-01-24
+-- Last update: 2013-08-21
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Controller for M25Pxxx series of SPI flash memories. Provides
+-- read and write access to a Flash memory by means of external command bits.
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2013 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+--use work.sxldr_wbgen2_pkg.all;
+
+entity m25p_flash is
+  
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+--    -- Wishbone registers (FAR register access)
+--    regs_i : in  t_sxldr_out_registers;
+--    regs_o : out t_sxldr_in_registers;
+
+    -- Data readout interface. 
+
+    -- 1: sets flash read address to addr_i
+    set_addr_i : in std_logic;
+
+    -- start address for read operations
+    addr_i : in std_logic_vector(23 downto 0);
+
+    -- data request: when 1, the controller reads subsequent bytes from
+    -- the flash, starting from addr_i address.
+    read_i   : in std_logic;
+    write_i  : in std_logic;
+    endcmd_i : in std_logic;
+
+    -- read and write data I/O
+    data_i : in  std_logic_vector(7 downto 0);
+    data_o : out std_logic_vector(7 downto 0);
+
+    -- when 1, data_o contains a valid byte and the controller is ready to accept
+    -- another command
+    ready_o : out std_logic;
+
+    -- SPI bus, connect to the flash memory.
+    spi_cs_n_o : out std_logic;
+    spi_sclk_o : out std_logic;
+    spi_mosi_o : out std_logic;
+    spi_miso_i : in  std_logic
+    );
+
+end m25p_flash;
+
+architecture behavioral of m25p_flash is
+
+  --============================================================================
+  -- Type declarations
+  --============================================================================
+  type t_state is 
+    (
+      IDLE,
+      WE_CMD,
+      WE_CSEL,
+      RW_CSEL,
+      RW_CMD,
+      ADDR0,
+      ADDR1,
+      ADDR2,
+      DUMMY_XFER,
+      RDATA,
+      WDATA
+    );
+
+  --============================================================================
+  -- Component declarations
+  --============================================================================
+  component spi_master
+    generic (
+      g_div_ratio_log2 : integer;
+      g_num_data_bits  : integer);
+    port (
+      clk_sys_i  : in  std_logic;
+      rst_n_i    : in  std_logic;
+      cs_i       : in  std_logic;
+      start_i    : in  std_logic;
+      cpol_i     : in  std_logic;
+      data_i     : in  std_logic_vector(g_num_data_bits - 1 downto 0);
+      ready_o    : out std_logic;
+      data_o     : out std_logic_vector(g_num_data_bits - 1 downto 0);
+      spi_cs_n_o : out std_logic;
+      spi_sclk_o : out std_logic;
+      spi_mosi_o : out std_logic;
+      spi_miso_i : in  std_logic);
+  end component;
+
+  --============================================================================
+  -- Signal declarations
+  --============================================================================
+  signal spi_cs, spi_cs_muxed                       : std_logic;
+  signal spi_start, spi_start_host, spi_start_muxed : std_logic;
+  signal spi_wdata, spi_wdata_host, spi_wdata_muxed : std_logic_vector(7 downto 0);
+  signal spi_rdata                                  : std_logic_vector(7 downto 0);
+  signal spi_ready                                  : std_logic;
+
+  signal fsm_cmd     : std_logic_vector(2 downto 0);
+  signal fsm_cmd_reg : std_logic_vector(2 downto 0);
+  signal state       : t_state;
+  signal ready_int   : std_logic;
+  
+  signal send_cmd    : std_logic;
+
+begin  -- rtl
+
+--  -- Host flash data register (bidirectional), updated by writing to FAR.RDATA
+--  p_host_spi_registers : process(clk_sys_i)
+--  begin
+--    if rising_edge(clk_sys_i) then
+--      if rst_n_i = '0' then
+--        spi_start_host <= '0';
+--        spi_wdata_host <= (others => '0');
+--      elsif regs_i.far_data_load_o = '1' then
+--        spi_wdata_host <= regs_i.far_data_o;
+--        spi_start_host <= regs_i.far_xfer_o;
+--      else
+--        spi_start_host <= '0';
+--      end if;
+--    end if;
+--  end process;
+
+
+--  -- Multplexes the access between to the flash SPI controller between
+--  -- the bootloader host (through FAR register) and the flash readout
+--  -- FSM. 
+--  p_mux_spi_access : process(spi_cs, spi_start, spi_wdata, spi_start_host, spi_wdata, spi_ready, regs_i, state)
+--  begin
+--    spi_cs_muxed       <= regs_i.far_cs_o or spi_cs;
+--    spi_wdata_muxed    <= spi_wdata_host or spi_wdata;
+--    spi_start_muxed    <= spi_start_host or spi_start;
+--  end process;
+
+--  regs_o.far_ready_i <= spi_ready;
+--  regs_o.far_data_i <= spi_rdata;
+  
+  -- SPI Master: executes SPI read/write transactions.
+  U_SPI_Master : spi_master
+    generic map (
+      g_div_ratio_log2 => 0,
+      g_num_data_bits  => 8)
+    port map (
+      clk_sys_i  => clk_sys_i,
+      rst_n_i    => rst_n_i,
+      cs_i       => spi_cs, -- spi_cs_muxed,
+      start_i    => spi_start, -- spi_start_muxed,
+      cpol_i     => '0',
+      data_i     => spi_wdata, -- spi_wdata_muxed,
+      ready_o    => spi_ready,
+      data_o     => spi_rdata,
+      spi_cs_n_o => spi_cs_n_o,
+      spi_sclk_o => spi_sclk_o,
+      spi_mosi_o => spi_mosi_o,
+      spi_miso_i => spi_miso_i);
+
+
+  -- FSM command vector out of inputs
+  fsm_cmd <= endcmd_i & write_i & read_i;
+
+  -- Main State machine
+  p_main_fsm : process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        state     <= IDLE;
+        spi_start <= '0';
+        spi_cs    <= '0';
+        spi_wdata <= (others => '0');
+        ready_int <= '1';
+        data_o    <= (others => '0');
+        send_cmd  <= '1';
+--        -- any access to FAR register stops internal bus request
+--      elsif(regs_i.far_data_load_o = '1') then
+--        spi_start <= '0';
+--        spi_cs    <= '0';
+--        spi_wdata <= (others => '0');
+--        state <= IDLE;
+      else
+        case state is
+          -- Idle: wait for "Set Address" or "Read" commands
+          when IDLE =>
+            fsm_cmd_reg <= fsm_cmd;
+            case fsm_cmd is
+              when "001" =>
+                if (send_cmd = '1') then
+                  send_cmd  <= '0';
+                  spi_cs    <= '0';
+                  spi_start <= '1';
+                  ready_int <= '0';
+                  state     <= RW_CSEL;
+                else
+                  spi_start <= '1';
+                  ready_int <= '0';
+                  state     <= RDATA;
+                end if;
+              when "010" =>
+                if (send_cmd = '1') then
+                  send_cmd  <= '0';
+                  spi_cs    <= '0';
+                  spi_start <= '1';
+                  ready_int <= '0';
+                  state     <= WE_CSEL;
+                else
+                  spi_wdata <= data_i;
+                  spi_start <= '1';
+                  ready_int <= '0';
+                  state     <= WDATA;
+                end if;
+              when "100" =>
+                spi_cs   <= '0';
+                send_cmd <= '1';
+                state    <= IDLE;
+              when others =>
+                state  <= IDLE;
+            end case;
+
+            --if set_addr_i = '1' then
+            --  spi_cs    <= '0';
+            --  spi_start <= '1';
+            --  ready_int <= '0';
+            --  state     <= RW_CSEL;
+            --elsif read_i = '1' then
+            --  spi_start <= '1';
+            --  ready_int <= '0';
+            --  state     <= RDATA;
+            --else
+            --  spi_start <= '0';
+            --  ready_int <= '1';
+            --end if;
+
+          -- executes a dummy SPI cycle with the SPI chip disabled (CS = 0), to
+          -- make sure it will correctly interpret the next transfer as a READ
+          -- command
+          when WE_CSEL =>
+            if(spi_ready = '1') then
+              spi_cs    <= '1';
+              spi_start <= '1';
+              spi_wdata <= x"06";
+              state     <= WE_CMD;
+            else
+              spi_start <= '0';
+            end if;
+
+          -- the write enable command is sent during this cycle
+          when WE_CMD =>
+            spi_start <= '0';
+            if (spi_ready = '1') then
+              spi_cs    <= '0';
+              spi_start <= '1';
+              state     <= RW_CSEL;
+            end if;
+
+            -- executes a dummy SPI cycle with the SPI chip disabled (CS = 0), to
+            -- make sure it will correctly interpret the next transfer as a READ
+            -- command
+          when RW_CSEL =>
+            if(spi_ready = '1') then
+              case fsm_cmd_reg is
+                when "001" =>
+                  spi_cs    <= '1';
+                  spi_start <= '1';
+                  spi_wdata <= x"0b";
+                  state     <= RW_CMD;
+                when "010" =>
+                  spi_cs    <= '1';
+                  spi_start <= '1';
+                  spi_wdata <= x"02";
+                  state     <= RW_CMD;
+                when others =>
+                  state <= IDLE;
+              end case;
+            else
+              spi_start <= '0';
+            end if;
+
+            -- Send command 0x0B (fast read) or 0x02 (page program)
+          when RW_CMD =>
+            if(spi_ready = '1') then
+              state     <= ADDR0;
+              spi_wdata <= addr_i(23 downto 16);
+              spi_start <= '1';
+            else
+              spi_start <= '0';
+            end if;
+
+            -- Send 1st byte of read address
+          when ADDR0 =>
+            if(spi_ready = '1') then
+              state     <= ADDR1;
+              spi_wdata <= addr_i(15 downto 8);
+              spi_start <= '1';
+            else
+              spi_start <= '0';
+            end if;
+
+            -- Send 2nd byte of read address
+          when ADDR1 =>
+            if(spi_ready = '1') then
+              state     <= ADDR2;
+              spi_wdata <= addr_i(7 downto 0);
+              spi_start <= '1';
+            else
+              spi_start <= '0';
+            end if;
+
+            -- Send 3rd byte of read address
+          when ADDR2 =>
+            if(spi_ready = '1') then
+              case fsm_cmd_reg is
+                when "001" =>
+                  spi_wdata <= "XXXXXXXX";
+                  spi_start <= '1';
+                  state     <= DUMMY_XFER;
+                when "010" =>
+                  spi_wdata <= data_i;
+                  spi_start <= '1';
+                  state     <= WDATA;
+                when others =>
+                  state <= IDLE;
+              end case;
+            else
+              spi_start <= '0';
+            end if;
+
+            -- dummy transfer (necessary for fast read mode)
+          when DUMMY_XFER =>
+            spi_start <= '0';
+            if(spi_ready = '1') then
+              state <= RDATA;
+              spi_start <= '1';
+            end if;
+
+            -- Data readout: waits for completion of read transaction initiated
+            -- upon assertion of read_i and returns the byte read data_o.
+          when RDATA =>
+            spi_start <= '0';
+            if(spi_ready = '1')then
+              data_o    <= spi_rdata;
+              ready_int <= '1';
+              state     <= IDLE;
+            else
+              ready_int <= '0';
+            end if;
+
+          -- wait for completion of write cycle
+          when WDATA =>
+            spi_start <= '0';
+            if(spi_ready = '1')then
+              ready_int <= '1';
+              state     <= IDLE;
+            else
+              ready_int <= '0';
+            end if;
+
+          when others =>
+            state <= IDLE;
+        end case;
+      end if;
+    end if;
+  end process;
+
+  -- De-assert ready flag early
+  ready_o <= ready_int and not (endcmd_i or write_i or read_i);
+  
+end behavioral;
+
--- a/hdl/multiboot/rtl/multiboot_fsm.vhd
+++ b/hdl/multiboot/rtl/multiboot_fsm.vhd
@@ -45,30 +45,50 @@ entity multiboot_fsm is
  port
  (
    -- Clock and reset inputs
-    clk_i           : in  std_logic;
-    rst_n_i         : in  std_logic;
+    clk_i                : in  std_logic;
+    rst_n_i              : in  std_logic;

    -- Control register inputs
-    rdbootsts_i     : in  std_logic;
-    wmb_i           : in  std_logic;
-    wgb_i           : in  std_logic;
-    iprog_i         : in  std_logic;
+    reg_rdbootsts_i      : in  std_logic;
+    reg_wmb_i            : in  std_logic;
+    reg_wgb_i            : in  std_logic;
+    reg_iprog_i          : in  std_logic;
+    reg_flr_i            : in  std_logic;
+    reg_flw_i            : in  std_logic;

    -- Multiboot and golden bitstream start addresses
-    gbbar_i         : in  std_logic_vector(31 downto 0);
-    mbbar_i         : in  std_logic_vector(31 downto 0);
+    reg_gbbar_i          : in  std_logic_vector(31 downto 0);
+    reg_mbbar_i          : in  std_logic_vector(31 downto 0);

    -- Outputs to status register
-    bootsts_img_o   : out std_logic_vector(15 downto 0);
-    bootsts_valid_o : out std_logic;
+    reg_bootsts_img_o    : out std_logic_vector(15 downto 0);
+    reg_bootsts_valid_o  : out std_logic;
+
+    -- Flash read data and ready bit
+    reg_flrd_o           : out std_logic_vector(31 downto 0);
+    reg_flrrdy_o         : out std_logic;
+    
+    -- Flash write data and ready bit
+    reg_flwd_i           : in  std_logic_vector(31 downto 0);
+    reg_flwrdy_o         : out std_logic;
+
+    -- Ports for the external flash controller component
+    fl_set_addr_o        : out std_logic;
+    fl_addr_o            : out std_logic_vector(23 downto 0);
+    fl_read_o            : out std_logic;
+    fl_write_o           : out std_logic;
+    fl_endcmd_o          : out std_logic; 
+    fl_data_o            : out std_logic_vector(7 downto 0);
+    fl_data_i            : in  std_logic_vector(7 downto 0);
+    fl_ready_i           : in  std_logic;

    -- Ports for the external ICAP component
-    icap_dat_i      : in  std_logic_vector(15 downto 0);
-    icap_dat_o      : out std_logic_vector(15 downto 0);
+    icap_dat_i           : in  std_logic_vector(15 downto 0);
+    icap_dat_o           : out std_logic_vector(15 downto 0);

-    icap_busy_i     : in  std_logic;
-    icap_ce_n_o     : out std_logic;
-    icap_wr_n_o     : out std_logic
+    icap_busy_i          : in  std_logic;
+    icap_ce_n_o          : out std_logic;
+    icap_wr_n_o          : out std_logic
  );
 end entity multiboot_fsm;

@@ -81,6 +101,9 @@ architecture behav of multiboot_fsm is
  type t_state is
    (
      IDLE,
+      FLR_CMDADDR,
+      FLR_DATA,
+      FLW_DATA,
      DUMMY_1,
      DUMMY_2,
      SYNC_H,
@@ -128,49 +151,121 @@ architecture behav of multiboot_fsm is
  --============================================================================
  signal state       : t_state;

-  signal fsm_cmd     : std_logic_vector(3 downto 0);
-  signal fsm_cmd_reg : std_logic_vector(3 downto 0);
+  signal fsm_cmd     : std_logic_vector(5 downto 0);
+  signal fsm_cmd_reg : std_logic_vector(5 downto 0);

+  signal fl_bcnt : unsigned(1 downto 0);
+
+  signal fl_sreg : std_logic_vector(31 downto 0);
 --==============================================================================
 --  architecture begin
 --==============================================================================
 begin

+  reg_flrd_o <= fl_sreg;
+  fl_data_o  <= fl_sreg(7 downto 0);
+
  --============================================================================
  -- FSM logic
  --============================================================================
  -- Form state machine command vector from inputs
-  fsm_cmd <= iprog_i & wgb_i & wmb_i & rdbootsts_i;
+  fsm_cmd <= reg_flw_i   &
+             reg_flr_i   &
+             reg_iprog_i &
+             reg_wgb_i   &
+             reg_wmb_i   &
+             reg_rdbootsts_i;

  -- The state machine process
  p_fsm : process(clk_i)
  begin
    if rising_edge(clk_i) then
      if (rst_n_i = '0') then
-        state           <= IDLE;
-        fsm_cmd_reg     <= (others => '0');
-        icap_dat_o      <= (others => '0');
-        icap_ce_n_o     <= '1';
-        icap_wr_n_o     <= '1';
-        bootsts_img_o   <= (others => '0');
-        bootsts_valid_o <= '0';
+        state               <= IDLE;
+        fsm_cmd_reg         <= (others => '0');
+        icap_dat_o          <= (others => '0');
+        icap_ce_n_o         <= '1';
+        icap_wr_n_o         <= '1';
+        reg_bootsts_img_o   <= (others => '0');
+        reg_bootsts_valid_o <= '0';
+        fl_set_addr_o       <= '0';
+        fl_addr_o           <= (others => '0');
+        fl_read_o           <= '0';
+        fl_write_o          <= '0';
+        fl_endcmd_o         <= '0';
+        fl_bcnt             <= (others => '0');
+
+        reg_flrrdy_o        <= '0';
+        fl_sreg             <= (others => '0');
+
      else

        case state is

          when IDLE =>
+            --fl_set_addr_o <= '0';
+            fl_read_o   <= '0';
+            fl_write_o  <= '0';
+            fl_endcmd_o <= '0';
            icap_ce_n_o <= '1';
            icap_wr_n_o <= '1';
+            fsm_cmd_reg <= fsm_cmd;
            case fsm_cmd is
-              when "1000" | "0001" =>
+              when "001000" | "000001" =>
                state <= DUMMY_1;
-
+              when "010000" =>
+                state         <= FLR_DATA;
+                reg_flrrdy_o  <= '0';
+                -- fl_set_addr_o <= '1';
+                fl_read_o     <= '1';
+                fl_addr_o     <= reg_gbbar_i(23 downto 0);
+              when "100000" =>
+                state        <= FLW_DATA;
+                reg_flwrdy_o <= '0';
+                fl_write_o   <= '1';
+                fl_addr_o    <= reg_gbbar_i(23 downto 0);
+                fl_sreg      <= reg_flwd_i;
              when others =>
                state <= IDLE;
-
            end case;

-            fsm_cmd_reg <= fsm_cmd;
+          --====================================================================
+          -- Flash read sequence
+          --====================================================================
+          --when FLR_CMDADDR =>
+          --  fl_read_o <= '0';
+          --  if (fl_ready_i = '1') then
+          --    state     <= FLR_DATA;
+          --    fl_read_o <= '1';
+          --  end if;
+
+          when FLR_DATA =>
+            fl_read_o <= '0';
+            if (fl_ready_i = '1') then
+              fl_read_o <= '1';
+              fl_bcnt   <= fl_bcnt + 1;
+              fl_sreg    <= fl_data_i & fl_sreg(31 downto 8);
+              if (fl_bcnt = (fl_bcnt'range => '1')) then
+                fl_read_o    <= '0';
+                fl_endcmd_o  <= '1';
+                reg_flrrdy_o <= '1';
+                state        <= IDLE;
+              end if;
+            end if;
+            
+          when FLW_DATA =>
+            fl_write_o <= '0';
+            if (fl_ready_i = '1') then
+              fl_write_o <= '1';
+              fl_bcnt    <= fl_bcnt + 1;
+              fl_sreg   <= x"00" & fl_sreg(31 downto 8);
+              if (fl_bcnt = (fl_bcnt'range => '1')) then
+                fl_write_o   <= '0';
+                fl_endcmd_o  <= '1';
+                reg_flwrdy_o <= '1';
+                state        <= IDLE;
+              end if;
+            end if;

          --====================================================================
          -- Synchronization sequence + four NOOPs
@@ -205,9 +300,9 @@ begin
            icap_ce_n_o <= '0';
            icap_wr_n_o <= '0';
            case fsm_cmd_reg is
-              when "1000" =>
+              when "001000" =>
                state <= GEN_1;
-              when "0001" =>
+              when "000001" =>
                state <= BOOTSTS_CMD;
              when others =>
                state <= IDLE;
@@ -224,7 +319,7 @@ begin
            state       <= MBA_L;

          when MBA_L =>
-            icap_dat_o  <= mbbar_i(15 downto 0);
+            icap_dat_o  <= reg_mbbar_i(15 downto 0);
            icap_ce_n_o <= '0';
            icap_wr_n_o <= '0';
            state       <= GEN_2;
@@ -236,7 +331,7 @@ begin
            state       <= MBA_H;

          when MBA_H =>
-            icap_dat_o  <= mbbar_i(31 downto 16);
+            icap_dat_o  <= reg_mbbar_i(31 downto 16);
            icap_ce_n_o <= '0';
            icap_wr_n_o <= '0';
            state       <= GEN_3;
@@ -248,7 +343,7 @@ begin
            state       <= GBA_L;

          when GBA_L =>
-            icap_dat_o  <= gbbar_i(15 downto 0);
+            icap_dat_o  <= reg_gbbar_i(15 downto 0);
            icap_ce_n_o <= '0';
            icap_wr_n_o <= '0';
            state       <= GEN_4;
@@ -260,7 +355,7 @@ begin
            state       <= GBA_H;

          when GBA_H =>
-            icap_dat_o  <= gbbar_i(31 downto 16);
+            icap_dat_o  <= reg_gbbar_i(31 downto 16);
            icap_ce_n_o <= '0';
            icap_wr_n_o <= '0';
            state       <= IPROG_CMD;
@@ -330,9 +425,9 @@ begin
            icap_ce_n_o <= '0';
            icap_wr_n_o <= '1';
            if (icap_busy_i = '0') then
-              bootsts_img_o   <= icap_dat_i;
-              bootsts_valid_o <= '1';
-              state           <= BOOTSTS_SETWR_1;
+              reg_bootsts_img_o   <= icap_dat_i;
+              reg_bootsts_valid_o <= '1';
+              state               <= BOOTSTS_SETWR_1;
            end if;

          when BOOTSTS_SETWR_1 =>
@@ -388,7 +483,7 @@ begin
            state       <= IDLE;

          --====================================================================
-          -- Safety net
+          -- Go to IDLE in case of state error
          --====================================================================
          when others =>
            state <= IDLE;

--- a/hdl/multiboot/rtl/multiboot_regs.vhd
+++ b/hdl/multiboot/rtl/multiboot_regs.vhd
@@ -10,7 +10,7 @@
 -- version: 1.0
 --
 -- description: Implements the control status and address registers and
--              Wishbone interface for the design.
+--              Wishbone interface for the MultiBoot design.
 -- 
 --==============================================================================
 -- GNU LESSER GENERAL PUBLIC LICENSE
@@ -42,7 +42,7 @@ entity multiboot_regs is
    clk_sys_i          : in     std_logic;

    -- Wishbone ports
-    wb_adr_i           : in     std_logic_vector(1 downto 0);
+    wb_adr_i           : in     std_logic_vector(2 downto 0);
    wb_dat_i           : in     std_logic_vector(31 downto 0);
    wb_dat_o           : out    std_logic_vector(31 downto 0);
    wb_cyc_i           : in     std_logic;
@@ -57,39 +57,58 @@ entity multiboot_regs is
    multiboot_cr_wmb_o           : out    std_logic;
    multiboot_cr_wgb_o           : out    std_logic;
    multiboot_cr_iprog_o         : out    std_logic;
+    multiboot_cr_flr_o           : out    std_logic;
+    multiboot_cr_flw_o           : out    std_logic;

    -- Fields of status register
    multiboot_sr_bootsts_img_i   : in std_logic_vector(15 downto 0);
    multiboot_sr_valid_i         : in std_logic;
+    multiboot_sr_flrrdy_i        : in std_logic;
+    multiboot_sr_flwrdy_i        : in std_logic;

    -- Fields of bitstream address registers
    multiboot_gbbar_o            : out std_logic_vector(31 downto 0);
-    multiboot_mbbar_o            : out std_logic_vector(31 downto 0)
+    multiboot_mbbar_o            : out std_logic_vector(31 downto 0);
+
+    -- Fields of bitstream address registers
+    multiboot_flrdr_i             : in  std_logic_vector(31 downto 0);
+    multiboot_flwdr_o             : out std_logic_vector(31 downto 0)
  );
 end multiboot_regs;

 architecture behav of multiboot_regs is

-signal multiboot_cr_rdbootsts_int               : std_logic;
-signal multiboot_cr_wmb_int                     : std_logic;
-signal multiboot_cr_wgb_int                     : std_logic;
-signal multiboot_cr_iprog_int                   : std_logic;
-signal multiboot_sr_bootsts_img_int             : std_logic_vector(15 downto 0);
-signal multiboot_sr_valid_int                   : std_logic;
-signal multiboot_gbbar_int, multiboot_mbbar_int : std_logic_vector(31 downto 0);
-signal ack_sreg                                 : std_logic_vector(1 downto 0);
-signal rddata_reg                               : std_logic_vector(31 downto 0);
-signal wrdata_reg                               : std_logic_vector(31 downto 0);
-signal rwaddr_reg                               : std_logic_vector(1 downto 0);
-signal ack_in_progress                          : std_logic;
+signal multiboot_cr_rdbootsts_int   : std_logic;
+signal multiboot_cr_wmb_int         : std_logic;
+signal multiboot_cr_wgb_int         : std_logic;
+signal multiboot_cr_iprog_int       : std_logic;
+signal multiboot_cr_flr_int         : std_logic;
+signal multiboot_cr_flw_int         : std_logic;
+signal multiboot_sr_bootsts_img_int : std_logic_vector(15 downto 0);
+signal multiboot_sr_valid_int       : std_logic;
+signal multiboot_sr_flrrdy_int      : std_logic;
+signal multiboot_sr_flwrdy_int      : std_logic;
+signal multiboot_gbbar_int          : std_logic_vector(31 downto 0);
+signal multiboot_mbbar_int          : std_logic_vector(31 downto 0);
+signal multiboot_flrdr_int          : std_logic_vector(31 downto 0);
+signal multiboot_flwdr_int          : std_logic_vector(31 downto 0);
+signal ack_sreg                     : std_logic_vector(1 downto 0);
+signal rddata_reg                   : std_logic_vector(31 downto 0);
+signal wrdata_reg                   : std_logic_vector(31 downto 0);
+signal rwaddr_reg                   : std_logic_vector(2 downto 0);
+signal ack_in_progress              : std_logic;

 begin

 -- Some internal signals assignments.
  wrdata_reg <= wb_dat_i;
  rwaddr_reg <= wb_adr_i;
+
  multiboot_sr_bootsts_img_int <= multiboot_sr_bootsts_img_i;
  multiboot_sr_valid_int       <= multiboot_sr_valid_i;
+  multiboot_sr_flrrdy_int      <= multiboot_sr_flrrdy_i;
+  multiboot_sr_flwrdy_int      <= multiboot_sr_flwrdy_i;
+  multiboot_flrdr_int          <= multiboot_flrdr_i;

 -- Main register bank access process.
  process (clk_sys_i, rst_n_i)
@@ -102,6 +121,7 @@ begin
      multiboot_cr_wmb_int       <= '0';
      multiboot_cr_wgb_int       <= '0';
      multiboot_cr_iprog_int     <= '0';
+      multiboot_cr_flr_int       <= '0';
      multiboot_gbbar_int        <= (others => '0');
      multiboot_mbbar_int        <= (others => '0');
    elsif rising_edge(clk_sys_i) then
@@ -113,6 +133,8 @@ begin
        multiboot_cr_wmb_int       <= '0';
        multiboot_cr_wgb_int       <= '0';
        multiboot_cr_iprog_int     <= '0';
+        multiboot_cr_flr_int       <= '0';
+        multiboot_cr_flw_int       <= '0';
        if (ack_sreg(0) = '1') then
          ack_in_progress <= '0';
        else
@@ -120,19 +142,21 @@ begin
      else
        if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
          case rwaddr_reg is
-          when "00" => 
+          when "000" => 
            if (wb_we_i = '1') then
              multiboot_cr_rdbootsts_int <= wrdata_reg(0);
              multiboot_cr_wmb_int <= wrdata_reg(1);
              multiboot_cr_wgb_int <= wrdata_reg(2);
              multiboot_cr_iprog_int <= wrdata_reg(3);
+              multiboot_cr_flr_int   <= wrdata_reg(4); 
+              multiboot_cr_flw_int   <= wrdata_reg(5); 
            end if;
            rddata_reg(0) <= multiboot_cr_rdbootsts_int;
            rddata_reg(1) <= multiboot_cr_wmb_int;
            rddata_reg(2) <= multiboot_cr_wgb_int;
            rddata_reg(3) <= multiboot_cr_iprog_int;
-            rddata_reg(4) <= 'X';
-            rddata_reg(5) <= 'X';
+            rddata_reg(4) <= multiboot_cr_flr_int;
+            rddata_reg(5) <= multiboot_cr_flw_int;
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
            rddata_reg(8) <= 'X';
@@ -161,13 +185,13 @@ begin
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "01" => 
+          when "001" => 
            if (wb_we_i = '1') then
            end if;
            rddata_reg(15 downto 0) <= multiboot_sr_bootsts_img_int;
-            rddata_reg(16) <= 'X';
-            rddata_reg(17) <= 'X';
-            rddata_reg(18) <= 'X';
+            rddata_reg(16) <= multiboot_sr_valid_int;
+            rddata_reg(17) <= multiboot_sr_flrrdy_int;
+            rddata_reg(18) <= multiboot_sr_flwrdy_int;
            rddata_reg(19) <= 'X';
            rddata_reg(20) <= 'X';
            rddata_reg(21) <= 'X';
@@ -180,23 +204,34 @@ begin
            rddata_reg(28) <= 'X';
            rddata_reg(29) <= 'X';
            rddata_reg(30) <= 'X';
-            rddata_reg(31) <= multiboot_sr_valid_int;
+            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "10" =>
+          when "010" =>
            if (wb_we_i = '1') then
              multiboot_gbbar_int <= wrdata_reg;
            end if;
            rddata_reg <= multiboot_gbbar_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
-          when "11" =>
+          when "011" =>
            if (wb_we_i = '1') then
              multiboot_mbbar_int <= wrdata_reg;
            end if;
            rddata_reg <= multiboot_mbbar_int;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
+          when "100" =>
+            rddata_reg <= multiboot_flrdr_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
+          when "101" =>
+            if (wb_we_i = '1') then
+              multiboot_flwdr_int <= wrdata_reg;
+            end if;
+            rddata_reg <= multiboot_flwdr_int;
+            ack_sreg(0) <= '1';
+            ack_in_progress <= '1';
          when others =>
 -- prevent the slave from hanging the bus on invalid address
            ack_in_progress <= '1';
@@ -220,10 +255,16 @@ begin
  multiboot_cr_wgb_o <= multiboot_cr_wgb_int;
 -- IPROG
  multiboot_cr_iprog_o <= multiboot_cr_iprog_int;
+-- Flash read
+  multiboot_cr_flr_o   <= multiboot_cr_flr_int;
+-- Flash write
+  multiboot_cr_flw_o   <= multiboot_cr_flw_int;
 -- GBBAR
  multiboot_gbbar_o <= multiboot_gbbar_int;
 -- MBBAR
  multiboot_mbbar_o <= multiboot_mbbar_int;
+-- Flash data word
+  multiboot_flwdr_o <= multiboot_flwdr_int;

  -- ACK signal generation. Just pass the LSB of ACK counter.
  wb_ack_o <= ack_sreg(0);

--- a/hdl/multiboot/rtl/multiboot_regs.wb
+++ b/hdl/multiboot/rtl/multiboot_regs.wb
-peripheral {
-  name = "MultiBoot registers";
-  hdl_entity = "multiboot_regs";
-  prefix = "multiboot";
-
-  reg {
-    name = "Control Register";
-    description = "Contains bits for controlling the MultiBoot module";
-    prefix = "cr";
-    field {
-      name = "Read BOOTSTS register";
-      prefix = "rdbootsts";
-      type = BIT;
-    };
-    field {
-      name = "Write MultiBoot Bitstream";
-      description = "Write a bitstream to Flash at the MultiBoot bitstream address";
-      prefix = "wmb";
-      type = BIT;
-    };
-    field {
-      name = "Write Golden Bitstream";
-      description = "Write a bitstream to Flash at the golden bitstream address";
-      prefix = "wgb";
-      type = BIT;
-    };
-    field {
-      name = "IPROG";
-      description = "Issue the IPROG command to configuration logic";
-      prefix = "iprog";
-      type = BIT;
-    };
-  };
-
-  reg {
-    name = "Status Register";
-    description = "Contains the BOOTSTS register image";
-    prefix = "sr";
-    field = {
-      name = "BOOTSTS image";
-      prefix = "bootsts_img";
-      type = SLV;
-      size = 16;
-      access_dev = WRITE_ONLY;
-      access_bus = READ_ONLY;
-    };
-  };
-};
--- a/hdl/multiboot/rtl/spi_master.vhd
+++ b/hdl/multiboot/rtl/spi_master.vhd
+-----------------------------------------------------------------------------
+-- Title      : SPI Bus Master
+-- Project    : Simple VME64x FMC Carrier (SVEC)
+-------------------------------------------------------------------------------
+-- File       : spi_master.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Created    : 2011-08-24
+-- Last update: 2013-01-25
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Description: Just a simple SPI master (bus-less). 
+-------------------------------------------------------------------------------
+--
+-- Copyright (c) 2011-2013 CERN / BE-CO-HT
+--
+-- This source file is free software; you can redistribute it   
+-- and/or modify it under the terms of the GNU Lesser General   
+-- Public License as published by the Free Software Foundation; 
+-- either version 2.1 of the License, or (at your option) any   
+-- later version.                                               
+--
+-- This source is distributed in the hope that it will be       
+-- useful, but WITHOUT ANY WARRANTY; without even the implied   
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
+-- PURPOSE.  See the GNU Lesser General Public License for more 
+-- details.                                                     
+--
+-- You should have received a copy of the GNU Lesser General    
+-- Public License along with this source; if not, download it   
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity spi_master is
+  generic(
+    -- clock division ratio (SCLK = clk_sys_i / (2 ** g_div_ratio_log2).
+    g_div_ratio_log2 : integer := 2;
+    -- number of data bits per transfer
+    g_num_data_bits  : integer := 2);
+  port (
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    -- state of the Chip select line (1 = CS active). External control
+    -- allows for multi-transfer commands (SPI master itself does not
+    -- control the state of spi_cs_n_o)
+    cs_i : in std_logic;
+
+    -- 1: start next transfer (using CPOL, DATA and SEL from the inputs below)
+    start_i    : in  std_logic;
+
+    -- Clock polarity: 1: slave clocks in the data on rising SCLK edge, 0: ...
+    -- on falling SCLK edge
+    cpol_i     : in  std_logic;
+
+    -- TX Data input 
+    data_i     : in  std_logic_vector(g_num_data_bits - 1 downto 0);
+
+    -- 1: data_o contains the result of last read operation. Core is ready to initiate
+    -- another transfer.
+    ready_o    : out std_logic;
+
+    -- data read from selected slave, valid when ready_o == 1.
+    data_o     : out std_logic_vector(g_num_data_bits - 1 downto 0);
+
+    -- these are obvious
+    spi_cs_n_o : out std_logic;
+    spi_sclk_o : out std_logic;
+    spi_mosi_o : out std_logic;
+    spi_miso_i : in  std_logic
+    );
+
+end spi_master;
+
+architecture behavioral of spi_master is
+
+  signal divider       : unsigned(11 downto 0);
+  signal tick : std_logic;
+
+  signal sreg    : std_logic_vector(g_num_data_bits-1 downto 0);
+  signal rx_sreg : std_logic_vector(g_num_data_bits-1 downto 0);
+
+  type   t_state is (IDLE, TX_CS, TX_DAT1, TX_DAT2, TX_SCK1, TX_SCK2, TX_CS2, TX_GAP);
+  signal state : t_state;
+  signal sclk  : std_logic;
+
+  signal counter : unsigned(4 downto 0);
+  
+begin  -- rtl
+
+  -- Simple clock divder. Produces a 'tick' signal which defines the timing for
+  -- the main state machine transitions.
+  p_divide_spi_clock: process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        divider <= (others => '0');
+      else
+        if(start_i = '1' or tick = '1') then
+          divider <= (others => '0');
+        else
+          divider <= divider + 1;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  tick <= divider(g_div_ratio_log2); 
+
+  -- Main state machine. Executes SPI transfers
+  p_main_fsm: process(clk_sys_i)
+  begin
+    if rising_edge(clk_sys_i) then
+      if rst_n_i = '0' then
+        state           <= IDLE;
+        sclk            <= '0';
+        sreg            <= (others => '0');
+        rx_sreg         <= (others => '0');
+        spi_mosi_o      <= '0';
+        data_o          <= (others => '0');
+        counter         <= (others => '0');
+      else
+        case state is
+          -- Waits for start of transfer command
+          when IDLE =>
+            sclk    <= '0';
+            counter <= (others => '0');
+            if(start_i = '1') then
+              sreg            <= data_i;
+              state           <= TX_CS;
+              spi_mosi_o      <= data_i(sreg'high);
+            end if;
+
+          -- Generates a gap between the externally asserted Chip Select and
+          -- the beginning of data transfer
+          when TX_CS =>
+            if tick = '1' then
+              state <= TX_DAT1;
+            end if;
+
+          -- Outputs subsequent bits to MOSI line.
+          when TX_DAT1 =>
+            if(tick = '1') then
+              spi_mosi_o <= sreg(sreg'high);
+              sreg       <= sreg(sreg'high-1 downto 0) & '0';
+              state      <= TX_SCK1;
+            end if;
+
+          -- Flips the SCLK (active edge)
+          when TX_SCK1 =>
+            if(tick = '1') then
+              sclk    <= not sclk;
+              counter <= counter + 1;
+              state   <= TX_DAT2;
+            end if;
+
+          -- Shifts in bits read from the slave
+          when TX_DAT2 =>
+
+            if(tick = '1') then
+              rx_sreg <= rx_sreg(rx_sreg'high-1 downto 0) & spi_miso_i;
+              state   <= TX_SCK2;
+            end if;
+
+          -- Flips the SCLK (inactive edge). Checks if all bits have been
+          -- transferred.
+          when TX_SCK2 =>
+            if(tick = '1') then
+              sclk <= not sclk;
+              if(counter = g_num_data_bits) then
+                state <= TX_CS2;
+              else
+                state <= TX_DAT1;
+              end if;
+            end if;
+
+          -- Generates a gap for de-assertoin of CS line
+          when TX_CS2 =>
+            if(tick = '1') then
+              state           <= TX_GAP;
+              data_o          <= rx_sreg;
+            end if;
+
+          when TX_GAP =>
+            if (tick = '1') then
+              state <= IDLE;
+            end if;
+        end case;
+      end if;
+    end if;
+  end process;
+
+  ready_o    <= '1' when (state = IDLE and start_i = '0') else '0';
+
+  -- SCLK polarity control
+  spi_sclk_o <= sclk xor cpol_i;
+  spi_cs_n_o <= not cs_i;
+  
+end behavioral;
+
--- a/hdl/multiboot/rtl/xil_multiboot.vhd
+++ b/hdl/multiboot/rtl/xil_multiboot.vhd
@@ -52,7 +52,13 @@ entity xil_multiboot is

    -- Wishbone ports
    wbs_i   : in  t_wishbone_slave_in;
-    wbs_o   : out t_wishbone_slave_out
+    wbs_o   : out t_wishbone_slave_out;
+
+    -- SPI ports
+    spi_cs_n_o : out std_logic;
+    spi_sclk_o : out std_logic;
+    spi_mosi_o : out std_logic;
+    spi_miso_i : in  std_logic
  );
 end entity xil_multiboot;

@@ -78,7 +84,7 @@ architecture behav of xil_multiboot is
      clk_sys_i          : in     std_logic;

      -- Wishbone ports
-      wb_adr_i           : in     std_logic_vector(1 downto 0);
+      wb_adr_i           : in     std_logic_vector(2 downto 0);
      wb_dat_i           : in     std_logic_vector(31 downto 0);
      wb_dat_o           : out    std_logic_vector(31 downto 0);
      wb_cyc_i           : in     std_logic;
@@ -93,14 +99,22 @@ architecture behav of xil_multiboot is
      multiboot_cr_wmb_o           : out    std_logic;
      multiboot_cr_wgb_o           : out    std_logic;
      multiboot_cr_iprog_o         : out    std_logic;
+      multiboot_cr_flr_o           : out    std_logic;
+      multiboot_cr_flw_o           : out    std_logic;

      -- Fields of status register
      multiboot_sr_bootsts_img_i   : in std_logic_vector(15 downto 0);
      multiboot_sr_valid_i         : in std_logic;
+      multiboot_sr_flrrdy_i        : in std_logic;
+      multiboot_sr_flwrdy_i        : in std_logic;

      -- Fields of bitstream address registers
      multiboot_gbbar_o            : out std_logic_vector(31 downto 0);
-      multiboot_mbbar_o            : out std_logic_vector(31 downto 0)
+      multiboot_mbbar_o            : out std_logic_vector(31 downto 0);
+
+      -- Fields of bitstream address registers
+      multiboot_flrdr_i             : in  std_logic_vector(31 downto 0);
+      multiboot_flwdr_o             : out std_logic_vector(31 downto 0)
    );
  end component multiboot_regs;

@@ -109,33 +123,93 @@ architecture behav of xil_multiboot is
    port
    (
      -- Clock and reset inputs
-      clk_i   : in  std_logic;
-      rst_n_i : in  std_logic;
+      clk_i                : in  std_logic;
+      rst_n_i              : in  std_logic;

      -- Control register inputs
-      rdbootsts_i : in  std_logic;
-      wmb_i       : in  std_logic;
-      wgb_i       : in  std_logic;
-      iprog_i     : in  std_logic;
+      reg_rdbootsts_i      : in  std_logic;
+      reg_wmb_i            : in  std_logic;
+      reg_wgb_i            : in  std_logic;
+      reg_iprog_i          : in  std_logic;
+      reg_flr_i            : in  std_logic;
+      reg_flw_i            : in  std_logic;

      -- Multiboot and golden bitstream start addresses
-      gbbar_i         : in  std_logic_vector(31 downto 0);
-      mbbar_i         : in  std_logic_vector(31 downto 0);
+      reg_gbbar_i          : in  std_logic_vector(31 downto 0);
+      reg_mbbar_i          : in  std_logic_vector(31 downto 0);

      -- Outputs to status register
-      bootsts_img_o   : out std_logic_vector(15 downto 0);
-      bootsts_valid_o : out std_logic;
-
-      -- Data input and outputs for ICAP component
-      icap_dat_i      : in  std_logic_vector(15 downto 0);
-      icap_dat_o      : out std_logic_vector(15 downto 0);
-
-      icap_busy_i     : in  std_logic;
-      icap_ce_n_o     : out std_logic;
-      icap_wr_n_o     : out std_logic
+      reg_bootsts_img_o    : out std_logic_vector(15 downto 0);
+      reg_bootsts_valid_o  : out std_logic;
+
+      -- Flash read data and ready bit
+      reg_flrd_o           : out std_logic_vector(31 downto 0);
+      reg_flrrdy_o         : out std_logic;
+
+      -- Flash write data and ready bit
+      reg_flwd_i           : in  std_logic_vector(31 downto 0);
+      reg_flwrdy_o         : out std_logic;
+
+      -- Ports for the external flash controller component
+      fl_set_addr_o        : out std_logic;
+      fl_addr_o            : out std_logic_vector(23 downto 0);
+      fl_read_o            : out std_logic;
+      fl_write_o           : out std_logic;
+      fl_endcmd_o          : out std_logic; 
+      fl_data_o            : out std_logic_vector(7 downto 0);
+      fl_data_i            : in  std_logic_vector(7 downto 0);
+      fl_ready_i           : in  std_logic;
+
+      -- Ports for the external ICAP component
+      icap_dat_i           : in  std_logic_vector(15 downto 0);
+      icap_dat_o           : out std_logic_vector(15 downto 0);
+
+      icap_busy_i          : in  std_logic;
+      icap_ce_n_o          : out std_logic;
+      icap_wr_n_o          : out std_logic
    );
  end component multiboot_fsm;

+  -- Flash controller component
+  component m25p_flash is
+    port (
+      clk_sys_i : in std_logic;
+      rst_n_i   : in std_logic;
+  
+  --    -- Wishbone registers (FAR register access)
+  --    regs_i : in  t_sxldr_out_registers;
+  --    regs_o : out t_sxldr_in_registers;
+  
+      -- Data readout interface. 
+  
+      -- 1: sets flash read address to addr_i
+      set_addr_i : in std_logic;
+  
+      -- start address for read operations
+      addr_i : in std_logic_vector(23 downto 0);
+  
+      -- data request: when 1, the controller reads subsequent bytes from
+      -- the flash, starting from addr_i address.
+      read_i   : in std_logic;
+      write_i  : in std_logic;
+      endcmd_i : in std_logic;
+  
+      -- read data output
+      data_i : in  std_logic_vector(7 downto 0);
+      data_o : out std_logic_vector(7 downto 0);
+  
+      -- when 1, data_o contains a valid byte and the controller is ready to accept
+      -- another command
+      ready_o : out std_logic;
+  
+      -- SPI bus, connect to the flash memory.
+      spi_cs_n_o : out std_logic;
+      spi_sclk_o : out std_logic;
+      spi_mosi_o : out std_logic;
+      spi_miso_i : in  std_logic
+      );
+  end component m25p_flash;
+
  --============================================================================
  -- Signal declarations
  --============================================================================
@@ -143,10 +217,30 @@ architecture behav of xil_multiboot is
  signal rdbootsts     : std_logic;
  signal wmb, wgb      : std_logic;
  signal iprog         : std_logic;
+  signal flr           : std_logic;
+  signal flw           : std_logic;
  signal bootsts_img   : std_logic_vector(15 downto 0);
  signal sr_valid      : std_logic;
  signal gbbar, mbbar  : std_logic_vector(31 downto 0);

+  -- FSM signals
+  signal fsm_icap_din  : std_logic_vector(15 downto 0);
+  signal fsm_icap_dout : std_logic_vector(15 downto 0);
+
+  -- Flash controller signals
+  signal fl_set_addr   : std_logic;
+  signal fl_addr       : std_logic_vector(23 downto 0);
+  signal fl_read       : std_logic;
+  signal fl_write      : std_logic;
+  signal fl_data_out   : std_logic_vector(7 downto 0);
+  signal fl_data_in    : std_logic_vector(7 downto 0);
+  signal fl_ready      : std_logic;
+  signal fl_endcmd     : std_logic;
+  signal flrd          : std_logic_vector(31 downto 0);
+  signal flrrdy        : std_logic;
+  signal flwd          : std_logic_vector(31 downto 0);
+  signal flwrdy        : std_logic;
+
  -- ICAP signals
  signal icap_ce_n     : std_logic;
  signal icap_wr_n     : std_logic;
@@ -154,10 +248,6 @@ architecture behav of xil_multiboot is
  signal icap_din      : std_logic_vector(15 downto 0);
  signal icap_dout     : std_logic_vector(15 downto 0);

-  -- FSM signals
-  signal fsm_icap_din  : std_logic_vector(15 downto 0);
-  signal fsm_icap_dout : std_logic_vector(15 downto 0);
-
 --==============================================================================
 --  architecture begin
 --==============================================================================
@@ -166,13 +256,18 @@ begin
  --============================================================================
  -- Register component instantiation
  --============================================================================
+  -- First, some unused signal assignments
+  wbs_o.err <= '0';
+  wbs_o.rty <= '0';
+
+  -- Now, instantiate the component
  cmp_regs : multiboot_regs
    port map
    (
      rst_n_i                    => rst_n_i,
      clk_sys_i                  => clk_i,

-      wb_adr_i                   => wbs_i.adr(3 downto 2),
+      wb_adr_i                   => wbs_i.adr(4 downto 2),
      wb_dat_i                   => wbs_i.dat,
      wb_dat_o                   => wbs_o.dat,
      wb_cyc_i                   => wbs_i.cyc,
@@ -186,12 +281,19 @@ begin
      multiboot_cr_wmb_o         => wmb,
      multiboot_cr_wgb_o         => wgb,
      multiboot_cr_iprog_o       => iprog,
+      multiboot_cr_flr_o         => flr,
+      multiboot_cr_flw_o         => flw,

      multiboot_sr_bootsts_img_i => bootsts_img,
      multiboot_sr_valid_i       => sr_valid,
+      multiboot_sr_flrrdy_i      => flrrdy,
+      multiboot_sr_flwrdy_i      => flwrdy,

      multiboot_gbbar_o          => gbbar,
-      multiboot_mbbar_o          => mbbar
+      multiboot_mbbar_o          => mbbar,
+
+      multiboot_flrdr_i          => flrd,
+      multiboot_flwdr_o          => flwd
    );

  --============================================================================
@@ -200,26 +302,63 @@ begin
  cmp_fsm : multiboot_fsm
    port map
    (
-      clk_i           => clk_i,
-      rst_n_i         => rst_n_i,
-
-      rdbootsts_i     => rdbootsts,
-      wmb_i           => wmb,
-      wgb_i           => wgb,
-      iprog_i         => iprog,
-
-      gbbar_i         => gbbar,
-      mbbar_i         => mbbar,
-
-      bootsts_img_o   => bootsts_img,
-      bootsts_valid_o => sr_valid,
-
-      icap_dat_i      => fsm_icap_din,
-      icap_dat_o      => fsm_icap_dout,
+      clk_i                => clk_i,
+      rst_n_i              => rst_n_i,
+
+      reg_rdbootsts_i      => rdbootsts,
+      reg_wmb_i            => wmb,
+      reg_wgb_i            => wgb,
+      reg_iprog_i          => iprog,
+      reg_flr_i            => flr,
+      reg_flw_i            => flw,
+
+      reg_gbbar_i          => gbbar,
+      reg_mbbar_i          => mbbar,
+
+      reg_bootsts_img_o    => bootsts_img,
+      reg_bootsts_valid_o  => sr_valid,
+      
+      fl_set_addr_o        => fl_set_addr,
+      fl_addr_o            => fl_addr,
+      fl_read_o            => fl_read,
+      fl_write_o           => fl_write,
+      fl_endcmd_o          => fl_endcmd,
+      fl_data_i            => fl_data_out,
+      fl_data_o            => fl_data_in,
+      fl_ready_i           => fl_ready,
+
+      reg_flrd_o           => flrd,
+      reg_flrrdy_o         => flrrdy,
+      reg_flwd_i           => flwd,
+      reg_flwrdy_o         => flwrdy,
+
+      icap_dat_i           => fsm_icap_din,
+      icap_dat_o           => fsm_icap_dout,
+      icap_busy_i          => icap_busy,
+      icap_ce_n_o          => icap_ce_n,
+      icap_wr_n_o          => icap_wr_n
+    );

-      icap_busy_i     => icap_busy,
-      icap_ce_n_o     => icap_ce_n,
-      icap_wr_n_o     => icap_wr_n
+  --============================================================================
+  -- Flash controller instantiation
+  --============================================================================
+  cmp_flash_ctrl : m25p_flash
+    port map
+    (
+      clk_sys_i  => clk_i,
+      rst_n_i    => rst_n_i,
+      set_addr_i => fl_set_addr,
+      addr_i     => fl_addr,
+      read_i     => fl_read,
+      write_i    => fl_write,
+      endcmd_i   => fl_endcmd,
+      data_o     => fl_data_out,
+      data_i     => fl_data_in,
+      ready_o    => fl_ready,
+      spi_cs_n_o => spi_cs_n_o,
+      spi_sclk_o => spi_sclk_o,
+      spi_mosi_o => spi_mosi_o,
+      spi_miso_i => spi_miso_i
    );

  --============================================================================

--- a/hdl/multiboot/sim/run.do
+++ b/hdl/multiboot/sim/run.do
@@ -2,7 +2,9 @@ vlib work

 vcom -explicit -93 "~/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
 vcom -explicit -93 "~/Projects/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
-
+                   
+vcom -explicit -93 "../rtl/spi_master.vhd"
+vcom -explicit -93 "../rtl/m25p_flash.vhd"
 vcom -explicit -93 "../rtl/multiboot_regs.vhd"
 vcom -explicit -93 "../rtl/multiboot_fsm.vhd"
 vcom -explicit -93 "../rtl/xil_multiboot.vhd"
@@ -15,4 +17,4 @@ log -r /*
 # add wave *
 do wave.do

-run 5 us
+run 20 us
--- a/hdl/multiboot/sim/testbench.vhd
+++ b/hdl/multiboot/sim/testbench.vhd
@@ -69,42 +69,15 @@ architecture behav of testbench is

      -- Wishbone ports
      wbs_i   : in  t_wishbone_slave_in;
-      wbs_o   : out t_wishbone_slave_out
-    );
-  end component xil_multiboot;
+      wbs_o   : out t_wishbone_slave_out;

-  component multiboot_regs is
-    port (
-      -- Clock and reset inputs
-      rst_n_i            : in     std_logic;
-      clk_sys_i          : in     std_logic;
-  
-      -- Wishbone ports
-      wb_adr_i           : in     std_logic_vector(1 downto 0);
-      wb_dat_i           : in     std_logic_vector(31 downto 0);
-      wb_dat_o           : out    std_logic_vector(31 downto 0);
-      wb_cyc_i           : in     std_logic;
-      wb_sel_i           : in     std_logic_vector(3 downto 0);
-      wb_stb_i           : in     std_logic;
-      wb_we_i            : in     std_logic;
-      wb_ack_o           : out    std_logic;
-      wb_stall_o         : out    std_logic;
-  
-      -- Fields of control register
-      multiboot_cr_rdbootsts_o     : out    std_logic;
-      multiboot_cr_wmb_o           : out    std_logic;
-      multiboot_cr_wgb_o           : out    std_logic;
-      multiboot_cr_iprog_o         : out    std_logic;
-  
-      -- Fields of status register
-      multiboot_sr_bootsts_img_i   : in std_logic_vector(15 downto 0);
-      multiboot_sr_valid_i         : in std_logic;
-  
-      -- Fields of bitstream address registers
-      multiboot_gbbar_o              : out std_logic_vector(31 downto 0);
-      multiboot_mbbar_o              : out std_logic_vector(31 downto 0)
+      -- SPI ports
+      spi_cs_n_o : out std_logic;
+      spi_sclk_o : out std_logic;
+      spi_mosi_o : out std_logic;
+      spi_miso_i : in  std_logic
    );
-  end component multiboot_regs;
+  end component xil_multiboot;

  --============================================================================
  -- Signal declarations
@@ -131,6 +104,11 @@ architecture behav of testbench is

  signal str : string(1 to 8);

+  signal sclk        : std_logic;
+  signal cs_n        : std_logic;
+  signal mosi        : std_logic;
+  signal miso        : std_logic;
+
 --==============================================================================
 --  architecture begin
 --==============================================================================
@@ -142,10 +120,15 @@ begin
  UUT: xil_multiboot
    port map
    (
-      rst_n_i => rst_n,
-      clk_i   => clk,
-      wbs_i   => wbs_in,
-      wbs_o   => wbs_out
+      rst_n_i    => rst_n,
+      clk_i      => clk,
+      wbs_i      => wbs_in,
+      wbs_o      => wbs_out,
+
+      spi_sclk_o => sclk,
+      spi_cs_n_o => cs_n,
+      spi_mosi_o => mosi,
+      spi_miso_i => miso
    );

  -- bind Wishbone ports to signals
@@ -189,100 +172,78 @@ begin

    wait for 1500ns;

-    -- Send IPROG
+    -- Write flash address
    wait for 200 ns;
-    str <= "wr-iprog";
-    adr <= x"00000000";
-    dat <= x"00000008";
+    str <= "wr-faddr";
+    adr <= x"00000008";
+    dat <= x"00000020";
    write <= '1';
    transfer <= '1';
    wait for c_clk_per;
    transfer <= '0';

-    -- Send RDBOOTSTS
+    -- Init flash read
    wait for 200 ns;
-    str <= "wr-bsts ";
+    str <= "wr-rdf  ";
    adr <= x"00000000";
-    dat <= x"00000001";
+    dat <= x"00000010";
    write <= '1';
    transfer <= '1';
    wait for c_clk_per;
    transfer <= '0';

-    -- Read from SR
-    wait for 500 ns;
-    str <= "rd-sr   ";
-    adr <= x"00000004";
-    write <= '0';
+    wait for 6000 ns;
+
+    -- Write flash data
+    wait for 200 ns;
+    str <= "wr-fdata";
+    adr <= x"00000014";
+    dat <= x"AA995566";
+    write <= '1';
    transfer <= '1';
    wait for c_clk_per;
    transfer <= '0';

-    ---- Read from CR
-    --wait for 30 ns;
-    --str <= "rd-cr   ";
-    --adr <= x"00000000";
-    --write <= '0';
-    --transfer <= '1';
-    --wait for c_clk_per;
-    --transfer <= '0';
+    -- Init flash write
+    wait for 200 ns;
+    str <= "wr-start";
+    adr <= x"00000000";
+    dat <= x"00000020";
+    write <= '1';
+    transfer <= '1';
+    wait for c_clk_per;
+    transfer <= '0';

-    ---- Read from SR
-    --wait for 30 ns;
-    --str <= "rd-sr   ";
-    --valid <= '1';
-    --bootsts_img <= x"f3f3";
-    --adr <= x"00000004";
-    --write <= '0';
-    --transfer <= '1';
-    --wait for c_clk_per;
-    --transfer <= '0';
+    wait for 6000 ns;

-    ---- write to GBBAR
-    --wait for 30 ns;
-    --str <= "wr-gbbar";
-    --adr <= x"00000008";
-    --dat <= x"0b012345";
-    --write <= '1';
-    --transfer <= '1';
-    --wait for c_clk_per;
-    --transfer <= '0';
+    -- Init flash read
+    wait for 200 ns;
+    str <= "wr-rdf  ";
+    adr <= x"00000000";
+    dat <= x"00000010";
+    write <= '1';
+    transfer <= '1';
+    wait for c_clk_per;
+    transfer <= '0';

-    ---- read from GBBAR
-    --wait for 30 ns;
-    --str <= "rd-gbbar";
-    --adr <= x"00000008";
-    --write <= '0';
-    --transfer <= '1';
-    --wait for c_clk_per;
-    --transfer <= '0';
+    wait for 6000 ns;

-    ---- write to MBBAR
-    --wait for 30 ns;
-    --str <= "wr-mbbar";
-    --adr <= x"0000000C";
-    --dat <= x"0b024321";
+    ---- Send IPROG
+    --wait for 200 ns;
+    --str <= "wr-iprog";
+    --adr <= x"00000000";
+    --dat <= x"00000008";
    --write <= '1';
    --transfer <= '1';
    --wait for c_clk_per;
    --transfer <= '0';

-    ---- read from MBBAR
-    --wait for 30 ns;
-    --str <= "rd-mbbar";
-    --adr <= x"0000000C";
-    --write <= '0';
-    --transfer <= '1';
-    --wait for c_clk_per;
-    --transfer <= '0';
-
-    ---- Read from SR
-    --wait for 30 ns;
-    --str <= "rd-sr   ";
-    --valid <= '1';
-    --bootsts_img <= x"3f3f";
-    --adr <= x"00000004";
-    --write <= '0';
+    ---- Send RDBOOTSTS
+    --wait for 200 ns;
+    --str <= "wr-bsts ";
+    --adr <= x"00000000";
+    --dat <= x"00000001";
+    --write <= '1';
    --transfer <= '1';
    --wait for c_clk_per;
    --transfer <= '0';

--- a/hdl/multiboot/sim/transcript
+++ b/hdl/multiboot/sim/transcript
@@ -8,408 +8,3 @@
 # //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.
 # //
 #  
-do run.do
-# ** Warning: (vlib-34) Library already exists at "work".
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Compiling package genram_pkg
-# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
-# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
-# -- Compiling package body genram_pkg
-# -- Loading package genram_pkg
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Loading package genram_pkg
-# -- Compiling package wishbone_pkg
-# -- Compiling package body wishbone_pkg
-# -- Loading package wishbone_pkg
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Compiling entity multiboot_regs
-# -- Compiling architecture behav of multiboot_regs
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Compiling entity multiboot_fsm
-# -- Compiling architecture behav of multiboot_fsm
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Loading package VCOMPONENTS
-# -- Loading package genram_pkg
-# -- Loading package wishbone_pkg
-# -- Compiling entity xil_multiboot
-# -- Compiling architecture behav of xil_multiboot
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Loading package genram_pkg
-# -- Loading package wishbone_pkg
-# -- Compiling entity testbench
-# -- Compiling architecture behav of testbench
-# ** Warning: [4] testbench.vhd(190): (vcom-1207) An abstract literal and an identifier must have a separator between them.
-# vsim -lib work -voptargs=\"+acc\" -debugdb work.testbench 
-# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
-# Loading std.standard
-# Loading std.textio(body)
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.numeric_std(body)
-# Loading work.genram_pkg(body)
-# Loading work.wishbone_pkg(body)
-# Loading work.testbench(behav)#1
-# Loading unisim.vcomponents
-# Loading work.xil_multiboot(behav)#1
-# Loading work.multiboot_regs(behav)#1
-# Loading work.multiboot_fsm(behav)#1
-# Loading ieee.std_logic_arith(body)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading unisim.vpkg(body)
-# ** Warning: (vsim-3479) Time unit 'ps' is less than the simulator resolution (1ns).
-#    Time: 0 ns  Iteration: 0  Instance: /testbench/UUT/cmp_icap
-# Loading unisim.icap_spartan6(icap_spartan6_v)#1
-# Loading unisim.sim_config_s6(sim_config_s6_v)#1
-# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.err, and its initial value is not used.
-# Therefore, simulation behavior may occur that is not in compliance with
-# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.err.
-# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.rty, and its initial value is not used.
-# Therefore, simulation behavior may occur that is not in compliance with
-# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.rty.
-# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
-# Therefore, simulation behavior may occur that is not in compliance with
-# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
-# ** Note:  Message :  ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
-#    Time: 1338 ns  Iteration: 2  Instance: /testbench/UUT/cmp_icap
-add wave  \
-sim:/testbench/UUT/cmp_icap/SIM_CONFIG_S6_INST/reg_addr
-add wave  \
-sim:/testbench/UUT/cmp_icap/SIM_CONFIG_S6_INST/rd_reg_addr
-add wave  \
-sim:/testbench/UUT/rdbootsts \
-sim:/testbench/UUT/iprog
-find drivers -source -time {1980 ns} -cause sim:/testbench/UUT/cmp_fsm/icap_dat_o
-do run.do
-# ** Warning: (vlib-34) Library already exists at "work".
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Compiling package genram_pkg
-# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
-# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
-# -- Compiling package body genram_pkg
-# -- Loading package genram_pkg
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Loading package genram_pkg
-# -- Compiling package wishbone_pkg
-# -- Compiling package body wishbone_pkg
-# -- Loading package wishbone_pkg
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Compiling entity multiboot_regs
-# -- Compiling architecture behav of multiboot_regs
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Compiling entity multiboot_fsm
-# -- Compiling architecture behav of multiboot_fsm
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Loading package VCOMPONENTS
-# -- Loading package genram_pkg
-# -- Loading package wishbone_pkg
-# -- Compiling entity xil_multiboot
-# -- Compiling architecture behav of xil_multiboot
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Loading package genram_pkg
-# -- Loading package wishbone_pkg
-# -- Compiling entity testbench
-# -- Compiling architecture behav of testbench
-# ** Warning: [4] testbench.vhd(190): (vcom-1207) An abstract literal and an identifier must have a separator between them.
-# vsim -lib work -voptargs=\"+acc\" -debugdb work.testbench 
-# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
-# ** Note: (vopt-143) Recognized 1 FSM in architecture body "multiboot_fsm(behav)".
-# Loading std.standard
-# Loading std.textio(body)
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.numeric_std(body)
-# Loading work.genram_pkg(body)
-# Loading work.wishbone_pkg(body)
-# Loading work.testbench(behav)#1
-# Loading unisim.vcomponents
-# Loading work.xil_multiboot(behav)#1
-# Loading work.multiboot_regs(behav)#1
-# Loading work.multiboot_fsm(behav)#1
-# Loading ieee.std_logic_arith(body)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading unisim.vpkg(body)
-# ** Warning: (vsim-3479) Time unit 'ps' is less than the simulator resolution (1ns).
-#    Time: 0 ns  Iteration: 0  Instance: /testbench/UUT/cmp_icap
-# Loading unisim.icap_spartan6(icap_spartan6_v)#1
-# Loading unisim.sim_config_s6(sim_config_s6_v)#1
-# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.err, and its initial value is not used.
-# Therefore, simulation behavior may occur that is not in compliance with
-# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.err.
-# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.rty, and its initial value is not used.
-# Therefore, simulation behavior may occur that is not in compliance with
-# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.rty.
-# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
-# Therefore, simulation behavior may occur that is not in compliance with
-# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
-# ** Note:  Message :  ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
-#    Time: 1338 ns  Iteration: 2  Instance: /testbench/UUT/cmp_icap
-add wave  \
-sim:/testbench/UUT/cmp_icap/SIM_CONFIG_S6_INST/rd_reg_addr
-add wave  \
-sim:/testbench/UUT/cmp_icap/SIM_CONFIG_S6_INST/reg_addr
-do run.do
-# ** Warning: (vlib-34) Library already exists at "work".
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Compiling package genram_pkg
-# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
-# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
-# -- Compiling package body genram_pkg
-# -- Loading package genram_pkg
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Loading package genram_pkg
-# -- Compiling package wishbone_pkg
-# -- Compiling package body wishbone_pkg
-# -- Loading package wishbone_pkg
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Compiling entity multiboot_regs
-# -- Compiling architecture behav of multiboot_regs
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Compiling entity multiboot_fsm
-# -- Compiling architecture behav of multiboot_fsm
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Loading package VCOMPONENTS
-# -- Loading package genram_pkg
-# -- Loading package wishbone_pkg
-# -- Compiling entity xil_multiboot
-# -- Compiling architecture behav of xil_multiboot
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Loading package genram_pkg
-# -- Loading package wishbone_pkg
-# -- Compiling entity testbench
-# -- Compiling architecture behav of testbench
-# ** Warning: [4] testbench.vhd(190): (vcom-1207) An abstract literal and an identifier must have a separator between them.
-# vsim -lib work -voptargs=\"+acc\" -debugdb work.testbench 
-# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
-# ** Note: (vopt-143) Recognized 1 FSM in architecture body "multiboot_fsm(behav)".
-# Loading std.standard
-# Loading std.textio(body)
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.numeric_std(body)
-# Loading work.genram_pkg(body)
-# Loading work.wishbone_pkg(body)
-# Loading work.testbench(behav)#1
-# Loading unisim.vcomponents
-# Loading work.xil_multiboot(behav)#1
-# Loading work.multiboot_regs(behav)#1
-# Loading work.multiboot_fsm(behav)#1
-# Loading ieee.std_logic_arith(body)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading unisim.vpkg(body)
-# ** Warning: (vsim-3479) Time unit 'ps' is less than the simulator resolution (1ns).
-#    Time: 0 ns  Iteration: 0  Instance: /testbench/UUT/cmp_icap
-# Loading unisim.icap_spartan6(icap_spartan6_v)#1
-# Loading unisim.sim_config_s6(sim_config_s6_v)#1
-# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.err, and its initial value is not used.
-# Therefore, simulation behavior may occur that is not in compliance with
-# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.err.
-# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.rty, and its initial value is not used.
-# Therefore, simulation behavior may occur that is not in compliance with
-# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.rty.
-# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
-# Therefore, simulation behavior may occur that is not in compliance with
-# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
-# ** Note:  Message :  ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
-#    Time: 1338 ns  Iteration: 2  Instance: /testbench/UUT/cmp_icap
-do run.do
-# ** Warning: (vlib-34) Library already exists at "work".
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Compiling package genram_pkg
-# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
-# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
-# -- Compiling package body genram_pkg
-# -- Loading package genram_pkg
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Loading package genram_pkg
-# -- Compiling package wishbone_pkg
-# -- Compiling package body wishbone_pkg
-# -- Loading package wishbone_pkg
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Compiling entity multiboot_regs
-# -- Compiling architecture behav of multiboot_regs
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Compiling entity multiboot_fsm
-# -- Compiling architecture behav of multiboot_fsm
-# ** Error: ../rtl/multiboot_fsm.vhd(154): Illegal target for signal assignment.
-# ** Error: ../rtl/multiboot_fsm.vhd(154): (vcom-1136) Unknown identifier "icap_busy".
-# ** Error: ../rtl/multiboot_fsm.vhd(367): (vcom-1136) Unknown identifier "icap_busy".
-# ** Error: ../rtl/multiboot_fsm.vhd(367): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
-# ** Error: ../rtl/multiboot_fsm.vhd(386): (vcom-1136) Unknown identifier "icap_busy".
-# ** Error: ../rtl/multiboot_fsm.vhd(386): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
-# ** Error: ../rtl/multiboot_fsm.vhd(436): VHDL Compiler exiting
-# ** Error: /opt/modelsim_10.0d/modeltech/linux/vcom failed.
-# Error in macro ./run.do line 7
-# /opt/modelsim_10.0d/modeltech/linux/vcom failed.
-#     while executing
-# "vcom -explicit -93 "../rtl/multiboot_fsm.vhd""
-do run.do
-# ** Warning: (vlib-34) Library already exists at "work".
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Compiling package genram_pkg
-# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
-# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
-# -- Compiling package body genram_pkg
-# -- Loading package genram_pkg
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Loading package genram_pkg
-# -- Compiling package wishbone_pkg
-# -- Compiling package body wishbone_pkg
-# -- Loading package wishbone_pkg
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Compiling entity multiboot_regs
-# -- Compiling architecture behav of multiboot_regs
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Compiling entity multiboot_fsm
-# -- Compiling architecture behav of multiboot_fsm
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Loading package VCOMPONENTS
-# -- Loading package genram_pkg
-# -- Loading package wishbone_pkg
-# -- Compiling entity xil_multiboot
-# -- Compiling architecture behav of xil_multiboot
-# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec  5 2011
-# -- Loading package STANDARD
-# -- Loading package TEXTIO
-# -- Loading package std_logic_1164
-# -- Loading package NUMERIC_STD
-# -- Loading package genram_pkg
-# -- Loading package wishbone_pkg
-# -- Compiling entity testbench
-# -- Compiling architecture behav of testbench
-# ** Warning: [4] testbench.vhd(190): (vcom-1207) An abstract literal and an identifier must have a separator between them.
-# vsim -lib work -voptargs=\"+acc\" -debugdb work.testbench 
-# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
-# ** Note: (vopt-143) Recognized 1 FSM in architecture body "multiboot_fsm(behav)".
-# Loading std.standard
-# Loading std.textio(body)
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.numeric_std(body)
-# Loading work.genram_pkg(body)
-# Loading work.wishbone_pkg(body)
-# Loading work.testbench(behav)#1
-# Loading unisim.vcomponents
-# Loading work.xil_multiboot(behav)#1
-# Loading work.multiboot_regs(behav)#1
-# Loading work.multiboot_fsm(behav)#1
-# Loading ieee.std_logic_arith(body)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading unisim.vpkg(body)
-# ** Warning: (vsim-3479) Time unit 'ps' is less than the simulator resolution (1ns).
-#    Time: 0 ns  Iteration: 0  Instance: /testbench/UUT/cmp_icap
-# Loading unisim.icap_spartan6(icap_spartan6_v)#1
-# Loading unisim.sim_config_s6(sim_config_s6_v)#1
-# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.err, and its initial value is not used.
-# Therefore, simulation behavior may occur that is not in compliance with
-# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.err.
-# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.rty, and its initial value is not used.
-# Therefore, simulation behavior may occur that is not in compliance with
-# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.rty.
-# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
-# Therefore, simulation behavior may occur that is not in compliance with
-# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
-# ** Note:  Message :  ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
-#    Time: 1338 ns  Iteration: 2  Instance: /testbench/UUT/cmp_icap
--- a/hdl/multiboot/sim/vsim.dbg
+++ b/hdl/multiboot/sim/vsim.dbg
--- a/hdl/multiboot/sim/wave.do
+++ b/hdl/multiboot/sim/wave.do
@@ -2,41 +2,37 @@ onerror {resume}
 quietly WaveActivateNextPane {} 0
 add wave -noupdate /testbench/rst_n
 add wave -noupdate /testbench/clk
-add wave -noupdate -radix hexadecimal /testbench/wb_adr
-add wave -noupdate -radix hexadecimal /testbench/wb_dat_in
-add wave -noupdate -radix hexadecimal /testbench/wb_dat_out
-add wave -noupdate /testbench/wb_cyc
-add wave -noupdate /testbench/wb_stb
-add wave -noupdate /testbench/wb_we
-add wave -noupdate /testbench/wb_ack
-add wave -noupdate /testbench/wb_stall
-add wave -noupdate /testbench/wb_sel
-add wave -noupdate /testbench/transfer
-add wave -noupdate /testbench/write
-add wave -noupdate -radix hexadecimal /testbench/adr
-add wave -noupdate -radix hexadecimal /testbench/dat
 add wave -noupdate /testbench/str
 add wave -noupdate -divider FSM
-add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/gbbar_i
-add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/mbbar_i
-add wave -noupdate /testbench/UUT/cmp_fsm/bootsts_img_o
-add wave -noupdate /testbench/UUT/cmp_fsm/bootsts_valid_o
-add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/icap_dat_i
-add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/icap_dat_o
-add wave -noupdate /testbench/UUT/cmp_fsm/icap_ce_n_o
-add wave -noupdate /testbench/UUT/cmp_fsm/icap_wr_n_o
 add wave -noupdate /testbench/UUT/cmp_fsm/state
-add wave -noupdate -divider ICAP
-add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_icap/I
-add wave -noupdate /testbench/UUT/cmp_icap/prog_b
-add wave -noupdate /testbench/UUT/cmp_icap/init_b
-add wave -noupdate /testbench/UUT/cmp_icap/done_o
 add wave -noupdate /testbench/UUT/cmp_fsm/fsm_cmd
 add wave -noupdate /testbench/UUT/cmp_fsm/fsm_cmd_reg
-add wave -noupdate /testbench/UUT/cmp_icap/BUSY
+add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/fl_addr_o
+add wave -noupdate /testbench/UUT/cmp_fsm/fl_read_o
+add wave -noupdate /testbench/UUT/cmp_fsm/fl_endcmd_o
+add wave -noupdate /testbench/UUT/cmp_fsm/fl_bcnt
+add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/fl_sreg
+add wave -noupdate -divider flash
+add wave -noupdate /testbench/UUT/cmp_flash_ctrl/set_addr_i
+add wave -noupdate /testbench/UUT/cmp_flash_ctrl/write_i
+add wave -noupdate /testbench/UUT/cmp_flash_ctrl/read_i
+add wave -noupdate /testbench/UUT/cmp_flash_ctrl/ready_o
+add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_flash_ctrl/data_i
+add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_flash_ctrl/data_o
+add wave -noupdate /testbench/UUT/cmp_flash_ctrl/spi_cs_n_o
+add wave -noupdate /testbench/UUT/cmp_flash_ctrl/spi_sclk_o
+add wave -noupdate /testbench/UUT/cmp_flash_ctrl/spi_mosi_o
+add wave -noupdate /testbench/UUT/cmp_flash_ctrl/spi_miso_i
+add wave -noupdate /testbench/UUT/cmp_flash_ctrl/state
+add wave -noupdate /testbench/UUT/cmp_flash_ctrl/ready_int
+add wave -noupdate /testbench/UUT/cmp_flash_ctrl/ready_o
+add wave -noupdate /testbench/UUT/cmp_fsm/reg_flr_i
+add wave -noupdate /testbench/UUT/cmp_fsm/reg_flw_i
+add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/reg_flwd_i
+add wave -noupdate /testbench/UUT/cmp_fsm/reg_flwrdy_o
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {1918 ns} 0}
-configure wave -namecolwidth 276
+WaveRestoreCursors {{Cursor 1} {1007 ns} 0}
+configure wave -namecolwidth 298
 configure wave -valuecolwidth 99
 configure wave -justifyvalue left
 configure wave -signalnamewidth 0
@@ -50,4 +46,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {0 ns} {5250 ns}
+WaveRestoreZoom {0 ns} {21 us}
--- a/hdl/multiboot/syn/Makefile
+++ b/hdl/multiboot/syn/Makefile
@@ -43,6 +43,8 @@ FILES := ../top/conv_regs.vhd \
 ../../bicolor_led_ctrl/bicolor_led_ctrl.vhd \
 ../rtl/multiboot_regs.vhd \
 ../rtl/multiboot_fsm.vhd \
+../rtl/spi_master.vhd \
+../rtl/m25p_flash.vhd \
 ../rtl/xil_multiboot.vhd \
 ../../rtm_detector/rtl/rtm_detector.vhd \
 ../../reset_gen/rtl/reset_gen.vhd \

--- a/hdl/multiboot/syn/conv_ttl_blo.bit
+++ b/hdl/multiboot/syn/conv_ttl_blo.bit
--- a/hdl/multiboot/syn/conv_ttl_blo.gise
+++ b/hdl/multiboot/syn/conv_ttl_blo.gise
@@ -72,35 +72,35 @@
  </files>

  <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1377088348" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1377088348">
+    <transform xil_pn:end_ts="1377268031" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1377268031">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
-    <transform xil_pn:end_ts="1377088348" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1377088348">
+    <transform xil_pn:end_ts="1377268031" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1377268031">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
-    <transform xil_pn:end_ts="1377088348" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1377088348">
+    <transform xil_pn:end_ts="1377268031" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1377268031">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
-    <transform xil_pn:end_ts="1377088348" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1377088348">
+    <transform xil_pn:end_ts="1377268031" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1377268031">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
-    <transform xil_pn:end_ts="1377088348" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1377088348">
+    <transform xil_pn:end_ts="1377268031" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1377268031">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
-    <transform xil_pn:end_ts="1377088348" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1377088348">
+    <transform xil_pn:end_ts="1377268031" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1377268031">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
-    <transform xil_pn:end_ts="1377088348" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1377088348">
+    <transform xil_pn:end_ts="1377268031" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1377268031">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
-    <transform xil_pn:end_ts="1377088363" xil_pn:in_ck="6680273903363502638" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1377088348">
+    <transform xil_pn:end_ts="1377268050" xil_pn:in_ck="-7576895194167686066" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1377268031">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
@@ -118,11 +118,11 @@
      <outfile xil_pn:name="webtalk_pn.xml"/>
      <outfile xil_pn:name="xst"/>
    </transform>
-    <transform xil_pn:end_ts="1377088363" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1377088363">
+    <transform xil_pn:end_ts="1377268050" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1377268050">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
-    <transform xil_pn:end_ts="1377088373" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1377088363">
+    <transform xil_pn:end_ts="1377268058" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1377268050">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_ngo"/>
@@ -131,7 +131,7 @@
      <outfile xil_pn:name="conv_ttl_blo.ngd"/>
      <outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/>
    </transform>
-    <transform xil_pn:end_ts="1377088421" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1377088373">
+    <transform xil_pn:end_ts="1377268144" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1377268058">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
@@ -144,7 +144,7 @@
      <outfile xil_pn:name="conv_ttl_blo_summary.xml"/>
      <outfile xil_pn:name="conv_ttl_blo_usage.xml"/>
    </transform>
-    <transform xil_pn:end_ts="1377088474" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1377088421">
+    <transform xil_pn:end_ts="1377268198" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1377268144">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
@@ -158,7 +158,7 @@
      <outfile xil_pn:name="conv_ttl_blo_pad.txt"/>
      <outfile xil_pn:name="conv_ttl_blo_par.xrpt"/>
    </transform>
-    <transform xil_pn:end_ts="1377088509" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1377088474">
+    <transform xil_pn:end_ts="1377268234" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1377268198">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
@@ -169,7 +169,7 @@
      <outfile xil_pn:name="webtalk.log"/>
      <outfile xil_pn:name="webtalk_pn.xml"/>
    </transform>
-    <transform xil_pn:end_ts="1377088474" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1377088464">
+    <transform xil_pn:end_ts="1377268198" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1377268187">
      <status xil_pn:value="FailedRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

--- a/hdl/multiboot/syn/conv_ttl_blo.xise
+++ b/hdl/multiboot/syn/conv_ttl_blo.xise
@@ -146,6 +146,9 @@
    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -302,6 +305,7 @@
    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
@@ -333,315 +337,321 @@
  <libraries/>

  <files>
-    <file xil_pn:name="../top/conv_regs.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../top/conv_ttl_blo.ucf" xil_pn:type="FILE_UCF">
      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
    </file>
-    <file xil_pn:name="../top/conv_ttl_blo.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../top/conv_regs.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
    </file>
-    <file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../top/conv_ttl_blo.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
    </file>
-    <file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
    </file>
-    <file xil_pn:name="../rtl/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
    </file>
-    <file xil_pn:name="../rtl/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../rtl/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
    </file>
-    <file xil_pn:name="../rtl/xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../rtl/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
    </file>
-    <file xil_pn:name="../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../rtl/spi_master.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
    </file>
-    <file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../rtl/m25p_flash.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
    </file>
-    <file xil_pn:name="../../vbcp_wb/rtl/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../rtl/xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
    </file>
-    <file xil_pn:name="../../vbcp_wb/rtl/i2c_slave.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
    </file>
-    <file xil_pn:name="../../vbcp_wb/rtl/vbcp_wb.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../reset_gen/rtl/reset_gen.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
    </file>
-    <file xil_pn:name="../../glitch_filt/rtl/glitch_filt.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../vbcp_wb/rtl/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
    </file>
-    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../vbcp_wb/rtl/i2c_slave.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
    </file>
-    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../vbcp_wb/rtl/vbcp_wb.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
    </file>
-    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../glitch_filt/rtl/glitch_filt.vhd" xil_pn:type="FILE_VHDL">
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    </file>
-    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
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-    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
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-    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
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+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
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+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
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+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
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+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
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+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
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-    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
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+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
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-    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
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+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd" xil_pn:type="FILE_VHDL">
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+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_wfifo.vhd" xil_pn:type="FILE_VHDL">
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+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
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-    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
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-    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
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-    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/common/gc_clk_div.vhd" xil_pn:type="FILE_VHDL">
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-    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
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+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
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-    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
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-    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
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-    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
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-    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="102"/>
    </file>
-    <file xil_pn:name="../top/conv_ttl_blo.ucf" xil_pn:type="FILE_UCF">
+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
      <association xil_pn:name="Implementation" xil_pn:seqID="103"/>
    </file>
+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="104"/>
+    </file>
+    <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="Implementation" xil_pn:seqID="105"/>
+    </file>
  </files>

  <bindings/>

--- a/hdl/multiboot/top/conv_ttl_blo.ucf
+++ b/hdl/multiboot/top/conv_ttl_blo.ucf
@@ -299,16 +299,15 @@ NET "fpga_gap_i" IOSTANDARD = LVCMOS33;
 ###-----------------------------------------------------------------------------
 ###-- ROM memory
 ###-----------------------------------------------------------------------------
-#NET "fpga_prom_cclk_o" LOC = Y20;
-#NET "fpga_prom_cclk_o" IOSTANDARD = "LVCMOS33";
-#NET "fpga_prom_cso_b_n_o" LOC = AA3;
-#NET "fpga_prom_cso_b_n_o" IOSTANDARD = "LVCMOS33";
-#NET "fpga_prom_miso_i" LOC = AA20;
-#NET "fpga_prom_miso_i" IOSTANDARD = "LVCMOS33";
-#NET "fpga_prom_mosi_o" LOC = AB20;
-#NET "fpga_prom_mosi_o" IOSTANDARD = "LVCMOS33";
-#
-#
+NET "fpga_prom_cclk_o" LOC = Y20;
+NET "fpga_prom_cclk_o" IOSTANDARD = "LVCMOS33";
+NET "fpga_prom_cso_b_n_o" LOC = AA3;
+NET "fpga_prom_cso_b_n_o" IOSTANDARD = "LVCMOS33";
+NET "fpga_prom_miso_i" LOC = AA20;
+NET "fpga_prom_miso_i" IOSTANDARD = "LVCMOS33";
+NET "fpga_prom_mosi_o" LOC = AB20;
+NET "fpga_prom_mosi_o" IOSTANDARD = "LVCMOS33";
+
 ###=============================================================================
 ###--          WHITE RABBIT
 ###=============================================================================

--- a/hdl/multiboot/top/conv_ttl_blo.vhd
+++ b/hdl/multiboot/top/conv_ttl_blo.vhd
@@ -98,6 +98,12 @@ entity conv_ttl_blo is
    fpga_ga_i              : in  std_logic_vector(4 downto 0);
    fpga_gap_i             : in  std_logic;

+    -- Flash memory lines
+    fpga_prom_cclk_o       : out std_logic;
+    fpga_prom_cso_b_n_o    : out std_logic;
+    fpga_prom_mosi_o       : out std_logic;
+    fpga_prom_miso_i       : in  std_logic;
+
    -- It allows power sequencing of the 24V rail after a security delay
    mr_n_o                 : out std_logic;

@@ -230,10 +236,16 @@ architecture behav of conv_ttl_blo is
      -- Clock and reset input ports
      clk_i   : in  std_logic;
      rst_n_i : in  std_logic;
-  
+
      -- Wishbone ports
      wbs_i   : in  t_wishbone_slave_in;
-      wbs_o   : out t_wishbone_slave_out
+      wbs_o   : out t_wishbone_slave_out;
+
+      -- SPI ports
+      spi_cs_n_o : out std_logic;
+      spi_sclk_o : out std_logic;
+      spi_mosi_o : out std_logic;
+      spi_miso_i : in  std_logic
    );
  end component xil_multiboot;

@@ -539,7 +551,12 @@ begin
      rst_n_i => rst_n,

      wbs_i   => xbar_master_out(c_slv_multiboot),
-      wbs_o   => xbar_master_in(c_slv_multiboot)
+      wbs_o   => xbar_master_in(c_slv_multiboot),
+
+      spi_cs_n_o => fpga_prom_cso_b_n_o,
+      spi_sclk_o => fpga_prom_cclk_o,
+      spi_mosi_o => fpga_prom_mosi_o,
+      spi_miso_i => fpga_prom_miso_i
    );

  --============================================================================