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Conv TTL Blocking - Gateware
Commit c5f49592 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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reboot and read bootsts working

parent effeaabc
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Showing with 212 additions and 227 deletions
hdl/multiboot/rtl/multiboot_fsm.vhd
View file @ c5f49592
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hdl/multiboot/rtl/xil_multiboot.vhd
View file @ c5f49592
......@@ -130,7 +130,7 @@ architecture behav of xil_multiboot is
icap_dat_i : in std_logic_vector(15 downto 0);
icap_dat_o : out std_logic_vector(15 downto 0);
-- Active low chip- and write-enable outputs for ICAP component
icap_busy_i : in std_logic;
icap_ce_n_o : out std_logic;
icap_wr_n_o : out std_logic
);
......@@ -217,6 +217,7 @@ begin
icap_dat_i => fsm_icap_din,
icap_dat_o => fsm_icap_dout,
icap_busy_i => icap_busy,
icap_ce_n_o => icap_ce_n,
icap_wr_n_o => icap_wr_n
);
......
hdl/multiboot/sim/transcript
View file @ c5f49592
......@@ -42,49 +42,6 @@ do run.do
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_fsm
# -- Compiling architecture behav of multiboot_fsm
# ** Error: ../rtl/multiboot_fsm.vhd(303): (vcom-1136) Unknown identifier "NOP".
# ** Error: ../rtl/multiboot_fsm.vhd(311): Illegal target for signal assignment.
# ** Error: ../rtl/multiboot_fsm.vhd(311): (vcom-1136) Unknown identifier "icap_we_n".
# ** Error: ../rtl/multiboot_fsm.vhd(422): VHDL Compiler exiting
# ** Error: /opt/modelsim_10.0d/modeltech/linux/vcom failed.
# Error in macro ./run.do line 7
# /opt/modelsim_10.0d/modeltech/linux/vcom failed.
# while executing
# "vcom -explicit -93 "../rtl/multiboot_fsm.vhd""
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package wishbone_pkg
# -- Compiling package body wishbone_pkg
# -- Loading package wishbone_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_regs
# -- Compiling architecture behav of multiboot_regs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_fsm
# -- Compiling architecture behav of multiboot_fsm
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
......@@ -107,7 +64,6 @@ do run.do
# ** Warning: [4] testbench.vhd(190): (vcom-1207) An abstract literal and an identifier must have a separator between them.
# vsim -lib work -voptargs=\"+acc\" -debugdb work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "multiboot_fsm(behav)".
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
......@@ -138,6 +94,14 @@ do run.do
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
add wave \
sim:/testbench/UUT/cmp_icap/SIM_CONFIG_S6_INST/reg_addr
add wave \
sim:/testbench/UUT/cmp_icap/SIM_CONFIG_S6_INST/rd_reg_addr
add wave \
sim:/testbench/UUT/rdbootsts \
sim:/testbench/UUT/iprog
find drivers -source -time {1980 ns} -cause sim:/testbench/UUT/cmp_fsm/icap_dat_o
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
......@@ -225,6 +189,10 @@ do run.do
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
add wave \
sim:/testbench/UUT/cmp_icap/SIM_CONFIG_S6_INST/rd_reg_addr
add wave \
sim:/testbench/UUT/cmp_icap/SIM_CONFIG_S6_INST/reg_addr
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
......@@ -281,6 +249,7 @@ do run.do
# ** Warning: [4] testbench.vhd(190): (vcom-1207) An abstract literal and an identifier must have a separator between them.
# vsim -lib work -voptargs=\"+acc\" -debugdb work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "multiboot_fsm(behav)".
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
......@@ -309,11 +278,54 @@ do run.do
# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# ** Error: invalid command name "zoom"
# Error in macro ./run.do line 18
# invalid command name "zoom"
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package wishbone_pkg
# -- Compiling package body wishbone_pkg
# -- Loading package wishbone_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_regs
# -- Compiling architecture behav of multiboot_regs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_fsm
# -- Compiling architecture behav of multiboot_fsm
# ** Error: ../rtl/multiboot_fsm.vhd(154): Illegal target for signal assignment.
# ** Error: ../rtl/multiboot_fsm.vhd(154): (vcom-1136) Unknown identifier "icap_busy".
# ** Error: ../rtl/multiboot_fsm.vhd(367): (vcom-1136) Unknown identifier "icap_busy".
# ** Error: ../rtl/multiboot_fsm.vhd(367): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
# ** Error: ../rtl/multiboot_fsm.vhd(386): (vcom-1136) Unknown identifier "icap_busy".
# ** Error: ../rtl/multiboot_fsm.vhd(386): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
# ** Error: ../rtl/multiboot_fsm.vhd(436): VHDL Compiler exiting
# ** Error: /opt/modelsim_10.0d/modeltech/linux/vcom failed.
# Error in macro ./run.do line 7
# /opt/modelsim_10.0d/modeltech/linux/vcom failed.
# while executing
# "zoom fit"
# "vcom -explicit -93 "../rtl/multiboot_fsm.vhd""
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
......@@ -370,6 +382,7 @@ do run.do
# ** Warning: [4] testbench.vhd(190): (vcom-1207) An abstract literal and an identifier must have a separator between them.
# vsim -lib work -voptargs=\"+acc\" -debugdb work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "multiboot_fsm(behav)".
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
......@@ -400,4 +413,3 @@ do run.do
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
write format wave -window .main_pane.wave.interior.cs.body.pw.wf /home/tstana/Projects/conv-ttl-blo/conv-ttl-blo-gw/hdl/multiboot/sim/wave.do
hdl/multiboot/syn/conv_ttl_blo.gise
View file @ c5f49592
......@@ -72,35 +72,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1377019849" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1377019849">
<transform xil_pn:end_ts="1377088348" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1377088348">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377019849" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1377019849">
<transform xil_pn:end_ts="1377088348" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1377088348">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377019849" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1377019849">
<transform xil_pn:end_ts="1377088348" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1377088348">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377019849" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1377019849">
<transform xil_pn:end_ts="1377088348" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1377088348">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377019849" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1377019849">
<transform xil_pn:end_ts="1377088348" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1377088348">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377019849" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1377019849">
<transform xil_pn:end_ts="1377088348" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1377088348">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377019849" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1377019849">
<transform xil_pn:end_ts="1377088348" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1377088348">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377019866" xil_pn:in_ck="6680273903363502638" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1377019849">
<transform xil_pn:end_ts="1377088363" xil_pn:in_ck="6680273903363502638" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1377088348">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -118,11 +118,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1377019866" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1377019866">
<transform xil_pn:end_ts="1377088363" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1377088363">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377019874" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1377019866">
<transform xil_pn:end_ts="1377088373" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1377088363">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -131,7 +131,7 @@
<outfile xil_pn:name="conv_ttl_blo.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1377019923" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1377019874">
<transform xil_pn:end_ts="1377088421" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1377088373">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -144,7 +144,7 @@
<outfile xil_pn:name="conv_ttl_blo_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1377019976" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1377019923">
<transform xil_pn:end_ts="1377088474" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1377088421">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -158,7 +158,7 @@
<outfile xil_pn:name="conv_ttl_blo_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1377020011" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1377019976">
<transform xil_pn:end_ts="1377088509" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1377088474">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
......@@ -169,7 +169,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1377019976" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1377019965">
<transform xil_pn:end_ts="1377088474" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1377088464">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
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