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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
Commits
6c5f2ce5
Commit
6c5f2ce5
authored
Dec 10, 2012
by
Carlos Gil Soriano
Browse files
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Plain Diff
Improving system testbench. I2C core fully-tested.
parent
67ca4cac
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7 changed files
with
254 additions
and
64 deletions
+254
-64
image1.gise
hdl/IMAGES/image1/project/image1.gise
+3
-3
wave.do
hdl/IMAGES/image1/project/waveform/wave.do
+14
-12
image1_top_tb.vhd
hdl/IMAGES/image1/test/image1_top_tb.vhd
+182
-31
image1_top_tb_pkg.vhd
hdl/IMAGES/image1/test/image1_top_tb_pkg.vhd
+49
-6
i2c_master_driver.txt
hdl/IMAGES/image1/test/log/i2c_master_driver.txt
+0
-6
i2c_regs.vhd
hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd
+2
-2
i2c_master_driver.vhd
hdl/i2c_slave_wb_master/test/i2c_master_driver.vhd
+4
-4
No files found.
hdl/IMAGES/image1/project/image1.gise
View file @
6c5f2ce5
...
...
@@ -60,7 +60,7 @@
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"135
4715194"
xil_pn:in_ck=
"-8135161928864423195"
xil_pn:name=
"TRAN_copyAbstractToPostAbstractSimulation"
xil_pn:start_ts=
"1354715193
"
>
<transform
xil_pn:end_ts=
"135
5158578"
xil_pn:in_ck=
"-8135161928864423195"
xil_pn:name=
"TRAN_copyAbstractToPostAbstractSimulation"
xil_pn:start_ts=
"1355158578
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"../../../../../general-cores/modules/genrams/genram_pkg.vhd"
/>
...
...
@@ -112,7 +112,7 @@
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"135
4715194"
xil_pn:in_ck=
"-8135161928864423195"
xil_pn:name=
"TRAN_copyPostAbstractToPreSimulation"
xil_pn:start_ts=
"1354715194
"
>
<transform
xil_pn:end_ts=
"135
5158578"
xil_pn:in_ck=
"-8135161928864423195"
xil_pn:name=
"TRAN_copyPostAbstractToPreSimulation"
xil_pn:start_ts=
"1355158578
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"../../../../../general-cores/modules/genrams/genram_pkg.vhd"
/>
...
...
@@ -152,7 +152,7 @@
<outfile
xil_pn:name=
"../test/image1_top_tb.vhd"
/>
<outfile
xil_pn:name=
"../test/image1_top_tb_pkg.vhd"
/>
</transform>
<transform
xil_pn:end_ts=
"135
4715195"
xil_pn:in_ck=
"-8135161928864423195"
xil_pn:name=
"TRAN_MSimulateBehavioralModel"
xil_pn:prop_ck=
"889151390353550919"
xil_pn:start_ts=
"1354715194
"
>
<transform
xil_pn:end_ts=
"135
5158579"
xil_pn:in_ck=
"-8135161928864423195"
xil_pn:name=
"TRAN_MSimulateBehavioralModel"
xil_pn:prop_ck=
"889151390353550919"
xil_pn:start_ts=
"1355158578
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"image1_top_tb.fdo"
/>
...
...
hdl/IMAGES/image1/project/waveform/wave.do
View file @
6c5f2ce5
...
...
@@ -43,7 +43,8 @@ add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/inst_i2c
add wave -noupdate /image1_top_tb/uut/inst_i2c_slave/inst_i2c_regs/i2c_master_WB_BASIC_fsm
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/inst_i2c_slave_core/s_CTR0
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/inst_i2c_slave_core/s_LT
add wave -noupdate /image1_top_tb/uut/inst_i2c_slave/s_CTR0_slv
add wave -noupdate -radix hexadecimal -subitemconfig {/image1_top_tb/i2c_driver/rd_data_o(31) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(30) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(29) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(28) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(27) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(26) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(25) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(24) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(23) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(22) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(21) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(20) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(19) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(18) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(17) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(16) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(15) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(14) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(13) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(12) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(11) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(10) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(9) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(8) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(7) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(6) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(5) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(4) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(3) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(2) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(1) {-radix hexadecimal} /image1_top_tb/i2c_driver/rd_data_o(0) {-radix hexadecimal}} /image1_top_tb/i2c_driver/rd_data_o
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/s_CTR0_slv
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/s_LT_slv
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/inst_i2c_slave_core/s_DRXA_slv
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/inst_i2c_slave_core/s_DRXB_slv
...
...
@@ -54,12 +55,12 @@ add wave -noupdate -group i2c /image1_top_tb/uut/inst_i2c_slave/sda_o
add wave -noupdate -group i2c /image1_top_tb/uut/inst_i2c_slave/sda_oen
add wave -noupdate -group i2c /image1_top_tb/uut/inst_i2c_slave/scl_oen
add wave -noupdate -group i2c /image1_top_tb/uut/inst_i2c_slave/scl_o
add wave -noupdate -
expand -
group wb_master_i2c_o /image1_top_tb/uut/inst_i2c_slave/wb_master_stb_o
add wave -noupdate -
expand -
group wb_master_i2c_o /image1_top_tb/uut/inst_i2c_slave/wb_master_cyc_o
add wave -noupdate -
expand -
group wb_master_i2c_o /image1_top_tb/uut/inst_i2c_slave/wb_master_sel_o
add wave -noupdate -
expand -
group wb_master_i2c_o /image1_top_tb/uut/inst_i2c_slave/wb_master_we_o
add wave -noupdate -
expand -
group wb_master_i2c_o /image1_top_tb/uut/inst_i2c_slave/wb_master_data_o
add wave -noupdate -
expand -
group wb_master_i2c_o -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/wb_master_addr_o
add wave -noupdate -group wb_master_i2c_o /image1_top_tb/uut/inst_i2c_slave/wb_master_stb_o
add wave -noupdate -group wb_master_i2c_o /image1_top_tb/uut/inst_i2c_slave/wb_master_cyc_o
add wave -noupdate -group wb_master_i2c_o /image1_top_tb/uut/inst_i2c_slave/wb_master_sel_o
add wave -noupdate -group wb_master_i2c_o /image1_top_tb/uut/inst_i2c_slave/wb_master_we_o
add wave -noupdate -group wb_master_i2c_o /image1_top_tb/uut/inst_i2c_slave/wb_master_data_o
add wave -noupdate -group wb_master_i2c_o -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/wb_master_addr_o
add wave -noupdate -group wb_master_i2c_i -radix hexadecimal /image1_top_tb/uut/inst_i2c_slave/wb_master_data_i
add wave -noupdate -group wb_master_i2c_i /image1_top_tb/uut/inst_i2c_slave/wb_master_ack_i
add wave -noupdate -group wb_master_i2c_i /image1_top_tb/uut/inst_i2c_slave/wb_master_rty_i
...
...
@@ -122,10 +123,10 @@ add wave -noupdate -group wb_slave_multiboot_o /image1_top_tb/uut/inst_multiboot
add wave -noupdate -group wb_slave_multiboot_o /image1_top_tb/uut/inst_multiboot/wb_ack_o
add wave -noupdate -group wb_slave_multiboot_o /image1_top_tb/uut/inst_multiboot/wb_err_o
add wave -noupdate -group wb_slave_multiboot_o /image1_top_tb/uut/inst_multiboot/wb_rty_o
add wave -noupdate -radix hexadecimal
-subitemconfig {/image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_CTR0.OP {-radix hexadecimal} /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_CTR0.PEN {-radix hexadecimal} /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_CTR0.x {-radix hexadecimal}}
/image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_CTR0
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_CTR0
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_CTR1
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_STAT
add wave -noupdate -radix hexadecimal
-subitemconfig {/image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_MBA.ADDR {-radix hexadecimal} /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_MBA.SPI_OPC {-radix hexadecimal} /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_MBA.SPI_OPC(31) {-radix hexadecimal} /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_MBA.SPI_OPC(30) {-radix hexadecimal} /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_MBA.SPI_OPC(29) {-radix hexadecimal} /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_MBA.SPI_OPC(28) {-radix hexadecimal} /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_MBA.SPI_OPC(27) {-radix hexadecimal} /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_MBA.SPI_OPC(26) {-radix hexadecimal} /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_MBA.SPI_OPC(25) {-radix hexadecimal} /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_MBA.SPI_OPC(24) {-radix hexadecimal}}
/image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_MBA
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_MBA
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_GBA
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_MBA_ICAP
add wave -noupdate -radix hexadecimal /image1_top_tb/uut/inst_multiboot/multiboot_regs_inst/s_GBA_ICAP
...
...
@@ -143,13 +144,14 @@ add wave -noupdate -group i2c_driver /image1_top_tb/i2c_driver/scl_master_o
add wave -noupdate /image1_top_tb/i2c_driver/i2c_addr_op_i
add wave -noupdate -radix hexadecimal /image1_top_tb/i2c_driver/wishbone_addr_i
add wave -noupdate -radix hexadecimal /image1_top_tb/i2c_driver/wr_data_i
add wave -noupdate -radix hexadecimal /image1_top_tb/i2c_driver/rd_data_o
add wave -noupdate /image1_top_tb/s_I2C_driver_ctrl
add wave -noupdate /image1_top_tb/s_I2C_driver_ctrl_done
add wave -noupdate -radix hexadecimal /image1_top_tb/i2c_driver/s_DTX
add wave -noupdate -radix hexadecimal /image1_top_tb/s_I2C_regs
add wave -noupdate -radix hexadecimal /image1_top_tb/s_wr_fw_regs_slv
add wave -noupdate -radix hexadecimal /image1_top_tb/s_wr_fw_regs
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {
319579439
3 ps} 0}
WaveRestoreCursors {{Cursor 1} {
149636136
3 ps} 0}
configure wave -namecolwidth 173
configure wave -valuecolwidth 100
configure wave -justifyvalue left
...
...
@@ -164,4 +166,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {
0 ps} {5250 u
s}
WaveRestoreZoom {
1480828541 ps} {1502603265 p
s}
hdl/IMAGES/image1/test/image1_top_tb.vhd
View file @
6c5f2ce5
This diff is collapsed.
Click to expand it.
hdl/IMAGES/image1/test/image1_top_tb_pkg.vhd
View file @
6c5f2ce5
...
...
@@ -125,6 +125,29 @@ package image1_top_tb_pkg is
end
record
;
type
t_wr_fw_reg
is
record
I2C_CTR0
:
work
.
i2c_slave_pkg
.
r_CTR0
;
MULTIBOOT_CTR0
:
work
.
multiboot_pkg
.
r_CTR0
;
MULTIBOOT_MBA
:
work
.
multiboot_pkg
.
r_BAR
;
MULTIBOOT_GBA
:
work
.
multiboot_pkg
.
r_BAR
;
M25P32_FMI
:
work
.
m25p32_pkg
.
r_FMI
;
M25P32_SR_m25p32
:
work
.
m25p32_pkg
.
r_SR_m25p32
;
M25P32_DATA_WRITE
:
STD_LOGIC_VECTOR
(
31
downto
0
);
end
record
;
type
t_wr_fw_reg_slv
is
record
I2C_CTR0
:
STD_LOGIC_VECTOR
(
31
downto
0
);
MULTIBOOT_CTR0
:
STD_LOGIC_VECTOR
(
31
downto
0
);
MULTIBOOT_MBA
:
STD_LOGIC_VECTOR
(
31
downto
0
);
MULTIBOOT_GBA
:
STD_LOGIC_VECTOR
(
31
downto
0
);
M25P32_FMI
:
STD_LOGIC_VECTOR
(
31
downto
0
);
M25P32_SR_m25p32
:
STD_LOGIC_VECTOR
(
31
downto
0
);
M25P32_DATA_WRITE
:
STD_LOGIC_VECTOR
(
31
downto
0
);
end
record
;
constant
c_fpga_en_default
:
t_fpga_en
:
=
(
GEN
=>
'0'
,
BLO
=>
'0'
,
TTL
=>
'0'
,
...
...
@@ -155,17 +178,17 @@ package image1_top_tb_pkg is
--! c_I2C_DTX_addr [0048]
--! c_I2C_DRXA_addr [004C]
--! c_I2C_DRXB_addr [0050]
--! c_MULTIBOOT_CTR0_addr [0080]
--! c_MULTIBOOT_CTR0_addr [0080]
W
--! c_MULTIBOOT_CTR1_addr [0084]
--! c_MULTIBOOT_STAT_addr [0088]
--! c_MULTIBOOT_MBA_addr [008C]
--! c_MULTIBOOT_GBA_addr [0090]
--! c_MULTIBOOT_MBA_addr [008C]
W
--! c_MULTIBOOT_GBA_addr [0090]
W
--! c_MULTIBOOT_MBA_ICAP_addr [0094]
--! c_MULTIBOOT_GBA_ICAP_addr [0098]
--! c_M25P32_FMI_addr [0200]
--! c_M25P32_SR_m25p32_addr [0204]
--! c_M25P32_FMI_addr [0200]
W
--! c_M25P32_SR_m25p32_addr [0204]
W
--! c_M25P32_DATA_READ_addr [0208]
--! c_M25P32_DATA_WRITE_addr [0300 - 03FF]
--! c_M25P32_DATA_WRITE_addr [0300 - 03FF]
W
--! ==================================
constant
c_I2C_CTR0_addr
:
STD_LOGIC_VECTOR
(
15
downto
0
)
...
...
@@ -201,7 +224,27 @@ package image1_top_tb_pkg is
constant
c_M25P32_DATA_WRITE_addr
:
STD_LOGIC_VECTOR
(
15
downto
0
)
:
=
X"0"
&
"001"
&
work
.
m25p32_pkg
.
c_DATA_WRITE_addr
&
"00"
;
function
f_STD_LOGIC_VECTOR
(
fw_regs
:
t_wr_fw_reg
)
return
t_wr_fw_reg_slv
;
end
image1_top_tb_pkg
;
package
body
image1_top_tb_pkg
is
function
f_STD_LOGIC_VECTOR
(
fw_regs
:
t_wr_fw_reg
)
return
t_wr_fw_reg_slv
is
variable
v_return
:
t_wr_fw_reg_slv
;
begin
v_return
.
I2C_CTR0
:
=
f_STD_LOGIC_VECTOR
(
fw_regs
.
I2C_CTR0
);
v_return
.
MULTIBOOT_CTR0
:
=
X"000000"
&
f_STD_LOGIC_VECTOR
(
fw_regs
.
MULTIBOOT_CTR0
);
v_return
.
MULTIBOOT_MBA
:
=
f_STD_LOGIC_VECTOR
(
fw_regs
.
MULTIBOOT_MBA
);
v_return
.
MULTIBOOT_GBA
:
=
f_STD_LOGIC_VECTOR
(
fw_regs
.
MULTIBOOT_GBA
);
v_return
.
M25P32_FMI
:
=
X"00"
&
f_STD_LOGIC_VECTOR
(
fw_regs
.
M25P32_FMI
);
v_return
.
M25P32_SR_m25p32
:
=
X"000000"
&
f_STD_LOGIC_VECTOR
(
fw_regs
.
M25P32_SR_m25p32
);
v_return
.
M25P32_DATA_WRITE
:
=
fw_regs
.
M25P32_DATA_WRITE
;
return
v_return
;
end
f_STD_LOGIC_VECTOR
;
end
image1_top_tb_pkg
;
hdl/IMAGES/image1/test/log/i2c_master_driver.txt
View file @
6c5f2ce5
...
...
@@ -20,9 +20,3 @@
5 OK READ [ADDRESS|0]
6 OK READ [ADDRESS|0]
6 OK READ WISHBONE HIGH
6 OK READ WISHBONE LOW
6 OK READ [ADDRESS|0]
7 OK READ [ADDRESS|0]
7 OK READ WISHBONE HIGH
7 OK READ WISHBONE LOW
7 OK READ [ADDRESS|0]
hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd
View file @
6c5f2ce5
...
...
@@ -214,8 +214,8 @@ begin
when
'1'
=>
s_wb_slave_ack
<=
'1'
;
case
s_wb_slave_addr
is
when
c_CTR0_addr
=>
s_CTR0
<=
f_CTR0
(
wb_slave_data_i
);
--
when c_CTR0_addr =>
--
s_CTR0 <= f_CTR0(wb_slave_data_i);
when
others
=>
s_wb_slave_ack
<=
'0'
;
s_wb_slave_err
<=
'1'
;
...
...
hdl/i2c_slave_wb_master/test/i2c_master_driver.vhd
View file @
6c5f2ce5
...
...
@@ -304,16 +304,16 @@ begin
send_byte
(
wishbone_addr_i
(
7
downto
0
));
check_ack
(
s_test_id
,
"WRITE"
,
WISHBONE_LOW
);
--! 4.- Send DATA0
send_byte
(
wr_data_i
(
7
downto
0
));
send_byte
(
wr_data_i
(
31
downto
24
));
check_ack
(
s_test_id
,
"WRITE"
,
DATA0
);
--! 5.- Send DATA1
send_byte
(
wr_data_i
(
15
downto
8
));
send_byte
(
wr_data_i
(
23
downto
16
));
check_ack
(
s_test_id
,
"WRITE"
,
DATA1
);
--! 6.- Send DATA2
send_byte
(
wr_data_i
(
23
downto
16
));
send_byte
(
wr_data_i
(
15
downto
8
));
check_ack
(
s_test_id
,
"WRITE"
,
DATA2
);
--! 7.- Send DATA3
send_byte
(
wr_data_i
(
31
downto
24
));
send_byte
(
wr_data_i
(
7
downto
0
));
check_ack
(
s_test_id
,
"WRITE"
,
DATA3
);
pause_I2C
;
s_write_done
<=
'1'
;
...
...
Write
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