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Conv TTL Blocking - Gateware
Commit 653b8796 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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write to flash works, made m25p fsm more modular

parent 78ca5d50
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hdl/multiboot/rtl/m25p_flash.vhd
View file @ 653b8796
......@@ -53,16 +53,14 @@ entity m25p_flash is
-- Data readout interface.
-- 1: sets flash read address to addr_i
set_addr_i : in std_logic;
-- start address for read operations
addr_i : in std_logic_vector(23 downto 0);
-- data request: when 1, the controller reads subsequent bytes from
-- the flash, starting from addr_i address.
read_i : in std_logic;
serase_i : in std_logic;
write_i : in std_logic;
read_i : in std_logic;
endcmd_i : in std_logic;
-- read and write data I/O
......@@ -89,17 +87,33 @@ architecture behavioral of m25p_flash is
--============================================================================
type t_state is
(
-- idle state
IDLE,
WE_CMD,
WE_CSEL,
RW_CSEL,
RW_CMD,
ADDR0,
ADDR1,
ADDR2,
-- sector erase cmd address states
SEWECMD,
SEWECSEL,
SECMD,
SECSEL,
SEADDR0,
SEADDR1,
SEADDR2,
-- write cmd states
WWECMD,
WWECSEL,
WCSEL,
WCMD,
WADDR0,
WADDR1,
WADDR2,
WDATA,
-- read cmd states
RCSEL,
RCMD,
RADDR0,
RADDR1,
RADDR2,
DUMMY_XFER,
RDATA,
WDATA
RDATA
);
--============================================================================
......@@ -192,9 +206,6 @@ begin -- rtl
spi_miso_i => spi_miso_i);
-- FSM command vector out of inputs
fsm_cmd <= endcmd_i & write_i & read_i;
-- Main State machine
p_main_fsm : process(clk_sys_i)
begin
......@@ -215,48 +226,49 @@ begin -- rtl
-- state <= IDLE;
else
case state is
-- Idle: wait for "Set Address" or "Read" commands
-- Idle: wait for ERASE, WRITE, READ or END commands (in this order)
when IDLE =>
fsm_cmd_reg <= fsm_cmd;
case fsm_cmd is
when "001" =>
if (send_cmd = '1') then
send_cmd <= '0';
spi_cs <= '0';
spi_start <= '1';
ready_int <= '0';
state <= RW_CSEL;
else
spi_start <= '1';
ready_int <= '0';
state <= RDATA;
end if;
when "010" =>
if (send_cmd = '1') then
send_cmd <= '0';
spi_cs <= '0';
spi_start <= '1';
ready_int <= '0';
state <= WE_CSEL;
else
spi_wdata <= data_i;
spi_start <= '1';
ready_int <= '0';
state <= WDATA;
end if;
when "100" =>
spi_cs <= '0';
send_cmd <= '1';
state <= IDLE;
when others =>
state <= IDLE;
end case;
if (serase_i = '1') then
spi_cs <= '0';
spi_start <= '1';
ready_int <= '0';
state <= SEWECSEL;
elsif (write_i = '1') then
if (send_cmd = '1') then
send_cmd <= '0';
spi_cs <= '0';
spi_start <= '1';
ready_int <= '0';
state <= WWECSEL;
else
spi_wdata <= data_i;
spi_start <= '1';
ready_int <= '0';
state <= WDATA;
end if;
elsif (read_i = '1') then
if (send_cmd = '1') then
send_cmd <= '0';
spi_cs <= '0';
spi_start <= '1';
ready_int <= '0';
state <= RCSEL;
else
spi_start <= '1';
ready_int <= '0';
state <= RDATA;
end if;
elsif (endcmd_i = '1') then
spi_cs <= '0';
send_cmd <= '1';
state <= IDLE;
end if;
--if set_addr_i = '1' then
-- spi_cs <= '0';
-- spi_start <= '1';
-- ready_int <= '0';
-- state <= RW_CSEL;
-- state <= RCSEL;
--elsif read_i = '1' then
-- spi_start <= '1';
-- ready_int <= '0';
......@@ -266,124 +278,242 @@ begin -- rtl
-- ready_int <= '1';
--end if;
--===================================================================
-- Erase sequence
--===================================================================
-- executes a dummy SPI cycle with the SPI chip disabled (CS = 0), to
-- make sure it will correctly interpret the next transfer as a READ
-- command
when WE_CSEL =>
-- make sure it will correctly interpret the next transfer as a
-- WRITE ENABLE command
when SEWECSEL =>
if(spi_ready = '1') then
spi_cs <= '1';
spi_start <= '1';
spi_wdata <= x"06";
state <= WE_CMD;
state <= SEWECMD;
else
spi_start <= '0';
end if;
-- the write enable command is sent during this cycle
when WE_CMD =>
when SEWECMD =>
spi_start <= '0';
if (spi_ready = '1') then
spi_cs <= '0';
spi_start <= '1';
state <= RW_CSEL;
state <= SECSEL;
end if;
-- executes a dummy SPI cycle with the SPI chip disabled (CS = 0), to
-- make sure it will correctly interpret the next transfer as a READ
-- command
when RW_CSEL =>
-- executes a dummy SPI cycle with the SPI chip disabled (CS = 0), to
-- make sure it will correctly interpret the previous WRITE ENABLE
-- transfer
when SECSEL =>
if(spi_ready = '1') then
case fsm_cmd_reg is
when "001" =>
spi_cs <= '1';
spi_start <= '1';
spi_wdata <= x"0b";
state <= RW_CMD;
when "010" =>
spi_cs <= '1';
spi_start <= '1';
spi_wdata <= x"02";
state <= RW_CMD;
when others =>
state <= IDLE;
end case;
spi_cs <= '1';
spi_start <= '1';
spi_wdata <= x"D8";
state <= SECMD;
else
spi_start <= '0';
end if;
-- Send command 0x0B (fast read) or 0x02 (page program)
when RW_CMD =>
-- Send command 0xD8 (sector erase)
when SECMD =>
if(spi_ready = '1') then
state <= ADDR0;
state <= SEADDR0;
spi_wdata <= addr_i(23 downto 16);
spi_start <= '1';
else
spi_start <= '0';
end if;
-- Send 1st byte of read address
when ADDR0 =>
-- Send 1st byte of erase address
when SEADDR0 =>
if(spi_ready = '1') then
state <= ADDR1;
state <= SEADDR1;
spi_wdata <= addr_i(15 downto 8);
spi_start <= '1';
else
spi_start <= '0';
end if;
-- Send 2nd byte of read address
when ADDR1 =>
-- Send 2nd byte of erase address
when SEADDR1 =>
if(spi_ready = '1') then
state <= ADDR2;
state <= SEADDR2;
spi_wdata <= addr_i(7 downto 0);
spi_start <= '1';
else
spi_start <= '0';
end if;
-- Send 3rd byte of read address
when ADDR2 =>
-- Send 3rd byte of erase address
when SEADDR2 =>
if(spi_ready = '1') then
spi_wdata <= data_i;
spi_start <= '1';
state <= IDLE;
else
spi_start <= '0';
end if;
--===================================================================
-- Write sequence
--===================================================================
-- executes a dummy SPI cycle with the SPI chip disabled (CS = 0), to
-- make sure it will correctly interpret the next transfer as a
-- WRITE ENABLE command
when WWECSEL =>
if(spi_ready = '1') then
case fsm_cmd_reg is
when "001" =>
spi_wdata <= "XXXXXXXX";
spi_start <= '1';
state <= DUMMY_XFER;
when "010" =>
spi_wdata <= data_i;
spi_start <= '1';
state <= WDATA;
when others =>
state <= IDLE;
end case;
spi_cs <= '1';
spi_start <= '1';
spi_wdata <= x"06";
state <= WWECMD;
else
spi_start <= '0';
end if;
-- dummy transfer (necessary for fast read mode)
when DUMMY_XFER =>
-- the write enable command is sent during this cycle
when WWECMD =>
spi_start <= '0';
if (spi_ready = '1') then
spi_cs <= '0';
spi_start <= '1';
state <= WCSEL;
end if;
-- executes a dummy SPI cycle with the SPI chip disabled (CS = 0), to
-- make sure it will correctly interpret the previous WRITE ENABLE
-- transfer
when WCSEL =>
if(spi_ready = '1') then
state <= RDATA;
spi_cs <= '1';
spi_start <= '1';
spi_wdata <= x"02";
state <= WCMD;
else
spi_start <= '0';
end if;
-- Data readout: waits for completion of read transaction initiated
-- upon assertion of read_i and returns the byte read data_o.
when RDATA =>
-- Send command 0x02 (page program)
when WCMD =>
if(spi_ready = '1') then
state <= WADDR0;
spi_wdata <= addr_i(23 downto 16);
spi_start <= '1';
else
spi_start <= '0';
end if;
-- Send 1st byte of write address
when WADDR0 =>
if(spi_ready = '1') then
state <= WADDR1;
spi_wdata <= addr_i(15 downto 8);
spi_start <= '1';
else
spi_start <= '0';
end if;
-- Send 2nd byte of write address
when WADDR1 =>
if(spi_ready = '1') then
state <= WADDR2;
spi_wdata <= addr_i(7 downto 0);
spi_start <= '1';
else
spi_start <= '0';
end if;
-- Send 3rd byte of read address
when WADDR2 =>
if(spi_ready = '1') then
spi_wdata <= data_i;
spi_start <= '1';
state <= WDATA;
else
spi_start <= '0';
end if;
-- wait for completion of write cycle
when WDATA =>
spi_start <= '0';
if(spi_ready = '1')then
data_o <= spi_rdata;
ready_int <= '1';
state <= IDLE;
else
ready_int <= '0';
end if;
-- wait for completion of write cycle
when WDATA =>
--===================================================================
-- Read sequence
--===================================================================
-- executes a dummy SPI cycle with the SPI chip disabled (CS = 0), to
-- make sure it will correctly interpret the next transfer as a READ
-- command
when RCSEL =>
if(spi_ready = '1') then
spi_cs <= '1';
spi_start <= '1';
spi_wdata <= x"0B";
state <= RCMD;
else
spi_start <= '0';
end if;
-- Send command 0x0B (page program)
when RCMD =>
if(spi_ready = '1') then
state <= RADDR0;
spi_wdata <= addr_i(23 downto 16);
spi_start <= '1';
else
spi_start <= '0';
end if;
-- Send 1st byte of write address
when RADDR0 =>
if(spi_ready = '1') then
state <= RADDR1;
spi_wdata <= addr_i(15 downto 8);
spi_start <= '1';
else
spi_start <= '0';
end if;
-- Send 2nd byte of write address
when RADDR1 =>
if(spi_ready = '1') then
state <= RADDR2;
spi_wdata <= addr_i(7 downto 0);
spi_start <= '1';
else
spi_start <= '0';
end if;
-- Send 3rd byte of read address
when RADDR2 =>
if(spi_ready = '1') then
spi_wdata <= "XXXXXXXX";
spi_start <= '1';
state <= DUMMY_XFER;
else
spi_start <= '0';
end if;
-- dummy transfer (necessary for fast read mode)
when DUMMY_XFER =>
spi_start <= '0';
if(spi_ready = '1') then
state <= RDATA;
spi_start <= '1';
end if;
-- Data readout: waits for completion of read transaction initiated
-- upon assertion of read_i and returns the byte read data_o.
when RDATA =>
spi_start <= '0';
if(spi_ready = '1')then
data_o <= spi_rdata;
ready_int <= '1';
state <= IDLE;
else
......
hdl/multiboot/rtl/multiboot_fsm.vhd
View file @ 653b8796
......@@ -73,10 +73,10 @@ entity multiboot_fsm is
reg_flwrdy_o : out std_logic;
-- Ports for the external flash controller component
fl_set_addr_o : out std_logic;
fl_addr_o : out std_logic_vector(23 downto 0);
fl_read_o : out std_logic;
fl_serase_o : out std_logic;
fl_write_o : out std_logic;
fl_read_o : out std_logic;
fl_endcmd_o : out std_logic;
fl_data_o : out std_logic_vector(7 downto 0);
fl_data_i : in std_logic_vector(7 downto 0);
......@@ -188,10 +188,10 @@ begin
icap_wr_n_o <= '1';
reg_bootsts_img_o <= (others => '0');
reg_bootsts_valid_o <= '0';
fl_set_addr_o <= '0';
fl_addr_o <= (others => '0');
fl_read_o <= '0';
fl_serase_o <= '0';
fl_write_o <= '0';
fl_read_o <= '0';
fl_endcmd_o <= '0';
fl_bcnt <= (others => '0');
......@@ -203,7 +203,6 @@ begin
case state is
when IDLE =>
--fl_set_addr_o <= '0';
fl_read_o <= '0';
fl_write_o <= '0';
fl_endcmd_o <= '0';
......@@ -216,7 +215,6 @@ begin
when "010000" =>
state <= FLR_DATA;
reg_flrrdy_o <= '0';
-- fl_set_addr_o <= '1';
fl_read_o <= '1';
fl_addr_o <= reg_gbbar_i(23 downto 0);
when "100000" =>
......
hdl/multiboot/rtl/xil_multiboot.vhd
View file @ 653b8796
......@@ -151,10 +151,10 @@ architecture behav of xil_multiboot is
reg_flwrdy_o : out std_logic;
-- Ports for the external flash controller component
fl_set_addr_o : out std_logic;
fl_addr_o : out std_logic_vector(23 downto 0);
fl_read_o : out std_logic;
fl_serase_o : out std_logic;
fl_write_o : out std_logic;
fl_read_o : out std_logic;
fl_endcmd_o : out std_logic;
fl_data_o : out std_logic_vector(7 downto 0);
fl_data_i : in std_logic_vector(7 downto 0);
......@@ -182,16 +182,14 @@ architecture behav of xil_multiboot is
-- Data readout interface.
-- 1: sets flash read address to addr_i
set_addr_i : in std_logic;
-- start address for read operations
addr_i : in std_logic_vector(23 downto 0);
-- data request: when 1, the controller reads subsequent bytes from
-- the flash, starting from addr_i address.
read_i : in std_logic;
serase_i : in std_logic;
write_i : in std_logic;
read_i : in std_logic;
endcmd_i : in std_logic;
-- read data output
......@@ -228,10 +226,10 @@ architecture behav of xil_multiboot is
signal fsm_icap_dout : std_logic_vector(15 downto 0);
-- Flash controller signals
signal fl_set_addr : std_logic;
signal fl_addr : std_logic_vector(23 downto 0);
signal fl_read : std_logic;
signal fl_serase : std_logic;
signal fl_write : std_logic;
signal fl_read : std_logic;
signal fl_data_out : std_logic_vector(7 downto 0);
signal fl_data_in : std_logic_vector(7 downto 0);
signal fl_ready : std_logic;
......@@ -318,10 +316,10 @@ begin
reg_bootsts_img_o => bootsts_img,
reg_bootsts_valid_o => sr_valid,
fl_set_addr_o => fl_set_addr,
fl_addr_o => fl_addr,
fl_read_o => fl_read,
fl_serase_o => fl_serase,
fl_write_o => fl_write,
fl_read_o => fl_read,
fl_endcmd_o => fl_endcmd,
fl_data_i => fl_data_out,
fl_data_o => fl_data_in,
......@@ -347,10 +345,10 @@ begin
(
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
set_addr_i => fl_set_addr,
addr_i => fl_addr,
read_i => fl_read,
serase_i => fl_serase,
write_i => fl_write,
read_i => fl_read,
endcmd_i => fl_endcmd,
data_o => fl_data_out,
data_i => fl_data_in,
......
hdl/multiboot/sim/conv.txt 0 → 100644
View file @ 653b8796
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/multiboot/sim/dump.txt 0 → 100644
View file @ 653b8796
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/multiboot/sim/run.do
View file @ 653b8796
......@@ -3,6 +3,11 @@ vlib work
vcom -explicit -93 "~/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "~/Projects/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
vcom -explicit -93 "~/Projects/M25P64_VHDL_1.0/code/ACDC_check.vhd"
vcom -explicit -93 "~/Projects/M25P64_VHDL_1.0/code/mem_util_pkg.vhd"
vcom -explicit -93 "~/Projects/M25P64_VHDL_1.0/code/Memory_Access.vhd"
vcom -explicit -93 "~/Projects/M25P64_VHDL_1.0/code/Internal_Logic.vhd"
vcom -explicit -93 "~/Projects/M25P64_VHDL_1.0/code/M25P64.vhd"
vcom -explicit -93 "../rtl/spi_master.vhd"
vcom -explicit -93 "../rtl/m25p_flash.vhd"
vcom -explicit -93 "../rtl/multiboot_regs.vhd"
......@@ -10,11 +15,11 @@ vcom -explicit -93 "../rtl/multiboot_fsm.vhd"
vcom -explicit -93 "../rtl/xil_multiboot.vhd"
vcom -explicit -93 "testbench.vhd"
vsim -voptargs="+acc" -debugdb -lib work work.testbench
vsim -voptargs="+acc" -lib work work.testbench
log -r /*
#log -r /*
# add wave *
do wave.do
run 20 us
run 2.5 ms
hdl/multiboot/sim/testbench.vhd
View file @ 653b8796
......@@ -79,6 +79,56 @@ architecture behav of testbench is
);
end component xil_multiboot;
component M25P64 IS
GENERIC ( init_file: string := string'("conv.txt"); -- Init file name
SIZE : positive := 1048576*32; -- 64Mbit
Plength : positive := 256; -- Page length (in Byte)
SSIZE : positive := 524288; -- Sector size (in # of bits)
NB_BPi: positive := 3; -- Number of BPi bits
signature : STD_LOGIC_VECTOR (7 downto 0):="00010110"; -- Electronic signature
manufacturerID : STD_LOGIC_VECTOR (7 downto 0):="00100000"; -- Manufacturer ID
memtype : STD_LOGIC_VECTOR (7 downto 0):="00100000"; -- Memory Type
density : STD_LOGIC_VECTOR (7 downto 0):="00010111"; -- Density
Tc: TIME := 20 ns; -- Minimum Clock period
Tr: TIME := 50 ns; -- Minimum Clock period for read instruction
tSLCH: TIME:= 5 ns; -- notS active setup time (relative to C)
tCHSL: TIME:= 5 ns; -- notS not active hold time
tCH : TIME := 9 ns; -- Clock high time
tCL : TIME := 9 ns; -- Clock low time
tDVCH: TIME:= 2 ns; -- Data in Setup Time
tCHDX: TIME:= 5 ns; -- Data in Hold Time
tCHSH : TIME := 5 ns; -- notS active hold time (relative to C)
tSHCH: TIME := 5 ns; -- notS not active setup time (relative to C)
tSHSL: TIME := 100 ns; -- /S deselect time
tSHQZ: TIME := 8 ns; -- Output disable Time
tCLQV: TIME := 8 ns; -- clock low to output valid
tHLCH: TIME := 5 ns; -- NotHold active setup time
tCHHH: TIME := 5 ns; -- NotHold not active hold time
tHHCH: TIME := 5 ns; -- NotHold not active setup time
tCHHL: TIME := 5 ns; -- NotHold active hold time
tHHQX: TIME := 8 ns; -- NotHold high to Output Low-Z
tHLQZ: TIME := 8 ns; -- NotHold low to Output High-Z
tWHSL: TIME := 20 ns; -- Write protect setup time (SRWD=1)
tSHWL: TIME := 100 ns; -- Write protect hold time (SRWD=1)
tDP: TIME := 3 us; -- notS high to deep power down mode
tRES1: TIME := 30 us; -- notS high to stand-by power mode
tRES2: TIME := 30 us; --
tW: TIME := 15 ms; -- write status register cycle time
tPP: TIME := 0.64 ms; -- page program cycle time
tSE: TIME := 3 sec; -- sector erase cycle time
tBE: TIME := 80 sec; -- bulk erase cycle time
tVSL: TIME := 30 us; -- Vcc(min) to /S low
tPUW: TIME := 1 ms; -- Time delay to write instruction
Vwi: REAL := 2.5 ; -- Write inhibit voltage (unit: V)
Vccmin: REAL := 2.7 ; -- Minimum supply voltage
Vccmax: REAL := 3.6 -- Maximum supply voltage
);
PORT( VCC: IN REAL;
C, D, S, W, HOLD : IN std_logic ;
Q : OUT std_logic);
end component M25P64;
--============================================================================
-- Signal declarations
--============================================================================
......@@ -108,6 +158,7 @@ architecture behav of testbench is
signal cs_n : std_logic;
signal mosi : std_logic;
signal miso : std_logic;
signal fvcc : real;
--==============================================================================
-- architecture begin
......@@ -141,6 +192,21 @@ begin
wb_dat_in <= wbs_out.dat;
wb_stall <= wbs_out.stall;
--============================================================================
-- Instantiate memory
--============================================================================
cmp_mem : M25P64
port map
(
VCC => fvcc,
C => sclk,
D => mosi,
S => cs_n,
W => '1',
HOLD => '1',
Q => miso
);
--============================================================================
-- Clock and reset processes
--============================================================================
......@@ -153,8 +219,10 @@ begin
p_rst : process is
begin
rst_n <= '0';
fvcc <= 0.0;
wait for c_rst_width;
rst_n <= '1';
fvcc <= 3.3;
wait;
end process;
......@@ -170,13 +238,14 @@ begin
write <= '0';
transfer <= '0';
wait for 1500ns;
wait for 1.1 ms;
--wait for 1500ns;
-- Write flash address
wait for 200 ns;
str <= "wr-faddr";
adr <= x"00000008";
dat <= x"00000020";
dat <= x"00000010";
write <= '1';
transfer <= '1';
wait for c_clk_per;
......@@ -192,13 +261,13 @@ begin
wait for c_clk_per;
transfer <= '0';
wait for 6000 ns;
wait for 70000 ns;
-- Write flash data
wait for 200 ns;
str <= "wr-fdata";
adr <= x"00000014";
dat <= x"AA995566";
dat <= x"12344321";
write <= '1';
transfer <= '1';
wait for c_clk_per;
......@@ -214,7 +283,7 @@ begin
wait for c_clk_per;
transfer <= '0';
wait for 6000 ns;
wait for 1 ms;
-- Init flash read
wait for 200 ns;
......@@ -226,7 +295,7 @@ begin
wait for c_clk_per;
transfer <= '0';
wait for 6000 ns;
wait for 70000 ns;
---- Send IPROG
--wait for 200 ns;
......
hdl/multiboot/sim/transcript
View file @ 653b8796
......@@ -8,3 +8,936 @@
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
#
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package wishbone_pkg
# -- Compiling package body wishbone_pkg
# -- Loading package wishbone_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity ACDC_check
# -- Compiling architecture spy of ACDC_check
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package mem_util_pkg
# -- Compiling package body mem_util_pkg
# -- Loading package mem_util_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Memory_Access
# -- Compiling architecture Static_Alloc of Memory_Access
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Internal_Logic
# -- Compiling architecture behavioral of Internal_Logic
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity M25P64
# -- Compiling architecture structure of M25P64
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity spi_master
# -- Compiling architecture behavioral of spi_master
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity m25p_flash
# -- Compiling architecture behavioral of m25p_flash
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_regs
# -- Compiling architecture behav of multiboot_regs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_fsm
# -- Compiling architecture behav of multiboot_fsm
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package VCOMPONENTS
# -- Loading package genram_pkg
# -- Loading package wishbone_pkg
# -- Compiling entity xil_multiboot
# -- Compiling architecture behav of xil_multiboot
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Loading package wishbone_pkg
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "m25p_flash(behavioral)".
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.genram_pkg(body)
# Loading work.wishbone_pkg(body)
# Loading work.testbench(behav)#1
# Loading unisim.vcomponents
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.m25p_flash(behavioral)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# ** Warning: (vsim-3479) Time unit 'ps' is less than the simulator resolution (1ns).
# Time: 0 ns Iteration: 0 Instance: /testbench/UUT/cmp_icap
# Loading unisim.icap_spartan6(icap_spartan6_v)#1
# Loading unisim.sim_config_s6(sim_config_s6_v)#1
# Loading work.mem_util_pkg(body)
# Loading work.m25p64(structure)#1
# Loading work.internal_logic(behavioral)#1
# Loading work.memory_access(static_alloc)#1
# Loading work.acdc_check(spy)#1
# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# Trying to load conv.txt
# ** Error: (vsim-3549) TEXTIO procedure READ(STRING) : Wrong STRING length. Expected 512, found 232.
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
# ** Note: Page program cycle has begun
# Time: 1177248 ns Iteration: 4 Instance: /testbench/cmp_mem/SPI_decoder
# ** Note: Page program cycle is finished
# Time: 1817248 ns Iteration: 0 Instance: /testbench/cmp_mem/SPI_decoder
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package wishbone_pkg
# -- Compiling package body wishbone_pkg
# -- Loading package wishbone_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity ACDC_check
# -- Compiling architecture spy of ACDC_check
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package mem_util_pkg
# -- Compiling package body mem_util_pkg
# -- Loading package mem_util_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Memory_Access
# -- Compiling architecture Static_Alloc of Memory_Access
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Internal_Logic
# -- Compiling architecture behavioral of Internal_Logic
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity M25P64
# -- Compiling architecture structure of M25P64
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity spi_master
# -- Compiling architecture behavioral of spi_master
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity m25p_flash
# -- Compiling architecture behavioral of m25p_flash
# ** Error: ../rtl/m25p_flash.vhd(304): (vcom-1136) Unknown identifier "SECSEL".
# ** Error: ../rtl/m25p_flash.vhd(310): (vcom-1136) Unknown identifier "SECSEL".
# ** Error: ../rtl/m25p_flash.vhd(310): Choice in CASE statement alternative must be locally static.
# ** Error: ../rtl/m25p_flash.vhd(315): (vcom-1136) Unknown identifier "SECMD".
# ** Error: ../rtl/m25p_flash.vhd(321): (vcom-1136) Unknown identifier "SECMD".
# ** Error: ../rtl/m25p_flash.vhd(321): Choice in CASE statement alternative must be locally static.
# ** Error: ../rtl/m25p_flash.vhd(534): VHDL Compiler exiting
# ** Error: /opt/modelsim_10.0d/modeltech/linux/vcom failed.
# Error in macro ./run.do line 12
# /opt/modelsim_10.0d/modeltech/linux/vcom failed.
# while executing
# "vcom -explicit -93 "../rtl/m25p_flash.vhd""
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package wishbone_pkg
# -- Compiling package body wishbone_pkg
# -- Loading package wishbone_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity ACDC_check
# -- Compiling architecture spy of ACDC_check
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package mem_util_pkg
# -- Compiling package body mem_util_pkg
# -- Loading package mem_util_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Memory_Access
# -- Compiling architecture Static_Alloc of Memory_Access
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Internal_Logic
# -- Compiling architecture behavioral of Internal_Logic
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity M25P64
# -- Compiling architecture structure of M25P64
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity spi_master
# -- Compiling architecture behavioral of spi_master
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity m25p_flash
# -- Compiling architecture behavioral of m25p_flash
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_regs
# -- Compiling architecture behav of multiboot_regs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_fsm
# -- Compiling architecture behav of multiboot_fsm
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package VCOMPONENTS
# -- Loading package genram_pkg
# -- Loading package wishbone_pkg
# -- Compiling entity xil_multiboot
# -- Compiling architecture behav of xil_multiboot
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Loading package wishbone_pkg
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Error: ../rtl/xil_multiboot.vhd(362): (vopt-1130) Port "erase_i" of entity "m25p_flash" is not in the component being instantiated.
# ** Error: ../rtl/m25p_flash.vhd(86): Vopt Compiler exiting
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./run.do PAUSED at line 18
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package wishbone_pkg
# -- Compiling package body wishbone_pkg
# -- Loading package wishbone_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity ACDC_check
# -- Compiling architecture spy of ACDC_check
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package mem_util_pkg
# -- Compiling package body mem_util_pkg
# -- Loading package mem_util_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Memory_Access
# -- Compiling architecture Static_Alloc of Memory_Access
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Internal_Logic
# -- Compiling architecture behavioral of Internal_Logic
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity M25P64
# -- Compiling architecture structure of M25P64
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity spi_master
# -- Compiling architecture behavioral of spi_master
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity m25p_flash
# -- Compiling architecture behavioral of m25p_flash
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_regs
# -- Compiling architecture behav of multiboot_regs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_fsm
# -- Compiling architecture behav of multiboot_fsm
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package VCOMPONENTS
# -- Loading package genram_pkg
# -- Loading package wishbone_pkg
# -- Compiling entity xil_multiboot
# -- Compiling architecture behav of xil_multiboot
# ** Error: ../rtl/xil_multiboot.vhd(325): (vcom-1484) Unknown formal identifier "fl_serase_o".
# ** Error: ../rtl/xil_multiboot.vhd(365): (vcom-1035) Formal port "serase_i" has OPEN or no actual associated with it.
# ** Error: ../rtl/xil_multiboot.vhd(417): VHDL Compiler exiting
# ** Error: /opt/modelsim_10.0d/modeltech/linux/vcom failed.
# Error in macro ./run.do line 15
# /opt/modelsim_10.0d/modeltech/linux/vcom failed.
# while executing
# "vcom -explicit -93 "../rtl/xil_multiboot.vhd""
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package wishbone_pkg
# -- Compiling package body wishbone_pkg
# -- Loading package wishbone_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity ACDC_check
# -- Compiling architecture spy of ACDC_check
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package mem_util_pkg
# -- Compiling package body mem_util_pkg
# -- Loading package mem_util_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Memory_Access
# -- Compiling architecture Static_Alloc of Memory_Access
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Internal_Logic
# -- Compiling architecture behavioral of Internal_Logic
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity M25P64
# -- Compiling architecture structure of M25P64
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity spi_master
# -- Compiling architecture behavioral of spi_master
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity m25p_flash
# -- Compiling architecture behavioral of m25p_flash
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_regs
# -- Compiling architecture behav of multiboot_regs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_fsm
# -- Compiling architecture behav of multiboot_fsm
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package VCOMPONENTS
# -- Loading package genram_pkg
# -- Loading package wishbone_pkg
# -- Compiling entity xil_multiboot
# -- Compiling architecture behav of xil_multiboot
# ** Error: ../rtl/xil_multiboot.vhd(366): (vcom-1035) Formal port "serase_i" has OPEN or no actual associated with it.
# ** Error: ../rtl/xil_multiboot.vhd(418): VHDL Compiler exiting
# ** Error: /opt/modelsim_10.0d/modeltech/linux/vcom failed.
# Error in macro ./run.do line 15
# /opt/modelsim_10.0d/modeltech/linux/vcom failed.
# while executing
# "vcom -explicit -93 "../rtl/xil_multiboot.vhd""
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package wishbone_pkg
# -- Compiling package body wishbone_pkg
# -- Loading package wishbone_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity ACDC_check
# -- Compiling architecture spy of ACDC_check
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package mem_util_pkg
# -- Compiling package body mem_util_pkg
# -- Loading package mem_util_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Memory_Access
# -- Compiling architecture Static_Alloc of Memory_Access
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Internal_Logic
# -- Compiling architecture behavioral of Internal_Logic
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity M25P64
# -- Compiling architecture structure of M25P64
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity spi_master
# -- Compiling architecture behavioral of spi_master
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity m25p_flash
# -- Compiling architecture behavioral of m25p_flash
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_regs
# -- Compiling architecture behav of multiboot_regs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_fsm
# -- Compiling architecture behav of multiboot_fsm
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package VCOMPONENTS
# -- Loading package genram_pkg
# -- Loading package wishbone_pkg
# -- Compiling entity xil_multiboot
# -- Compiling architecture behav of xil_multiboot
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Loading package wishbone_pkg
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" work.testbench
# ** Note: (vsim-3812) Design is being optimized...
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "multiboot_fsm(behav)".
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "spi_master(behavioral)".
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "m25p_flash(behavioral)".
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "SIM_CONFIG_S6(SIM_CONFIG_S6_V)".
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.genram_pkg(body)
# Loading work.wishbone_pkg(body)
# Loading work.testbench(behav)#1
# Loading unisim.vcomponents
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.m25p_flash(behavioral)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# ** Warning: (vsim-3479) Time unit 'ps' is less than the simulator resolution (1ns).
# Time: 0 ns Iteration: 0 Instance: /testbench/UUT/cmp_icap
# Loading unisim.icap_spartan6(icap_spartan6_v)#1
# Loading unisim.sim_config_s6(sim_config_s6_v)#1
# Loading work.mem_util_pkg(body)
# Loading work.m25p64(structure)#1
# Loading work.internal_logic(behavioral)#1
# Loading work.memory_access(static_alloc)#1
# Loading work.acdc_check(spy)#1
# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# Trying to load conv.txt
# ** Error: (vsim-3549) TEXTIO procedure READ(STRING) : Wrong STRING length. Expected 512, found 232.
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
# ** Note: Page program cycle has begun
# Time: 1177248 ns Iteration: 4 Instance: /testbench/cmp_mem/SPI_decoder
# ** Note: Page program cycle is finished
# Time: 1817248 ns Iteration: 0 Instance: /testbench/cmp_mem/SPI_decoder
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package wishbone_pkg
# -- Compiling package body wishbone_pkg
# -- Loading package wishbone_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity ACDC_check
# -- Compiling architecture spy of ACDC_check
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package mem_util_pkg
# -- Compiling package body mem_util_pkg
# -- Loading package mem_util_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Memory_Access
# -- Compiling architecture Static_Alloc of Memory_Access
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Internal_Logic
# -- Compiling architecture behavioral of Internal_Logic
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity M25P64
# -- Compiling architecture structure of M25P64
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity spi_master
# -- Compiling architecture behavioral of spi_master
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity m25p_flash
# -- Compiling architecture behavioral of m25p_flash
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_regs
# -- Compiling architecture behav of multiboot_regs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_fsm
# -- Compiling architecture behav of multiboot_fsm
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package VCOMPONENTS
# -- Loading package genram_pkg
# -- Loading package wishbone_pkg
# -- Compiling entity xil_multiboot
# -- Compiling architecture behav of xil_multiboot
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Loading package wishbone_pkg
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Error: ../rtl/xil_multiboot.vhd(360): (vopt-1130) Port "set_addr_i" of entity "m25p_flash" is not in the component being instantiated.
# ** Error: ../rtl/m25p_flash.vhd(86): Vopt Compiler exiting
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./run.do PAUSED at line 18
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package genram_pkg
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# ** Warning: [3] /home/tstana/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd(50): (vcom-1246) Range -1 downto 0 is null.
# -- Compiling package body genram_pkg
# -- Loading package genram_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Compiling package wishbone_pkg
# -- Compiling package body wishbone_pkg
# -- Loading package wishbone_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity ACDC_check
# -- Compiling architecture spy of ACDC_check
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling package mem_util_pkg
# -- Compiling package body mem_util_pkg
# -- Loading package mem_util_pkg
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Memory_Access
# -- Compiling architecture Static_Alloc of Memory_Access
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity Internal_Logic
# -- Compiling architecture behavioral of Internal_Logic
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package mem_util_pkg
# -- Compiling entity M25P64
# -- Compiling architecture structure of M25P64
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity spi_master
# -- Compiling architecture behavioral of spi_master
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity m25p_flash
# -- Compiling architecture behavioral of m25p_flash
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_regs
# -- Compiling architecture behav of multiboot_regs
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity multiboot_fsm
# -- Compiling architecture behav of multiboot_fsm
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package VCOMPONENTS
# -- Loading package genram_pkg
# -- Loading package wishbone_pkg
# -- Compiling entity xil_multiboot
# -- Compiling architecture behav of xil_multiboot
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Loading package genram_pkg
# -- Loading package wishbone_pkg
# -- Compiling entity testbench
# -- Compiling architecture behav of testbench
# vsim -lib work -voptargs=\"+acc\" work.testbench
# ** Note: (vsim-3812) Design is being optimized...
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "multiboot_fsm(behav)".
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "spi_master(behavioral)".
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "m25p_flash(behavioral)".
# ** Note: (vopt-143) Recognized 1 FSM in architecture body "SIM_CONFIG_S6(SIM_CONFIG_S6_V)".
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.genram_pkg(body)
# Loading work.wishbone_pkg(body)
# Loading work.testbench(behav)#1
# Loading unisim.vcomponents
# Loading work.xil_multiboot(behav)#1
# Loading work.multiboot_regs(behav)#1
# Loading work.multiboot_fsm(behav)#1
# Loading work.m25p_flash(behavioral)#1
# Loading work.spi_master(behavioral)#1
# Loading ieee.std_logic_arith(body)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading unisim.vpkg(body)
# ** Warning: (vsim-3479) Time unit 'ps' is less than the simulator resolution (1ns).
# Time: 0 ns Iteration: 0 Instance: /testbench/UUT/cmp_icap
# Loading unisim.icap_spartan6(icap_spartan6_v)#1
# Loading unisim.sim_config_s6(sim_config_s6_v)#1
# Loading work.mem_util_pkg(body)
# Loading work.m25p64(structure)#1
# Loading work.internal_logic(behavioral)#1
# Loading work.memory_access(static_alloc)#1
# Loading work.acdc_check(spy)#1
# ** Warning: (vsim-8684) No drivers exist on out port /testbench/UUT/wbs_o.int, and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /testbench/wbs_out.int.
# ** Error: (vish-4014) No objects found matching '/testbench/UUT/cmp_flash_ctrl/set_addr_i'.
# Executing ONERROR command at macro ./wave.do line 16
# Trying to load conv.txt
# ** Error: (vsim-3549) TEXTIO procedure READ(STRING) : Wrong STRING length. Expected 512, found 232.
# Time: 0 ns Iteration: 0 Instance: /testbench/cmp_mem/Mem_access
# ** Note: Message : ICAP_SPARTAN6 has finished initialization. User can start read/write operation.
# Time: 1338 ns Iteration: 2 Instance: /testbench/UUT/cmp_icap
# ** Note: Page program cycle has begun
# Time: 1177248 ns Iteration: 4 Instance: /testbench/cmp_mem/SPI_decoder
# ** Note: Page program cycle is finished
# Time: 1817248 ns Iteration: 0 Instance: /testbench/cmp_mem/SPI_decoder
write format wave -window .main_pane.wave.interior.cs.body.pw.wf /home/tstana/Projects/conv-ttl-blo/conv-ttl-blo-gw/hdl/multiboot/sim/wave.do
q
hdl/multiboot/sim/vsim_stacktrace.vstf 0 → 100644
View file @ 653b8796
# Current time Mon Sep 2 14:33:01 2013
# ModelSim Stack Trace
# Program = vsim
# Id = "10.1"
# Version = "2011.12"
# Date = "Dec 5 2011"
# Platform = linux
# 0 0xb7715424: '<unknown (@0xb7715424)>'
# 1 0x089f10ca: '<unknown (@0x89f10ca)>'
# 2 0x089acb6b: '<unknown (@0x89acb6b)>'
# 3 0x089ffb2d: '<unknown (@0x89ffb2d)>'
# 4 0x0891484b: '<unknown (@0x891484b)>'
# 5 0x085d8725: '<unknown (@0x85d8725)>'
# 6 0x085d8980: '<unknown (@0x85d8980)>'
# 7 0x085d963d: '<unknown (@0x85d963d)>'
# 8 0x089a6f27: '<unknown (@0x89a6f27)>'
# 9 0x089a86d9: '<unknown (@0x89a86d9)>'
# 10 0x089a9b6d: '<unknown (@0x89a9b6d)>'
# 11 0x089a9fb0: '<unknown (@0x89a9fb0)>'
# 12 0x089aa99a: '<unknown (@0x89aa99a)>'
# 13 0x0875facb: '<unknown (@0x875facb)>'
# 14 0x089e0d0b: '<unknown (@0x89e0d0b)>'
# 15 0x08a0c882: '<unknown (@0x8a0c882)>'
# 16 0x089eeb90: '<unknown (@0x89eeb90)>'
# 17 0x089eee8e: '<unknown (@0x89eee8e)>'
# 18 0x08914d60: '<unknown (@0x8914d60)>'
# 19 0x0845c1f3: '<unknown (@0x845c1f3)>'
# 20 0x0838d719: '<unknown (@0x838d719)>'
# 21 0x08062b46: '<unknown (@0x8062b46)>'
# End of Stack Trace
# Current time Mon Sep 2 14:34:26 2013
# ModelSim Stack Trace
# Program = vsim
# Id = "10.1"
# Version = "2011.12"
# Date = "Dec 5 2011"
# Platform = linux
# 0 0xb77c0424: '<unknown (@0xb77c0424)>'
# 1 0x089f10ca: '<unknown (@0x89f10ca)>'
# 2 0x089acb6b: '<unknown (@0x89acb6b)>'
# 3 0x089ffb2d: '<unknown (@0x89ffb2d)>'
# 4 0x0891484b: '<unknown (@0x891484b)>'
# 5 0x085d8725: '<unknown (@0x85d8725)>'
# 6 0x085d8980: '<unknown (@0x85d8980)>'
# 7 0x085d963d: '<unknown (@0x85d963d)>'
# 8 0x089a6f27: '<unknown (@0x89a6f27)>'
# 9 0x089a86d9: '<unknown (@0x89a86d9)>'
# 10 0x089a9b6d: '<unknown (@0x89a9b6d)>'
# 11 0x089a9fb0: '<unknown (@0x89a9fb0)>'
# 12 0x089aa99a: '<unknown (@0x89aa99a)>'
# 13 0x0875facb: '<unknown (@0x875facb)>'
# 14 0x089e0d0b: '<unknown (@0x89e0d0b)>'
# 15 0x08a0c882: '<unknown (@0x8a0c882)>'
# 16 0x089eeb90: '<unknown (@0x89eeb90)>'
# 17 0x089eee8e: '<unknown (@0x89eee8e)>'
# 18 0x08914d60: '<unknown (@0x8914d60)>'
# 19 0x0845c1f3: '<unknown (@0x845c1f3)>'
# 20 0x0838d719: '<unknown (@0x838d719)>'
# 21 0x08062b46: '<unknown (@0x8062b46)>'
# End of Stack Trace
# Current time Mon Sep 2 14:38:02 2013
# ModelSim Stack Trace
# Program = vsim
# Id = "10.1"
# Version = "2011.12"
# Date = "Dec 5 2011"
# Platform = linux
# 0 0xb779c424: '<unknown (@0xb779c424)>'
# 1 0x089f10ca: '<unknown (@0x89f10ca)>'
# 2 0x089acb6b: '<unknown (@0x89acb6b)>'
# 3 0x089ffb2d: '<unknown (@0x89ffb2d)>'
# 4 0x0891484b: '<unknown (@0x891484b)>'
# 5 0x085d8725: '<unknown (@0x85d8725)>'
# 6 0x085d8980: '<unknown (@0x85d8980)>'
# 7 0x085d963d: '<unknown (@0x85d963d)>'
# 8 0x089a6f27: '<unknown (@0x89a6f27)>'
# 9 0x089a86d9: '<unknown (@0x89a86d9)>'
# 10 0x089a9b6d: '<unknown (@0x89a9b6d)>'
# 11 0x089a9fb0: '<unknown (@0x89a9fb0)>'
# 12 0x089aa99a: '<unknown (@0x89aa99a)>'
# 13 0x0875facb: '<unknown (@0x875facb)>'
# 14 0x089e0d0b: '<unknown (@0x89e0d0b)>'
# 15 0x08a0c882: '<unknown (@0x8a0c882)>'
# 16 0x089eeb90: '<unknown (@0x89eeb90)>'
# 17 0x089eee8e: '<unknown (@0x89eee8e)>'
# 18 0x08914d60: '<unknown (@0x8914d60)>'
# 19 0x0845c1f3: '<unknown (@0x845c1f3)>'
# 20 0x0838d719: '<unknown (@0x838d719)>'
# 21 0x08062b46: '<unknown (@0x8062b46)>'
# End of Stack Trace
# Current time Mon Sep 2 14:41:22 2013
# ModelSim Stack Trace
# Program = vsim
# Id = "10.1"
# Version = "2011.12"
# Date = "Dec 5 2011"
# Platform = linux
# 0 0xb778f424: '<unknown (@0xb778f424)>'
# 1 0x089f10ca: '<unknown (@0x89f10ca)>'
# 2 0x089acb6b: '<unknown (@0x89acb6b)>'
# 3 0x089ffb2d: '<unknown (@0x89ffb2d)>'
# 4 0x0891484b: '<unknown (@0x891484b)>'
# 5 0x085d8725: '<unknown (@0x85d8725)>'
# 6 0x085d8980: '<unknown (@0x85d8980)>'
# 7 0x085d8f39: '<unknown (@0x85d8f39)>'
# 8 0x085dd61b: '<unknown (@0x85dd61b)>'
# 9 0x089a6f27: '<unknown (@0x89a6f27)>'
# 10 0x089a86d9: '<unknown (@0x89a86d9)>'
# 11 0x089a9b6d: '<unknown (@0x89a9b6d)>'
# 12 0x089a9fb0: '<unknown (@0x89a9fb0)>'
# 13 0x089aa99a: '<unknown (@0x89aa99a)>'
# 14 0x0875facb: '<unknown (@0x875facb)>'
# 15 0x089e0d0b: '<unknown (@0x89e0d0b)>'
# 16 0x08a0c882: '<unknown (@0x8a0c882)>'
# 17 0x089eeb90: '<unknown (@0x89eeb90)>'
# 18 0x089eee8e: '<unknown (@0x89eee8e)>'
# 19 0x08914d60: '<unknown (@0x8914d60)>'
# 20 0x0845c1f3: '<unknown (@0x845c1f3)>'
# 21 0x0838d719: '<unknown (@0x838d719)>'
# 22 0x08062b46: '<unknown (@0x8062b46)>'
# End of Stack Trace
hdl/multiboot/sim/wave.do
View file @ 653b8796
......@@ -12,8 +12,7 @@ add wave -noupdate /testbench/UUT/cmp_fsm/fl_read_o
add wave -noupdate /testbench/UUT/cmp_fsm/fl_endcmd_o
add wave -noupdate /testbench/UUT/cmp_fsm/fl_bcnt
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/fl_sreg
add wave -noupdate -divider flash
add wave -noupdate /testbench/UUT/cmp_flash_ctrl/set_addr_i
add wave -noupdate -divider {flash ctrl}
add wave -noupdate /testbench/UUT/cmp_flash_ctrl/write_i
add wave -noupdate /testbench/UUT/cmp_flash_ctrl/read_i
add wave -noupdate /testbench/UUT/cmp_flash_ctrl/ready_o
......@@ -28,10 +27,13 @@ add wave -noupdate /testbench/UUT/cmp_flash_ctrl/ready_int
add wave -noupdate /testbench/UUT/cmp_flash_ctrl/ready_o
add wave -noupdate /testbench/UUT/cmp_fsm/reg_flr_i
add wave -noupdate /testbench/UUT/cmp_fsm/reg_flw_i
add wave -noupdate -radix hexadecimal /testbench/UUT/cmp_fsm/reg_flwd_i
add wave -noupdate -radix hexadecimal -childformat {{/testbench/UUT/cmp_fsm/reg_flwd_i(31) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(30) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(29) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(28) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(27) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(26) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(25) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(24) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(23) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(22) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(21) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(20) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(19) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(18) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(17) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(16) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(15) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(14) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(13) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(12) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(11) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(10) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(9) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(8) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(7) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(6) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(5) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(4) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(3) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(2) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(1) -radix hexadecimal} {/testbench/UUT/cmp_fsm/reg_flwd_i(0) -radix hexadecimal}} -subitemconfig {/testbench/UUT/cmp_fsm/reg_flwd_i(31) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(30) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(29) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(28) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(27) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(26) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(25) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(24) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(23) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(22) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(21) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(20) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(19) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(18) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(17) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(16) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(15) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(14) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(13) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(12) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(11) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(10) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(9) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(8) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(7) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(6) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(5) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(4) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(3) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(2) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(1) {-height 16 -radix hexadecimal} /testbench/UUT/cmp_fsm/reg_flwd_i(0) {-height 16 -radix hexadecimal}} /testbench/UUT/cmp_fsm/reg_flwd_i
add wave -noupdate /testbench/UUT/cmp_fsm/reg_flwrdy_o
add wave -noupdate -divider flash
add wave -noupdate -radix hexadecimal /testbench/cmp_mem/Mem_access/data_to_read
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{/testbench/cmp_mem/Mem_access/p_prog(15) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(16) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(17) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(18) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(19) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(20) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(21) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(22) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(23) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(24) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(25) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(26) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(27) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(28) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(29) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(30) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(31) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(32) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(33) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(34) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(35) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(36) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(37) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(38) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(39) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(40) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(41) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(42) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(43) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(44) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(45) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(46) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(47) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(48) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(49) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(50) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(51) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(52) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(53) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(54) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(55) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(56) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(57) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(58) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(59) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(60) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(61) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(62) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(63) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(64) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(65) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(66) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(67) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(68) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(69) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(70) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(71) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(72) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(73) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(74) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(75) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(76) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(77) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(78) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(79) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(80) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(81) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(82) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(83) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(84) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(85) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(86) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(87) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(88) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(89) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(90) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(91) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(92) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(93) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(94) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(95) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(96) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(97) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(98) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(99) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(100) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(101) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(102) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(103) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(104) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(105) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(106) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(107) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(108) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(109) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(110) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(111) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(112) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(113) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(114) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(115) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(116) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(117) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(118) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(119) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(120) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(121) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(122) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(123) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(124) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(125) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(126) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(127) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(128) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(129) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(130) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(131) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(132) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(133) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(134) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(135) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(136) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(137) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(138) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(139) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(140) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(141) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(142) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(143) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(144) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(145) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(146) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(147) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(148) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(149) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(150) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(151) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(152) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(153) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(154) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(155) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(156) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(157) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(158) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(159) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(160) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(161) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(162) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(163) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(164) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(165) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(166) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(167) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(168) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(169) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(170) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(171) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(172) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(173) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(174) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(175) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(176) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(177) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(178) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(179) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(180) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(181) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(182) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(183) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(184) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(185) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(186) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(187) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(188) -radix hexadecimal} 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{/testbench/cmp_mem/Mem_access/p_prog(236) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(237) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(238) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(239) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(240) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(241) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(242) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(243) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(244) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(245) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(246) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(247) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(248) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(249) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(250) -radix hexadecimal} {/testbench/cmp_mem/Mem_access/p_prog(251) -radix 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/testbench/cmp_mem/Mem_access/p_prog(182) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(183) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(184) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(185) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(186) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(187) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(188) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(189) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(190) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(191) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(192) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(193) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(194) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(195) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(196) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(197) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(198) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(199) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(200) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(201) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(202) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(203) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(204) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(205) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(206) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(207) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(208) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(209) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(210) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(211) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(212) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(213) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(214) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(215) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(216) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(217) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(218) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(219) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(220) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(221) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(222) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(223) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(224) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(225) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(226) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(227) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(228) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(229) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(230) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(231) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(232) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(233) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(234) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(235) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(236) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(237) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(238) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(239) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(240) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(241) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(242) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(243) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(244) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(245) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(246) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(247) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(248) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(249) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(250) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(251) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(252) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(253) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(254) {-height 16 -radix hexadecimal} /testbench/cmp_mem/Mem_access/p_prog(255) {-height 16 -radix hexadecimal}} /testbench/cmp_mem/Mem_access/p_prog
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1007 ns} 0}
WaveRestoreCursors {{Cursor 1} {2202927 ns} 0}
configure wave -namecolwidth 298
configure wave -valuecolwidth 99
configure wave -justifyvalue left
......@@ -46,4 +48,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ns} {21 us}
WaveRestoreZoom {847837 ns} {3472861 ns}
hdl/multiboot/syn/conv_ttl_blo.gise
View file @ 653b8796
......@@ -30,6 +30,7 @@
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_BIN" xil_pn:name="conv_ttl_blo.bin"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="conv_ttl_blo.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="conv_ttl_blo.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="conv_ttl_blo.cmd_log"/>
......@@ -52,6 +53,7 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="conv_ttl_blo.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="conv_ttl_blo.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="conv_ttl_blo_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="conv_ttl_blo_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_map.mrp" xil_pn:subbranch="Map"/>
......@@ -62,6 +64,7 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="conv_ttl_blo_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="conv_ttl_blo_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="conv_ttl_blo_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="conv_ttl_blo_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="conv_ttl_blo_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_xst.xrpt"/>
......@@ -72,35 +75,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1377268031" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1377268031">
<transform xil_pn:end_ts="1378136900" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1378136900">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377268031" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1377268031">
<transform xil_pn:end_ts="1378136900" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1378136900">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377268031" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1377268031">
<transform xil_pn:end_ts="1378136900" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1378136900">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377268031" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1377268031">
<transform xil_pn:end_ts="1378136900" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1378136900">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377268031" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1377268031">
<transform xil_pn:end_ts="1378136900" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1378136900">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377268031" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1377268031">
<transform xil_pn:end_ts="1378136900" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1378136900">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377268031" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1377268031">
<transform xil_pn:end_ts="1378136900" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1378136900">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377268050" xil_pn:in_ck="-7576895194167686066" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1377268031">
<transform xil_pn:end_ts="1378136923" xil_pn:in_ck="-7576895194167686066" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1378136900">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -118,11 +121,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1377268050" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1377268050">
<transform xil_pn:end_ts="1378136923" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1378136923">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377268058" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1377268050">
<transform xil_pn:end_ts="1378136933" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1378136923">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -131,7 +134,7 @@
<outfile xil_pn:name="conv_ttl_blo.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1377268144" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1377268058">
<transform xil_pn:end_ts="1378137024" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1378136933">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -144,7 +147,7 @@
<outfile xil_pn:name="conv_ttl_blo_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1377268198" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1377268144">
<transform xil_pn:end_ts="1378137078" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1378137024">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -158,18 +161,19 @@
<outfile xil_pn:name="conv_ttl_blo_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1377268234" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1377268198">
<transform xil_pn:end_ts="1378137114" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="6587536580693756888" xil_pn:start_ts="1378137078">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.bgn"/>
<outfile xil_pn:name="conv_ttl_blo.bin"/>
<outfile xil_pn:name="conv_ttl_blo.bit"/>
<outfile xil_pn:name="conv_ttl_blo.drc"/>
<outfile xil_pn:name="conv_ttl_blo.ut"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1377268198" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1377268187">
<transform xil_pn:end_ts="1378137078" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1378137067">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/multiboot/syn/conv_ttl_blo.xise
View file @ 653b8796
......@@ -56,7 +56,7 @@
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
......
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