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Conv TTL Blocking - Gateware
Commit 653b8796 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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write to flash works, made m25p fsm more modular

parent 78ca5d50
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hdl/multiboot/rtl/m25p_flash.vhd
View file @ 653b8796
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hdl/multiboot/rtl/multiboot_fsm.vhd
View file @ 653b8796
......@@ -73,10 +73,10 @@ entity multiboot_fsm is
reg_flwrdy_o : out std_logic;
-- Ports for the external flash controller component
fl_set_addr_o : out std_logic;
fl_addr_o : out std_logic_vector(23 downto 0);
fl_read_o : out std_logic;
fl_serase_o : out std_logic;
fl_write_o : out std_logic;
fl_read_o : out std_logic;
fl_endcmd_o : out std_logic;
fl_data_o : out std_logic_vector(7 downto 0);
fl_data_i : in std_logic_vector(7 downto 0);
......@@ -188,10 +188,10 @@ begin
icap_wr_n_o <= '1';
reg_bootsts_img_o <= (others => '0');
reg_bootsts_valid_o <= '0';
fl_set_addr_o <= '0';
fl_addr_o <= (others => '0');
fl_read_o <= '0';
fl_serase_o <= '0';
fl_write_o <= '0';
fl_read_o <= '0';
fl_endcmd_o <= '0';
fl_bcnt <= (others => '0');
......@@ -203,7 +203,6 @@ begin
case state is
when IDLE =>
--fl_set_addr_o <= '0';
fl_read_o <= '0';
fl_write_o <= '0';
fl_endcmd_o <= '0';
......@@ -216,7 +215,6 @@ begin
when "010000" =>
state <= FLR_DATA;
reg_flrrdy_o <= '0';
-- fl_set_addr_o <= '1';
fl_read_o <= '1';
fl_addr_o <= reg_gbbar_i(23 downto 0);
when "100000" =>
......
hdl/multiboot/rtl/xil_multiboot.vhd
View file @ 653b8796
......@@ -151,10 +151,10 @@ architecture behav of xil_multiboot is
reg_flwrdy_o : out std_logic;
-- Ports for the external flash controller component
fl_set_addr_o : out std_logic;
fl_addr_o : out std_logic_vector(23 downto 0);
fl_read_o : out std_logic;
fl_serase_o : out std_logic;
fl_write_o : out std_logic;
fl_read_o : out std_logic;
fl_endcmd_o : out std_logic;
fl_data_o : out std_logic_vector(7 downto 0);
fl_data_i : in std_logic_vector(7 downto 0);
......@@ -182,16 +182,14 @@ architecture behav of xil_multiboot is
-- Data readout interface.
-- 1: sets flash read address to addr_i
set_addr_i : in std_logic;
-- start address for read operations
addr_i : in std_logic_vector(23 downto 0);
-- data request: when 1, the controller reads subsequent bytes from
-- the flash, starting from addr_i address.
read_i : in std_logic;
serase_i : in std_logic;
write_i : in std_logic;
read_i : in std_logic;
endcmd_i : in std_logic;
-- read data output
......@@ -228,10 +226,10 @@ architecture behav of xil_multiboot is
signal fsm_icap_dout : std_logic_vector(15 downto 0);
-- Flash controller signals
signal fl_set_addr : std_logic;
signal fl_addr : std_logic_vector(23 downto 0);
signal fl_read : std_logic;
signal fl_serase : std_logic;
signal fl_write : std_logic;
signal fl_read : std_logic;
signal fl_data_out : std_logic_vector(7 downto 0);
signal fl_data_in : std_logic_vector(7 downto 0);
signal fl_ready : std_logic;
......@@ -318,10 +316,10 @@ begin
reg_bootsts_img_o => bootsts_img,
reg_bootsts_valid_o => sr_valid,
fl_set_addr_o => fl_set_addr,
fl_addr_o => fl_addr,
fl_read_o => fl_read,
fl_serase_o => fl_serase,
fl_write_o => fl_write,
fl_read_o => fl_read,
fl_endcmd_o => fl_endcmd,
fl_data_i => fl_data_out,
fl_data_o => fl_data_in,
......@@ -347,10 +345,10 @@ begin
(
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
set_addr_i => fl_set_addr,
addr_i => fl_addr,
read_i => fl_read,
serase_i => fl_serase,
write_i => fl_write,
read_i => fl_read,
endcmd_i => fl_endcmd,
data_o => fl_data_out,
data_i => fl_data_in,
......
hdl/multiboot/sim/conv.txt 0 → 100644
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hdl/multiboot/sim/dump.txt 0 → 100644
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hdl/multiboot/sim/run.do
View file @ 653b8796
......@@ -3,6 +3,11 @@ vlib work
vcom -explicit -93 "~/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "~/Projects/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
vcom -explicit -93 "~/Projects/M25P64_VHDL_1.0/code/ACDC_check.vhd"
vcom -explicit -93 "~/Projects/M25P64_VHDL_1.0/code/mem_util_pkg.vhd"
vcom -explicit -93 "~/Projects/M25P64_VHDL_1.0/code/Memory_Access.vhd"
vcom -explicit -93 "~/Projects/M25P64_VHDL_1.0/code/Internal_Logic.vhd"
vcom -explicit -93 "~/Projects/M25P64_VHDL_1.0/code/M25P64.vhd"
vcom -explicit -93 "../rtl/spi_master.vhd"
vcom -explicit -93 "../rtl/m25p_flash.vhd"
vcom -explicit -93 "../rtl/multiboot_regs.vhd"
......@@ -10,11 +15,11 @@ vcom -explicit -93 "../rtl/multiboot_fsm.vhd"
vcom -explicit -93 "../rtl/xil_multiboot.vhd"
vcom -explicit -93 "testbench.vhd"
vsim -voptargs="+acc" -debugdb -lib work work.testbench
vsim -voptargs="+acc" -lib work work.testbench
log -r /*
#log -r /*
# add wave *
do wave.do
run 20 us
run 2.5 ms
hdl/multiboot/sim/testbench.vhd
View file @ 653b8796
......@@ -79,6 +79,56 @@ architecture behav of testbench is
);
end component xil_multiboot;
component M25P64 IS
GENERIC ( init_file: string := string'("conv.txt"); -- Init file name
SIZE : positive := 1048576*32; -- 64Mbit
Plength : positive := 256; -- Page length (in Byte)
SSIZE : positive := 524288; -- Sector size (in # of bits)
NB_BPi: positive := 3; -- Number of BPi bits
signature : STD_LOGIC_VECTOR (7 downto 0):="00010110"; -- Electronic signature
manufacturerID : STD_LOGIC_VECTOR (7 downto 0):="00100000"; -- Manufacturer ID
memtype : STD_LOGIC_VECTOR (7 downto 0):="00100000"; -- Memory Type
density : STD_LOGIC_VECTOR (7 downto 0):="00010111"; -- Density
Tc: TIME := 20 ns; -- Minimum Clock period
Tr: TIME := 50 ns; -- Minimum Clock period for read instruction
tSLCH: TIME:= 5 ns; -- notS active setup time (relative to C)
tCHSL: TIME:= 5 ns; -- notS not active hold time
tCH : TIME := 9 ns; -- Clock high time
tCL : TIME := 9 ns; -- Clock low time
tDVCH: TIME:= 2 ns; -- Data in Setup Time
tCHDX: TIME:= 5 ns; -- Data in Hold Time
tCHSH : TIME := 5 ns; -- notS active hold time (relative to C)
tSHCH: TIME := 5 ns; -- notS not active setup time (relative to C)
tSHSL: TIME := 100 ns; -- /S deselect time
tSHQZ: TIME := 8 ns; -- Output disable Time
tCLQV: TIME := 8 ns; -- clock low to output valid
tHLCH: TIME := 5 ns; -- NotHold active setup time
tCHHH: TIME := 5 ns; -- NotHold not active hold time
tHHCH: TIME := 5 ns; -- NotHold not active setup time
tCHHL: TIME := 5 ns; -- NotHold active hold time
tHHQX: TIME := 8 ns; -- NotHold high to Output Low-Z
tHLQZ: TIME := 8 ns; -- NotHold low to Output High-Z
tWHSL: TIME := 20 ns; -- Write protect setup time (SRWD=1)
tSHWL: TIME := 100 ns; -- Write protect hold time (SRWD=1)
tDP: TIME := 3 us; -- notS high to deep power down mode
tRES1: TIME := 30 us; -- notS high to stand-by power mode
tRES2: TIME := 30 us; --
tW: TIME := 15 ms; -- write status register cycle time
tPP: TIME := 0.64 ms; -- page program cycle time
tSE: TIME := 3 sec; -- sector erase cycle time
tBE: TIME := 80 sec; -- bulk erase cycle time
tVSL: TIME := 30 us; -- Vcc(min) to /S low
tPUW: TIME := 1 ms; -- Time delay to write instruction
Vwi: REAL := 2.5 ; -- Write inhibit voltage (unit: V)
Vccmin: REAL := 2.7 ; -- Minimum supply voltage
Vccmax: REAL := 3.6 -- Maximum supply voltage
);
PORT( VCC: IN REAL;
C, D, S, W, HOLD : IN std_logic ;
Q : OUT std_logic);
end component M25P64;
--============================================================================
-- Signal declarations
--============================================================================
......@@ -108,6 +158,7 @@ architecture behav of testbench is
signal cs_n : std_logic;
signal mosi : std_logic;
signal miso : std_logic;
signal fvcc : real;
--==============================================================================
-- architecture begin
......@@ -141,6 +192,21 @@ begin
wb_dat_in <= wbs_out.dat;
wb_stall <= wbs_out.stall;
--============================================================================
-- Instantiate memory
--============================================================================
cmp_mem : M25P64
port map
(
VCC => fvcc,
C => sclk,
D => mosi,
S => cs_n,
W => '1',
HOLD => '1',
Q => miso
);
--============================================================================
-- Clock and reset processes
--============================================================================
......@@ -153,8 +219,10 @@ begin
p_rst : process is
begin
rst_n <= '0';
fvcc <= 0.0;
wait for c_rst_width;
rst_n <= '1';
fvcc <= 3.3;
wait;
end process;
......@@ -170,13 +238,14 @@ begin
write <= '0';
transfer <= '0';
wait for 1500ns;
wait for 1.1 ms;
--wait for 1500ns;
-- Write flash address
wait for 200 ns;
str <= "wr-faddr";
adr <= x"00000008";
dat <= x"00000020";
dat <= x"00000010";
write <= '1';
transfer <= '1';
wait for c_clk_per;
......@@ -192,13 +261,13 @@ begin
wait for c_clk_per;
transfer <= '0';
wait for 6000 ns;
wait for 70000 ns;
-- Write flash data
wait for 200 ns;
str <= "wr-fdata";
adr <= x"00000014";
dat <= x"AA995566";
dat <= x"12344321";
write <= '1';
transfer <= '1';
wait for c_clk_per;
......@@ -214,7 +283,7 @@ begin
wait for c_clk_per;
transfer <= '0';
wait for 6000 ns;
wait for 1 ms;
-- Init flash read
wait for 200 ns;
......@@ -226,7 +295,7 @@ begin
wait for c_clk_per;
transfer <= '0';
wait for 6000 ns;
wait for 70000 ns;
---- Send IPROG
--wait for 200 ns;
......
hdl/multiboot/sim/transcript
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hdl/multiboot/sim/vsim_stacktrace.vstf 0 → 100644
View file @ 653b8796
# Current time Mon Sep 2 14:33:01 2013
# ModelSim Stack Trace
# Program = vsim
# Id = "10.1"
# Version = "2011.12"
# Date = "Dec 5 2011"
# Platform = linux
# 0 0xb7715424: '<unknown (@0xb7715424)>'
# 1 0x089f10ca: '<unknown (@0x89f10ca)>'
# 2 0x089acb6b: '<unknown (@0x89acb6b)>'
# 3 0x089ffb2d: '<unknown (@0x89ffb2d)>'
# 4 0x0891484b: '<unknown (@0x891484b)>'
# 5 0x085d8725: '<unknown (@0x85d8725)>'
# 6 0x085d8980: '<unknown (@0x85d8980)>'
# 7 0x085d963d: '<unknown (@0x85d963d)>'
# 8 0x089a6f27: '<unknown (@0x89a6f27)>'
# 9 0x089a86d9: '<unknown (@0x89a86d9)>'
# 10 0x089a9b6d: '<unknown (@0x89a9b6d)>'
# 11 0x089a9fb0: '<unknown (@0x89a9fb0)>'
# 12 0x089aa99a: '<unknown (@0x89aa99a)>'
# 13 0x0875facb: '<unknown (@0x875facb)>'
# 14 0x089e0d0b: '<unknown (@0x89e0d0b)>'
# 15 0x08a0c882: '<unknown (@0x8a0c882)>'
# 16 0x089eeb90: '<unknown (@0x89eeb90)>'
# 17 0x089eee8e: '<unknown (@0x89eee8e)>'
# 18 0x08914d60: '<unknown (@0x8914d60)>'
# 19 0x0845c1f3: '<unknown (@0x845c1f3)>'
# 20 0x0838d719: '<unknown (@0x838d719)>'
# 21 0x08062b46: '<unknown (@0x8062b46)>'
# End of Stack Trace
# Current time Mon Sep 2 14:34:26 2013
# ModelSim Stack Trace
# Program = vsim
# Id = "10.1"
# Version = "2011.12"
# Date = "Dec 5 2011"
# Platform = linux
# 0 0xb77c0424: '<unknown (@0xb77c0424)>'
# 1 0x089f10ca: '<unknown (@0x89f10ca)>'
# 2 0x089acb6b: '<unknown (@0x89acb6b)>'
# 3 0x089ffb2d: '<unknown (@0x89ffb2d)>'
# 4 0x0891484b: '<unknown (@0x891484b)>'
# 5 0x085d8725: '<unknown (@0x85d8725)>'
# 6 0x085d8980: '<unknown (@0x85d8980)>'
# 7 0x085d963d: '<unknown (@0x85d963d)>'
# 8 0x089a6f27: '<unknown (@0x89a6f27)>'
# 9 0x089a86d9: '<unknown (@0x89a86d9)>'
# 10 0x089a9b6d: '<unknown (@0x89a9b6d)>'
# 11 0x089a9fb0: '<unknown (@0x89a9fb0)>'
# 12 0x089aa99a: '<unknown (@0x89aa99a)>'
# 13 0x0875facb: '<unknown (@0x875facb)>'
# 14 0x089e0d0b: '<unknown (@0x89e0d0b)>'
# 15 0x08a0c882: '<unknown (@0x8a0c882)>'
# 16 0x089eeb90: '<unknown (@0x89eeb90)>'
# 17 0x089eee8e: '<unknown (@0x89eee8e)>'
# 18 0x08914d60: '<unknown (@0x8914d60)>'
# 19 0x0845c1f3: '<unknown (@0x845c1f3)>'
# 20 0x0838d719: '<unknown (@0x838d719)>'
# 21 0x08062b46: '<unknown (@0x8062b46)>'
# End of Stack Trace
# Current time Mon Sep 2 14:38:02 2013
# ModelSim Stack Trace
# Program = vsim
# Id = "10.1"
# Version = "2011.12"
# Date = "Dec 5 2011"
# Platform = linux
# 0 0xb779c424: '<unknown (@0xb779c424)>'
# 1 0x089f10ca: '<unknown (@0x89f10ca)>'
# 2 0x089acb6b: '<unknown (@0x89acb6b)>'
# 3 0x089ffb2d: '<unknown (@0x89ffb2d)>'
# 4 0x0891484b: '<unknown (@0x891484b)>'
# 5 0x085d8725: '<unknown (@0x85d8725)>'
# 6 0x085d8980: '<unknown (@0x85d8980)>'
# 7 0x085d963d: '<unknown (@0x85d963d)>'
# 8 0x089a6f27: '<unknown (@0x89a6f27)>'
# 9 0x089a86d9: '<unknown (@0x89a86d9)>'
# 10 0x089a9b6d: '<unknown (@0x89a9b6d)>'
# 11 0x089a9fb0: '<unknown (@0x89a9fb0)>'
# 12 0x089aa99a: '<unknown (@0x89aa99a)>'
# 13 0x0875facb: '<unknown (@0x875facb)>'
# 14 0x089e0d0b: '<unknown (@0x89e0d0b)>'
# 15 0x08a0c882: '<unknown (@0x8a0c882)>'
# 16 0x089eeb90: '<unknown (@0x89eeb90)>'
# 17 0x089eee8e: '<unknown (@0x89eee8e)>'
# 18 0x08914d60: '<unknown (@0x8914d60)>'
# 19 0x0845c1f3: '<unknown (@0x845c1f3)>'
# 20 0x0838d719: '<unknown (@0x838d719)>'
# 21 0x08062b46: '<unknown (@0x8062b46)>'
# End of Stack Trace
# Current time Mon Sep 2 14:41:22 2013
# ModelSim Stack Trace
# Program = vsim
# Id = "10.1"
# Version = "2011.12"
# Date = "Dec 5 2011"
# Platform = linux
# 0 0xb778f424: '<unknown (@0xb778f424)>'
# 1 0x089f10ca: '<unknown (@0x89f10ca)>'
# 2 0x089acb6b: '<unknown (@0x89acb6b)>'
# 3 0x089ffb2d: '<unknown (@0x89ffb2d)>'
# 4 0x0891484b: '<unknown (@0x891484b)>'
# 5 0x085d8725: '<unknown (@0x85d8725)>'
# 6 0x085d8980: '<unknown (@0x85d8980)>'
# 7 0x085d8f39: '<unknown (@0x85d8f39)>'
# 8 0x085dd61b: '<unknown (@0x85dd61b)>'
# 9 0x089a6f27: '<unknown (@0x89a6f27)>'
# 10 0x089a86d9: '<unknown (@0x89a86d9)>'
# 11 0x089a9b6d: '<unknown (@0x89a9b6d)>'
# 12 0x089a9fb0: '<unknown (@0x89a9fb0)>'
# 13 0x089aa99a: '<unknown (@0x89aa99a)>'
# 14 0x0875facb: '<unknown (@0x875facb)>'
# 15 0x089e0d0b: '<unknown (@0x89e0d0b)>'
# 16 0x08a0c882: '<unknown (@0x8a0c882)>'
# 17 0x089eeb90: '<unknown (@0x89eeb90)>'
# 18 0x089eee8e: '<unknown (@0x89eee8e)>'
# 19 0x08914d60: '<unknown (@0x8914d60)>'
# 20 0x0845c1f3: '<unknown (@0x845c1f3)>'
# 21 0x0838d719: '<unknown (@0x838d719)>'
# 22 0x08062b46: '<unknown (@0x8062b46)>'
# End of Stack Trace
hdl/multiboot/sim/wave.do
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hdl/multiboot/syn/conv_ttl_blo.gise
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......@@ -30,6 +30,7 @@
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_BIN" xil_pn:name="conv_ttl_blo.bin"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="conv_ttl_blo.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="conv_ttl_blo.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="conv_ttl_blo.cmd_log"/>
......@@ -52,6 +53,7 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="conv_ttl_blo.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="conv_ttl_blo.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="conv_ttl_blo.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="conv_ttl_blo_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="conv_ttl_blo_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="conv_ttl_blo_map.mrp" xil_pn:subbranch="Map"/>
......@@ -62,6 +64,7 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="conv_ttl_blo_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="conv_ttl_blo_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="conv_ttl_blo_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="conv_ttl_blo_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="conv_ttl_blo_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="conv_ttl_blo_xst.xrpt"/>
......@@ -72,35 +75,35 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1377268031" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1377268031">
<transform xil_pn:end_ts="1378136900" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1378136900">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377268031" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1377268031">
<transform xil_pn:end_ts="1378136900" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1378136900">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377268031" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1377268031">
<transform xil_pn:end_ts="1378136900" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1378136900">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377268031" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1377268031">
<transform xil_pn:end_ts="1378136900" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1378136900">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377268031" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1377268031">
<transform xil_pn:end_ts="1378136900" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1378136900">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377268031" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1377268031">
<transform xil_pn:end_ts="1378136900" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1378136900">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377268031" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1377268031">
<transform xil_pn:end_ts="1378136900" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1378136900">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377268050" xil_pn:in_ck="-7576895194167686066" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1377268031">
<transform xil_pn:end_ts="1378136923" xil_pn:in_ck="-7576895194167686066" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1378136900">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -118,11 +121,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1377268050" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1377268050">
<transform xil_pn:end_ts="1378136923" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1378136923">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1377268058" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1377268050">
<transform xil_pn:end_ts="1378136933" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1378136923">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -131,7 +134,7 @@
<outfile xil_pn:name="conv_ttl_blo.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1377268144" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1377268058">
<transform xil_pn:end_ts="1378137024" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1378136933">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -144,7 +147,7 @@
<outfile xil_pn:name="conv_ttl_blo_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1377268198" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1377268144">
<transform xil_pn:end_ts="1378137078" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1378137024">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -158,18 +161,19 @@
<outfile xil_pn:name="conv_ttl_blo_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1377268234" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1377268198">
<transform xil_pn:end_ts="1378137114" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="6587536580693756888" xil_pn:start_ts="1378137078">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.bgn"/>
<outfile xil_pn:name="conv_ttl_blo.bin"/>
<outfile xil_pn:name="conv_ttl_blo.bit"/>
<outfile xil_pn:name="conv_ttl_blo.drc"/>
<outfile xil_pn:name="conv_ttl_blo.ut"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1377268198" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1377268187">
<transform xil_pn:end_ts="1378137078" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1378137067">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/multiboot/syn/conv_ttl_blo.xise
View file @ 653b8796
......@@ -56,7 +56,7 @@
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
......
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